From patchwork Mon Mar 23 23:33:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kun Yi X-Patchwork-Id: 11454219 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 263F692A for ; Mon, 23 Mar 2020 23:34:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E87EF206C3 for ; Mon, 23 Mar 2020 23:34:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="wLb+Ar23" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727064AbgCWXeL (ORCPT ); Mon, 23 Mar 2020 19:34:11 -0400 Received: from mail-pj1-f74.google.com ([209.85.216.74]:58919 "EHLO mail-pj1-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726203AbgCWXeL (ORCPT ); Mon, 23 Mar 2020 19:34:11 -0400 Received: by mail-pj1-f74.google.com with SMTP id r42so1079431pjb.8 for ; Mon, 23 Mar 2020 16:34:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=7LjvC3q1nQ+wxDAghAOLNAACAxWDARaR3snavvUSAi8=; b=wLb+Ar23/buIg4Ub7/nPgCT0wO4zmPeZltTSHw5Zn4FqJcxfGNQEWdYyORIkZcst/N e/hm4zsVffMwutoplcZYtlHaTP/oyGNdDkfgTGvvfCorZpUen/RFVAISawsfMB9zM/7l gsLWnQFqwSKtKqj969W8NzzgdwekZUwjXkfucKdm1coItrb8KC2zj9/2Ypi7uoToKKgB 5/Wi5COJFGtAPr1OrjD9qGxqTCH/l5YKlTeAztYwcKybcJIxJzickx93roYcr9KKywiv qm9LP3or00H9uk+k7puiBBJDl2BvAMrIWaRT13Bwz8X+LrrV66JJ/PDzQMW8NhA7A+lH 3c+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=7LjvC3q1nQ+wxDAghAOLNAACAxWDARaR3snavvUSAi8=; b=F60+CkCctJ1egnf4okfQY6Hw6bT/ELEKJJJBa9ClwS4XSB4XXdfF0MXO1PoaC4Xoy6 CA/oKJTzSPiL1SJnK52+LS//nMgdB1QNfak7UZQT+HPG39KSWquQZagXPchaKrQg8t54 uNGElUEfJpTpSUq0F8V+Z7Xd1wjVJQ3O85LzHAt8G0cUBc+F3jw1LhHnrpw2Wqu8NEfC 4mqa/iEv7JMDzm5SngVQHoMZJTwr/fUchWX+PbnxXDGgsu16+O0HYBiX1UPMAJEthT5y 5jRKSr3JcnIxJrQ83Torkj7pMGmy4mp36yDPNG9PaKLwwhfif3mU6m6Oig6boIIumSIn pzpA== X-Gm-Message-State: ANhLgQ3/Pgz+kOPSQUFf1WXrtiFc0/ZGJUEGYoEoYzFtF1c9ryDcwDX6 BEn/0qOrt/yERtwqa08KV/59zS+DmA== X-Google-Smtp-Source: ADFU+vsh5JhTusoxMMTwS+sSpolGEOagYn/0tAeB/e0HZaus0NN9pXFyTATbwzTZ75aV4NQe33eUkguGbA== X-Received: by 2002:a63:b146:: with SMTP id g6mr24906945pgp.85.1585006449264; Mon, 23 Mar 2020 16:34:09 -0700 (PDT) Date: Mon, 23 Mar 2020 16:33:52 -0700 In-Reply-To: <20200323233354.239365-1-kunyi@google.com> Message-Id: <20200323233354.239365-2-kunyi@google.com> Mime-Version: 1.0 References: <20200323233354.239365-1-kunyi@google.com> X-Mailer: git-send-email 2.25.1.696.g5e7596f4ac-goog Subject: [PATCH linux hwmon-next v2 1/3] hwmon: (sbtsi) Add basic support for SB-TSI sensors From: Kun Yi To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com Cc: Kun Yi , openbmc@lists.ozlabs.org, joel@jms.id.au, linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible interface that reports AMD SoC's Ttcl (normalized temperature), and resembles a typical 8-pin remote temperature sensor's I2C interface to BMC. This commit adds basic support using this interface to read CPU temperature, and read/write high/low CPU temp thresholds. To instantiate this driver on an AMD CPU with SB-TSI support, the i2c bus number would be the bus connected from the board management controller (BMC) to the CPU. The i2c address is specified in Section 6.3.1 of the spec [1]: The SB-TSI address is normally 98h for socket 0 and 90h for socket 1, but it could vary based on hardware address select pins. [1]: https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf Test status: tested reading temp1_input, and reading/writing temp1_max/min. Signed-off-by: Kun Yi Change-Id: I85ec65a57e8d73d7343aa9e250860ec85bfa79e5 --- drivers/hwmon/Kconfig | 10 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/sbtsi_temp.c | 261 +++++++++++++++++++++++++++++++++++++ 3 files changed, 272 insertions(+) create mode 100644 drivers/hwmon/sbtsi_temp.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 05a30832c6ba..9585dcd01d1b 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1412,6 +1412,16 @@ config SENSORS_RASPBERRYPI_HWMON This driver can also be built as a module. If so, the module will be called raspberrypi-hwmon. +config SENSORS_SBTSI + tristate "Emulated SB-TSI temperature sensor" + depends on I2C + help + If you say yes here you get support for emulated temperature + sensors on AMD SoCs with SB-TSI interface connected to a BMC device. + + This driver can also be built as a module. If so, the module will + be called sbtsi_temp. + config SENSORS_SHT15 tristate "Sensiron humidity and temperature sensors. SHT15 and compat." depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index b0b9c8e57176..cd109f003ce4 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -152,6 +152,7 @@ obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o obj-$(CONFIG_SENSORS_S3C) += s3c-hwmon.o +obj-$(CONFIG_SENSORS_SBTSI) += sbtsi_temp.o obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o obj-$(CONFIG_SENSORS_SCH5636) += sch5636.o diff --git a/drivers/hwmon/sbtsi_temp.c b/drivers/hwmon/sbtsi_temp.c new file mode 100644 index 000000000000..cc452cb29c2c --- /dev/null +++ b/drivers/hwmon/sbtsi_temp.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sbtsi_temp.c - hwmon driver for a SBI Temperature Sensor Interface (SB-TSI) + * compliant AMD SoC temperature device. + * + * Copyright (c) 2020, Google Inc. + * Copyright (c) 2020, Kun Yi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SB-TSI registers only support SMBus byte data access. "_INT" registers are + * the integer part of a temperature value or limit, and "_DEC" registers are + * corresponding decimal parts. + */ +#define SBTSI_REG_TEMP_INT 0x01 /* RO */ +#define SBTSI_REG_STATUS 0x02 /* RO */ +#define SBTSI_REG_CONFIG 0x03 /* RO */ +#define SBTSI_REG_TEMP_HIGH_INT 0x07 /* RW */ +#define SBTSI_REG_TEMP_LOW_INT 0x08 /* RW */ +#define SBTSI_REG_TEMP_DEC 0x10 /* RW */ +#define SBTSI_REG_TEMP_HIGH_DEC 0x13 /* RW */ +#define SBTSI_REG_TEMP_LOW_DEC 0x14 /* RW */ +#define SBTSI_REG_REV 0xFF /* RO */ + +#define SBTSI_CONFIG_READ_ORDER_SHIFT 5 + +#define SBTSI_TEMP_MIN 0 +#define SBTSI_TEMP_MAX 255875 +#define SBTSI_REV_MAX_VALID_ID 4 + +/* Each client has this additional data */ +struct sbtsi_data { + struct i2c_client *client; + struct mutex lock; +}; + +/* + * From SB-TSI spec: CPU temperature readings and limit registers encode the + * temperature in increments of 0.125 from 0 to 255.875. The "high byte" + * register encodes the base-2 of the integer portion, and the upper 3 bits of + * the "low byte" encode in base-2 the decimal portion. + * + * e.g. INT=0x19, DEC=0x20 represents 25.125 degrees Celsius + * + * Therefore temperature in millidegree Celsius = + * (INT + DEC / 256) * 1000 = (INT * 8 + DEC / 32) * 125 + */ +static inline int sbtsi_reg_to_mc(s32 integer, s32 decimal) +{ + return ((integer << 3) + (decimal >> 5)) * 125; +} + +/* + * Inversely, given temperature in millidegree Celsius + * INT = (TEMP / 125) / 8 + * DEC = ((TEMP / 125) % 8) * 32 + * Caller have to make sure temp doesn't exceed 255875, the max valid value. + */ +static inline void sbtsi_mc_to_reg(s32 temp, u8 *integer, u8 *decimal) +{ + temp /= 125; + *integer = temp >> 3; + *decimal = (temp & 0x7) << 5; +} + +static int sbtsi_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct sbtsi_data *data = dev_get_drvdata(dev); + s32 temp_int, temp_dec; + int err, reg_int, reg_dec; + u8 read_order; + + if (type != hwmon_temp) + return -EINVAL; + + read_order = 0; + switch (attr) { + case hwmon_temp_input: + /* + * ReadOrder bit specifies the reading order of integer and + * decimal part of CPU temp for atomic reads. If bit == 0, + * reading integer part triggers latching of the decimal part, + * so integer part should be read first. If bit == 1, read + * order should be reversed. + */ + err = i2c_smbus_read_byte_data(data->client, SBTSI_REG_CONFIG); + if (err < 0) + return err; + + read_order = (u8)err & BIT(SBTSI_CONFIG_READ_ORDER_SHIFT); + reg_int = SBTSI_REG_TEMP_INT; + reg_dec = SBTSI_REG_TEMP_DEC; + break; + case hwmon_temp_max: + reg_int = SBTSI_REG_TEMP_HIGH_INT; + reg_dec = SBTSI_REG_TEMP_HIGH_DEC; + break; + case hwmon_temp_min: + reg_int = SBTSI_REG_TEMP_LOW_INT; + reg_dec = SBTSI_REG_TEMP_LOW_DEC; + break; + default: + return -EINVAL; + } + + if (read_order == 0) { + temp_int = i2c_smbus_read_byte_data(data->client, reg_int); + temp_dec = i2c_smbus_read_byte_data(data->client, reg_dec); + } else { + temp_dec = i2c_smbus_read_byte_data(data->client, reg_dec); + temp_int = i2c_smbus_read_byte_data(data->client, reg_int); + } + + if (temp_int < 0) + return temp_int; + if (temp_dec < 0) + return temp_dec; + + *val = sbtsi_reg_to_mc(temp_int, temp_dec); + + return 0; +} + +static int sbtsi_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct sbtsi_data *data = dev_get_drvdata(dev); + int reg_int, reg_dec, err; + u8 temp_int, temp_dec; + + if (type != hwmon_temp) + return -EINVAL; + + switch (attr) { + case hwmon_temp_max: + reg_int = SBTSI_REG_TEMP_HIGH_INT; + reg_dec = SBTSI_REG_TEMP_HIGH_DEC; + break; + case hwmon_temp_min: + reg_int = SBTSI_REG_TEMP_LOW_INT; + reg_dec = SBTSI_REG_TEMP_LOW_DEC; + break; + default: + return -EINVAL; + } + + val = clamp_val(val, SBTSI_TEMP_MIN, SBTSI_TEMP_MAX); + mutex_lock(&data->lock); + sbtsi_mc_to_reg(val, &temp_int, &temp_dec); + err = i2c_smbus_write_byte_data(data->client, reg_int, temp_int); + if (err) + goto exit; + + err = i2c_smbus_write_byte_data(data->client, reg_dec, temp_dec); +exit: + mutex_unlock(&data->lock); + return err; +} + +static umode_t sbtsi_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + return 0444; + case hwmon_temp_min: + return 0644; + case hwmon_temp_max: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info *sbtsi_info[] = { + HWMON_CHANNEL_INFO(chip, + HWMON_C_REGISTER_TZ), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX), + NULL +}; + +static const struct hwmon_ops sbtsi_hwmon_ops = { + .is_visible = sbtsi_is_visible, + .read = sbtsi_read, + .write = sbtsi_write, +}; + +static const struct hwmon_chip_info sbtsi_chip_info = { + .ops = &sbtsi_hwmon_ops, + .info = sbtsi_info, +}; + +static int sbtsi_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device *hwmon_dev; + struct sbtsi_data *data; + + data = devm_kzalloc(dev, sizeof(struct sbtsi_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + mutex_init(&data->lock); + + dev_set_drvdata(dev, data); + + hwmon_dev = + devm_hwmon_device_register_with_info(dev, client->name, data, + &sbtsi_chip_info, NULL); + + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +static const struct i2c_device_id sbtsi_id[] = { + {"sbtsi", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, sbtsi_id); + +static const struct of_device_id __maybe_unused sbtsi_of_match[] = { + { + .compatible = "amd,sbtsi", + }, + { }, +}; +MODULE_DEVICE_TABLE(of, sbtsi_of_match); + +static struct i2c_driver sbtsi_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "sbtsi", + .of_match_table = of_match_ptr(sbtsi_of_match), + }, + .probe = sbtsi_probe, + .id_table = sbtsi_id, +}; + +module_i2c_driver(sbtsi_driver); + +MODULE_AUTHOR("Kun Yi "); +MODULE_DESCRIPTION("Hwmon driver for AMD SB-TSI emulated sensor"); +MODULE_LICENSE("GPL"); From patchwork Mon Mar 23 23:33:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kun Yi X-Patchwork-Id: 11454225 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D1B6E139A for ; Mon, 23 Mar 2020 23:34:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B2CF120719 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=tXPEW76sKJjaPQGOZOimHJEP26LY2RMe5WtADrdJadU=; b=ObWQOR+wvgUYbFLfd8T5QMcNRb53qxJcHZ1qJKXuDoA/RdTv/0VSBoI2a2gqV1ucSx R8WTW5quo10CMGksd3uz4EWgZ8e5nWzGgciUB1QZ8XKXkpG8XzuUHwdLXHyT2/FoFZCQ nk+eSZTgIBAyIm6BaFLyqkOSv2VllIovp1rVmkVZn10xFIoxa0azsNhiD7ST7EUBK23y z1DTl5BMIybon9fNCeSPe9L2zwMo0RHG7uRrtGhgbdnlqVvq2GcedIZZfOx4DeU76+Cg VyNc71iObPoEnSOH6XxuIJmPmHIOh6VqYySMJfXaQAbybjBIbT7Tyh+2XwoBWEw95Fee WyCw== X-Gm-Message-State: ANhLgQ3/auikJwva7hANxnU7tmKLh3GwWsODL7gXbn9ZSWIKmXiV+4QV EMT0EbADuUJiOMT55ug2+VzTrL9pTg== X-Google-Smtp-Source: ADFU+vuLxlD+2uO92bRrRaRHd0gjs4zp+jDXUXilAFiN/Eux1EFzVf5TdgZWCwGXv1Yhg1tiwl6PAvstYA== X-Received: by 2002:ab0:698e:: with SMTP id t14mr16110287uaq.53.1585006453359; Mon, 23 Mar 2020 16:34:13 -0700 (PDT) Date: Mon, 23 Mar 2020 16:33:53 -0700 In-Reply-To: <20200323233354.239365-1-kunyi@google.com> Message-Id: <20200323233354.239365-3-kunyi@google.com> Mime-Version: 1.0 References: <20200323233354.239365-1-kunyi@google.com> X-Mailer: git-send-email 2.25.1.696.g5e7596f4ac-goog Subject: [PATCH linux hwmon-next v2 2/3] hwmon: (sbtsi) Add documentation From: Kun Yi To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com Cc: Kun Yi , openbmc@lists.ozlabs.org, joel@jms.id.au, linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Document the SB-TSI sensor interface driver. Signed-off-by: Kun Yi Change-Id: I4b086a124d1d94a516386b0d2ff1cd7180b1dac1 --- Documentation/hwmon/sbtsi_temp.rst | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/hwmon/sbtsi_temp.rst diff --git a/Documentation/hwmon/sbtsi_temp.rst b/Documentation/hwmon/sbtsi_temp.rst new file mode 100644 index 000000000000..9f0f197c8aa2 --- /dev/null +++ b/Documentation/hwmon/sbtsi_temp.rst @@ -0,0 +1,40 @@ +Kernel driver sbtsi_temp +================== + +Supported hardware: + + * Sideband interface (SBI) Temperature Sensor Interface (SB-TSI) + compliant AMD SoC temperature device. + + Prefix: 'sbtsi_temp' + + Addresses scanned: This driver doesn't support address scanning. + + To instantiate this driver on an AMD CPU with SB-TSI + support, the i2c bus number would be the bus connected from the board + management controller (BMC) to the CPU. The i2c address is specified in + Section 6.3.1 of the SoC register reference: The SB-TSI address is normally + 98h for socket 0 and 90h for socket 1, but it could vary based on hardware + address select pins. + + Datasheet: The SB-TSI interface and protocol is available as part of + the open source SoC register reference at: + + https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf + + The Advanced Platform Management Link (APML) Specification is + available at: + + http://developer.amd.com/wordpress/media/2012/10/41918.pdf + +Author: Kun Yi + +Description +----------- + +The SBI temperature sensor interface (SB-TSI) is an emulation of the software +and physical interface of a typical 8-pin remote temperature sensor (RTS) on +AMD SoCs. It implements one temperature sensor with readings and limit +registers encode the temperature in increments of 0.125 from 0 to 255.875. +Limits can be set through the writable thresholds, and if reached will trigger +corresponding alert signals. From patchwork Mon Mar 23 23:33:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kun Yi X-Patchwork-Id: 11454221 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6FCB192A for ; Mon, 23 Mar 2020 23:34:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F46720780 for ; Mon, 23 Mar 2020 23:34:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="IHAJPl2o" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727129AbgCWXeS (ORCPT ); Mon, 23 Mar 2020 19:34:18 -0400 Received: from mail-pj1-f73.google.com ([209.85.216.73]:40630 "EHLO mail-pj1-f73.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727120AbgCWXeR (ORCPT ); Mon, 23 Mar 2020 19:34:17 -0400 Received: by mail-pj1-f73.google.com with SMTP id d10so1004466pjz.5 for ; Mon, 23 Mar 2020 16:34:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=g1IXTxNeLuaEoIeAZquMIN8o8RyeqEvLaY82fpBZWjc=; b=IHAJPl2oTxONyfNceKZR24ED2EcxarW3ZSAI9FkMqFE0ID+RRsYVYXi/fqi8YylKMo xZC9QD9AIn59b5g/bRMjVT4gSbndx3PplMKjOoHeqCMVeb07iDVn3kco3S0VNdhmg0pY rZAEkQXs/YaXzYjK4qx1UpuatgbmdmooExWI5KIZ4t/aZ9oaIBIEymCkr9WPFdlxs8Xr biYrXf/F84ARMgUzOsMmb9Xbpo8PItkZbMK/Up5Uv3q0W/dHd2VDhVqyNzBJnlSKEfrI G373NRUxDdgwxiKbtjsuFhX/4Q9Uv5meYi6iK8UDoWK7rFRjTpGOWB3UJoFEHcwDdFn4 LEcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=g1IXTxNeLuaEoIeAZquMIN8o8RyeqEvLaY82fpBZWjc=; b=n+gtCyT3P+w4Vn23TAH0v8VDFv+mP2+1Ycf/T0VABTqg98VMjSTHAGluEvcSb2aEdA 1TvG0Jdo7ZwC5QZ7aV+glUQg96S6rpjBJBb58ie5bIq/qgMcSM6/4+TDU2l7f+PIqGiB 5OHEhWr8Ieos5lRCtICvtTG7Emxe9CZW0V6qwsdZqH+GCjZ2hsq/IsdTYnzboTOshxp7 7s0/trh4J6lHROdAmCuzPkWCAs+h8Ot3lG6H2G1+xeMt3A2u5NzmG2OxGcBhlVv7sYy6 O70MNTfFx6G05wVuj3qWj0ON+e+fDS3gpuraN/9hjENJi35zCIuNPg1hsyv9Wx9nSC7n BbAA== X-Gm-Message-State: ANhLgQ1DcpunKkTxMc3aHMMg45Gs7+MOh+PJpkw5HNWaQcrDeDmirjKs YHteKdAzvu+1a59vJRKRuyHx1pfSDA== X-Google-Smtp-Source: ADFU+vtuicKd9xEczdBa/a3me7A5WmLybcBMMiKtFPfL2j6mf5FWfWwsC5ap0rDRstz05QphVWxOQwQh5A== X-Received: by 2002:a17:90a:e7c8:: with SMTP id kb8mr1901152pjb.79.1585006456742; Mon, 23 Mar 2020 16:34:16 -0700 (PDT) Date: Mon, 23 Mar 2020 16:33:54 -0700 In-Reply-To: <20200323233354.239365-1-kunyi@google.com> Message-Id: <20200323233354.239365-4-kunyi@google.com> Mime-Version: 1.0 References: <20200323233354.239365-1-kunyi@google.com> X-Mailer: git-send-email 2.25.1.696.g5e7596f4ac-goog Subject: [PATCH linux hwmon-next v2 3/3] dt-bindings: (hwmon/sbtsi_tmep) Add SB-TSI hwmon driver bindings From: Kun Yi To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com Cc: Kun Yi , openbmc@lists.ozlabs.org, joel@jms.id.au, linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Document device tree bindings for AMD SB-TSI emulated temperature sensor. Signed-off-by: Kun Yi Change-Id: Ife3285afa4cf8d410cb7bee1eb930dc0717084f9 --- .../devicetree/bindings/hwmon/sbtsi_temp.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/sbtsi_temp.txt diff --git a/Documentation/devicetree/bindings/hwmon/sbtsi_temp.txt b/Documentation/devicetree/bindings/hwmon/sbtsi_temp.txt new file mode 100644 index 000000000000..4020f075699e --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/sbtsi_temp.txt @@ -0,0 +1,14 @@ +*AMD SoC SB-TSI hwmon driver. + +Required properties: +- compatible: manufacturer and chip name, should be + "amd,sbtsi", + +- reg: I2C bus address of the device + +Example: + +sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; +};