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Thu, 26 Mar 2020 06:45:11 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com, devicetree@vger.kernel.org Subject: [PATCH v2 01/14] dt-bindings: usb: amlogic, meson-g12a-usb-ctrl: add the Amlogic GXL and GXM Families USB Glue Bindings Date: Thu, 26 Mar 2020 14:44:53 +0100 Message-Id: <20200326134507.4808-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064513_094184_56AE8B73 X-CRM114-Status: GOOD ( 10.27 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Amlogic GXL and GXM is slightly different from the Amlogic G12A Glue. The GXL SoCs only embeds 2 USB2 PHYs and no USB3 PHYs, and the GXM SoCs embeds 3 USB2 PHYs. Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../usb/amlogic,meson-g12a-usb-ctrl.yaml | 73 ++++++++++++++++++- 1 file changed, 69 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index b0e5e0fe9386..b0af50a7c124 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -25,9 +25,13 @@ description: | The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in host-only mode. + The Amlogic GXL & GXM SoCs doesn't embed an USB3 PHY. + properties: compatible: enum: + - amlogic,meson-gxl-usb-ctrl + - amlogic,meson-gxm-usb-ctrl - amlogic,meson-g12a-usb-ctrl - amlogic,meson-a1-usb-ctrl @@ -41,6 +45,11 @@ properties: clocks: minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 resets: minItems: 1 @@ -52,10 +61,8 @@ properties: maxItems: 1 phy-names: - items: - - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used - - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used - - const: usb3-phy0 # USB3 PHY if USB3_0 is used + minItems: 1 + maxItems: 3 phys: minItems: 1 @@ -89,6 +96,61 @@ required: - dr_mode allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-g12a-usb-ctrl + + then: + properties: + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + - const: usb3-phy0 # USB3 PHY if USB3_0 is used + - if: + properties: + compatible: + enum: + - amlogic,meson-gxl-usb-ctrl + + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + required: + - clock-names + - if: + properties: + compatible: + enum: + - amlogic,meson-gxm-usb-ctrl + + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + - const: usb2-phy2 # USB2 PHY2 if USBOTG_C port is used + + required: + - clock-names - if: properties: compatible: @@ -97,6 +159,9 @@ allOf: then: properties: + phy-names: + items: + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used clocks: minItems: 3 clock-names: From patchwork Thu Mar 26 13:44:54 2020 Content-Type: text/plain; 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Thu, 26 Mar 2020 06:45:12 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Subject: [PATCH v2 02/14] usb: dwc3: meson-g12a: specify phy names in soc data Date: Thu, 26 Mar 2020 14:44:54 +0100 Message-Id: <20200326134507.4808-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064514_408488_477CF328 X-CRM114-Status: GOOD ( 13.57 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:441 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hanjie Lin , Neil Armstrong , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org To handle the variable USB2 PHY counts on GXL and GXM SoCs, add the possible PHY names for each SoC in the compatible match data. Reviewed-by: Martin Blumenstingl Acked-by: Hanjie Lin Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 47 +++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 14 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 902553f39889..d97ead5aee4e 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -96,16 +96,8 @@ #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) -enum { - USB2_HOST_PHY = 0, - USB2_OTG_PHY, - USB3_HOST_PHY, - PHY_COUNT, -}; - -static const char *phy_names[PHY_COUNT] = { - "usb2-phy0", "usb2-phy1", "usb3-phy0", -}; +#define PHY_COUNT 3 +#define USB2_OTG_PHY 1 static struct clk_bulk_data meson_g12a_clocks[] = { { .id = NULL }, @@ -117,22 +109,44 @@ static struct clk_bulk_data meson_a1_clocks[] = { { .id = "xtal_usb_ctrl" }, }; +static const char *meson_g12a_phy_names[] = { + "usb2-phy0", "usb2-phy1", "usb3-phy0", +}; + +/* + * Amlogic A1 has a single physical PHY, in slot 1, but still has the + * two U2 PHY controls register blocks like G12A. + * Handling the first PHY on slot 1 would need a large amount of code + * changes, and the current management is generic enough to handle it + * correctly when only the "usb2-phy1" phy is specified on-par with the + * DT bindings. + */ +static const char *meson_a1_phy_names[] = { + "usb2-phy0", "usb2-phy1" +}; + struct dwc3_meson_g12a_drvdata { bool otg_switch_supported; struct clk_bulk_data *clks; int num_clks; + const char **phy_names; + int num_phys; }; static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, .num_clks = ARRAY_SIZE(meson_g12a_clocks), + .phy_names = meson_g12a_phy_names, + .num_phys = ARRAY_SIZE(meson_g12a_phy_names), }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { .otg_switch_supported = false, .clks = meson_a1_clocks, .num_clks = ARRAY_SIZE(meson_a1_clocks), + .phy_names = meson_a1_phy_names, + .num_phys = ARRAY_SIZE(meson_a1_phy_names), }; struct dwc3_meson_g12a { @@ -171,10 +185,13 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) else priv->otg_phy_mode = PHY_MODE_USB_HOST; - for (i = 0 ; i < USB3_HOST_PHY ; ++i) { + for (i = 0; i < priv->drvdata->num_phys; ++i) { if (!priv->phys[i]) continue; + if (!strstr(priv->drvdata->phy_names[i], "usb2")) + continue; + regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), U2P_R0_POWER_ON_RESET, U2P_R0_POWER_ON_RESET); @@ -284,17 +301,19 @@ static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = { static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv) { + const char *phy_name; int i; - for (i = 0 ; i < PHY_COUNT ; ++i) { - priv->phys[i] = devm_phy_optional_get(priv->dev, phy_names[i]); + for (i = 0 ; i < priv->drvdata->num_phys ; ++i) { + phy_name = priv->drvdata->phy_names[i]; + priv->phys[i] = devm_phy_optional_get(priv->dev, phy_name); if (!priv->phys[i]) continue; if (IS_ERR(priv->phys[i])) return PTR_ERR(priv->phys[i]); - if (i == USB3_HOST_PHY) + if (strstr(phy_name, "usb3")) priv->usb3_ports++; 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Thu, 26 Mar 2020 06:45:13 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Subject: [PATCH v2 03/14] usb: dwc3: meson-g12a: handle the phy and glue registers separately Date: Thu, 26 Mar 2020 14:44:55 +0100 Message-Id: <20200326134507.4808-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064516_387740_562620AA X-CRM114-Status: GOOD ( 18.06 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On the Amlogic GXL/GXM SoCs, only the USB control registers are available, the PHY mode being handled in the PHY registers. Thus, handle the PHY mode registers in separate regmaps and prepare support for Amlogic GXL/GXM SoCs by moving the regmap setup in a callback set in the SoC match data. Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 124 ++++++++++++++++++++--------- 1 file changed, 85 insertions(+), 39 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index d97ead5aee4e..37ef08493e37 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -30,7 +30,7 @@ #include #include -/* USB2 Ports Control Registers */ +/* USB2 Ports Control Registers, offsets are per-port */ #define U2P_REG_SIZE 0x20 @@ -50,14 +50,16 @@ /* USB Glue Control Registers */ -#define USB_R0 0x80 +#define G12A_GLUE_OFFSET 0x80 + +#define USB_R0 0x00 #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) #define USB_R0_U2D_ACT BIT(31) -#define USB_R1 0x84 +#define USB_R1 0x04 #define USB_R1_U3H_BIGENDIAN_GS BIT(0) #define USB_R1_U3H_PME_ENABLE BIT(1) #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2) @@ -69,23 +71,23 @@ #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) -#define USB_R2 0x88 +#define USB_R2 0x08 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) -#define USB_R3 0x8c +#define USB_R3 0x0c #define USB_R3_P30_SSC_ENABLE BIT(0) #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) #define USB_R3_P30_REF_SSP_EN BIT(13) -#define USB_R4 0x90 +#define USB_R4 0x10 #define USB_R4_P21_PORT_RESET_0 BIT(0) #define USB_R4_P21_SLEEP_M0 BIT(1) #define USB_R4_MEM_PD_MASK GENMASK(3, 2) #define USB_R4_P21_ONLY BIT(4) -#define USB_R5 0x94 +#define USB_R5 0x14 #define USB_R5_ID_DIG_SYNC BIT(0) #define USB_R5_ID_DIG_REG BIT(1) #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) @@ -125,20 +127,27 @@ static const char *meson_a1_phy_names[] = { "usb2-phy0", "usb2-phy1" }; +struct dwc3_meson_g12a; + struct dwc3_meson_g12a_drvdata { bool otg_switch_supported; struct clk_bulk_data *clks; int num_clks; const char **phy_names; int num_phys; + int (*setup_regmaps)(struct dwc3_meson_g12a *priv, void __iomem *base); }; +static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base); + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, .num_clks = ARRAY_SIZE(meson_g12a_clocks), .phy_names = meson_g12a_phy_names, .num_phys = ARRAY_SIZE(meson_g12a_phy_names), + .setup_regmaps = dwc3_meson_g12a_setup_regmaps, }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { @@ -147,11 +156,13 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = { .num_clks = ARRAY_SIZE(meson_a1_clocks), .phy_names = meson_a1_phy_names, .num_phys = ARRAY_SIZE(meson_a1_phy_names), + .setup_regmaps = dwc3_meson_g12a_setup_regmaps, }; struct dwc3_meson_g12a { struct device *dev; - struct regmap *regmap; + struct regmap *u2p_regmap[PHY_COUNT]; + struct regmap *usb_glue_regmap; struct reset_control *reset; struct phy *phys[PHY_COUNT]; enum usb_dr_mode otg_mode; @@ -168,11 +179,11 @@ static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { if (mode == PHY_MODE_USB_HOST) - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, U2P_R0_HOST_DEVICE); else - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, 0); } @@ -192,13 +203,12 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) if (!strstr(priv->drvdata->phy_names[i], "usb2")) continue; - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_POWER_ON_RESET, U2P_R0_POWER_ON_RESET); if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { - regmap_update_bits(priv->regmap, - U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); @@ -208,7 +218,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) dwc3_meson_g12a_usb2_set_mode(priv, i, PHY_MODE_USB_HOST); - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_POWER_ON_RESET, 0); } @@ -217,7 +227,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) { - regmap_update_bits(priv->regmap, USB_R3, + regmap_update_bits(priv->usb_glue_regmap, USB_R3, USB_R3_P30_SSC_RANGE_MASK | USB_R3_P30_REF_SSP_EN, USB_R3_P30_SSC_ENABLE | @@ -225,21 +235,21 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) USB_R3_P30_REF_SSP_EN); udelay(2); - regmap_update_bits(priv->regmap, USB_R2, + regmap_update_bits(priv->usb_glue_regmap, USB_R2, USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15)); - regmap_update_bits(priv->regmap, USB_R2, + regmap_update_bits(priv->usb_glue_regmap, USB_R2, USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20)); udelay(2); - regmap_update_bits(priv->regmap, USB_R1, + regmap_update_bits(priv->usb_glue_regmap, USB_R1, USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT, USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT); - regmap_update_bits(priv->regmap, USB_R1, + regmap_update_bits(priv->usb_glue_regmap, USB_R1, USB_R1_P30_PCS_TX_SWING_FULL_MASK, FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127)); } @@ -247,16 +257,16 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv) { if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) { - regmap_update_bits(priv->regmap, USB_R0, + regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, USB_R0_U2D_ACT); - regmap_update_bits(priv->regmap, USB_R0, + regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0); - regmap_update_bits(priv->regmap, USB_R4, + regmap_update_bits(priv->usb_glue_regmap, USB_R4, USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0); } else { - regmap_update_bits(priv->regmap, USB_R0, + regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, 0); - regmap_update_bits(priv->regmap, USB_R4, + regmap_update_bits(priv->usb_glue_regmap, USB_R4, USB_R4_P21_SLEEP_M0, 0); } } @@ -269,17 +279,17 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) if (ret) return ret; - regmap_update_bits(priv->regmap, USB_R1, + regmap_update_bits(priv->usb_glue_regmap, USB_R1, USB_R1_U3H_FLADJ_30MHZ_REG_MASK, FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20)); - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_EN_0, USB_R5_ID_DIG_EN_0); - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_EN_1, USB_R5_ID_DIG_EN_1); - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_TH_MASK, FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff)); @@ -292,7 +302,8 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) return 0; } -static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = { +static const struct regmap_config phy_meson_g12a_usb_glue_regmap_conf = { + .name = "usb-glue", .reg_bits = 8, .val_bits = 32, .reg_stride = 4, @@ -329,7 +340,7 @@ static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv) { u32 reg; - regmap_read(priv->regmap, USB_R5, ®); + regmap_read(priv->usb_glue_regmap, USB_R5, ®); if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG)) return PHY_MODE_USB_DEVICE; @@ -404,7 +415,8 @@ static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data) dev_warn(priv->dev, "Failed to switch OTG mode\n"); } - regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0); + regmap_update_bits(priv->usb_glue_regmap, USB_R5, + USB_R5_ID_DIG_IRQ, 0); return IRQ_HANDLED; } @@ -439,7 +451,7 @@ static int dwc3_meson_g12a_otg_init(struct platform_device *pdev, if (priv->otg_mode == USB_DR_MODE_OTG) { /* Ack irq before registering */ - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0); irq = platform_get_irq(pdev, 0); @@ -474,6 +486,41 @@ static int dwc3_meson_g12a_otg_init(struct platform_device *pdev, return 0; } +static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base) +{ + int i; + + priv->usb_glue_regmap = devm_regmap_init_mmio(priv->dev, + base + G12A_GLUE_OFFSET, + &phy_meson_g12a_usb_glue_regmap_conf); + if (IS_ERR(priv->usb_glue_regmap)) + return PTR_ERR(priv->usb_glue_regmap); + + /* Create a regmap for each USB2 PHY control register set */ + for (i = 0; i < priv->usb2_ports; i++) { + struct regmap_config u2p_regmap_config = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = U2P_R1, + }; + + u2p_regmap_config.name = devm_kasprintf(priv->dev, GFP_KERNEL, + "u2p-%d", i); + if (!u2p_regmap_config.name) + return -ENOMEM; + + priv->u2p_regmap[i] = devm_regmap_init_mmio(priv->dev, + base + (i * U2P_REG_SIZE), + &u2p_regmap_config); + if (IS_ERR(priv->u2p_regmap[i])) + return PTR_ERR(priv->u2p_regmap[i]); + } + + return 0; +} + static int dwc3_meson_g12a_probe(struct platform_device *pdev) { struct dwc3_meson_g12a *priv; @@ -490,10 +537,12 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - priv->regmap = devm_regmap_init_mmio(dev, base, - &phy_meson_g12a_usb3_regmap_conf); - if (IS_ERR(priv->regmap)) - return PTR_ERR(priv->regmap); + priv->drvdata = of_device_get_match_data(&pdev->dev); + + priv->dev = dev; + ret = priv->drvdata->setup_regmaps(priv, base); + if (ret) + return ret; priv->vbus = devm_regulator_get_optional(dev, "vbus"); if (IS_ERR(priv->vbus)) { @@ -502,8 +551,6 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) priv->vbus = NULL; } - priv->drvdata = of_device_get_match_data(&pdev->dev); - ret = devm_clk_bulk_get(dev, priv->drvdata->num_clks, priv->drvdata->clks); @@ -516,7 +563,6 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) return ret; platform_set_drvdata(pdev, priv); - priv->dev = dev; priv->reset = devm_reset_control_get(dev, NULL); if (IS_ERR(priv->reset)) { From patchwork Thu Mar 26 13:44:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13136161F for ; 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Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 37ef08493e37..41bcbd31fe4e 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -564,7 +564,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); - priv->reset = devm_reset_control_get(dev, NULL); + priv->reset = devm_reset_control_get_shared(dev, NULL); if (IS_ERR(priv->reset)) { ret = PTR_ERR(priv->reset); dev_err(dev, "failed to get device reset, err=%d\n", ret); From patchwork Thu Mar 26 13:44:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 66567161F for ; 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Fixes: e3e716e6b889 ("usb: dwc3: Add Amlogic A1 DWC3 glue") Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- drivers/usb/dwc3/dwc3-meson-g12a.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 41bcbd31fe4e..69381c42a6d3 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -588,7 +588,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) /* Get dr_mode */ priv->otg_mode = usb_get_dr_mode(dev); - dwc3_meson_g12a_usb_init(priv); + ret = dwc3_meson_g12a_usb_init(priv); + if (ret) + goto err_disable_clks; /* Init PHYs */ for (i = 0 ; i < PHY_COUNT ; ++i) { From patchwork Thu Mar 26 13:44:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460115 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0A6C161F for ; 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The Amlogic GXL/GXM will call phy_set_mode() instead of programming the PHY mode control registers, thus add two new callbacks to the SoC match data. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- drivers/usb/dwc3/dwc3-meson-g12a.c | 74 +++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 21 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 69381c42a6d3..328e74def56f 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -136,11 +136,21 @@ struct dwc3_meson_g12a_drvdata { const char **phy_names; int num_phys; int (*setup_regmaps)(struct dwc3_meson_g12a *priv, void __iomem *base); + int (*usb2_init_phy)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + int (*set_phy_mode)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); }; static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode); + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, @@ -148,6 +158,8 @@ static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .phy_names = meson_g12a_phy_names, .num_phys = ARRAY_SIZE(meson_g12a_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { @@ -157,6 +169,8 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = { .phy_names = meson_a1_phy_names, .num_phys = ARRAY_SIZE(meson_a1_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; struct dwc3_meson_g12a { @@ -175,8 +189,8 @@ struct dwc3_meson_g12a { const struct dwc3_meson_g12a_drvdata *drvdata; }; -static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, - int i, enum phy_mode mode) +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode) { if (mode == PHY_MODE_USB_HOST) regmap_update_bits(priv->u2p_regmap[i], U2P_R0, @@ -185,11 +199,41 @@ static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, else regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, 0); + + return 0; +} + +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode) +{ + int ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, + U2P_R0_POWER_ON_RESET); + + if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); + + ret = priv->drvdata->set_phy_mode(priv, i, mode); + } else + ret = priv->drvdata->set_phy_mode(priv, i, + PHY_MODE_USB_HOST); + + if (ret) + return ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, 0); + + return 0; } static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) { - int i; + int i, ret; if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) priv->otg_phy_mode = PHY_MODE_USB_DEVICE; @@ -203,23 +247,9 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) if (!strstr(priv->drvdata->phy_names[i], "usb2")) continue; - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, - U2P_R0_POWER_ON_RESET); - - if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); - - dwc3_meson_g12a_usb2_set_mode(priv, i, - priv->otg_phy_mode); - } else - dwc3_meson_g12a_usb2_set_mode(priv, i, - PHY_MODE_USB_HOST); - - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, 0); + ret = priv->drvdata->usb2_init_phy(priv, i, priv->otg_phy_mode); + if (ret) + return ret; } return 0; @@ -372,7 +402,9 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, priv->otg_phy_mode = mode; - dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode); + ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY, mode); + if (ret) + return ret; dwc3_meson_g12a_usb_otg_apply_mode(priv); From patchwork Thu Mar 26 13:44:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460123 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 28E931668 for ; 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A secondary, post_init callback is added to setup the OTG PHY mode after the sub-nodes probe. Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 46 +++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 328e74def56f..43b398b7b1f7 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -140,6 +140,8 @@ struct dwc3_meson_g12a_drvdata { enum phy_mode mode); int (*set_phy_mode)(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); + int (*usb_init)(struct dwc3_meson_g12a *priv); + int (*usb_post_init)(struct dwc3_meson_g12a *priv); }; static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, @@ -151,6 +153,8 @@ static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); +static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv); + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, @@ -160,6 +164,7 @@ static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .setup_regmaps = dwc3_meson_g12a_setup_regmaps, .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, .set_phy_mode = dwc3_meson_g12a_set_phy_mode, + .usb_init = dwc3_meson_g12a_usb_init, }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { @@ -171,6 +176,7 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = { .setup_regmaps = dwc3_meson_g12a_setup_regmaps, .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, .set_phy_mode = dwc3_meson_g12a_set_phy_mode, + .usb_init = dwc3_meson_g12a_usb_init, }; struct dwc3_meson_g12a { @@ -231,15 +237,11 @@ static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, return 0; } -static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) +static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv, + enum phy_mode mode) { int i, ret; - if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) - priv->otg_phy_mode = PHY_MODE_USB_DEVICE; - else - priv->otg_phy_mode = PHY_MODE_USB_HOST; - for (i = 0; i < priv->drvdata->num_phys; ++i) { if (!priv->phys[i]) continue; @@ -284,9 +286,10 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127)); } -static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv) +static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv, + enum phy_mode mode) { - if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) { + if (mode == PHY_MODE_USB_DEVICE) { regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, USB_R0_U2D_ACT); regmap_update_bits(priv->usb_glue_regmap, USB_R0, @@ -301,11 +304,12 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv) } } -static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) +static int dwc3_meson_g12a_usb_init_glue(struct dwc3_meson_g12a *priv, + enum phy_mode mode) { int ret; - ret = dwc3_meson_g12a_usb2_init(priv); + ret = dwc3_meson_g12a_usb2_init(priv, mode); if (ret) return ret; @@ -327,7 +331,7 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) if (priv->usb3_ports) dwc3_meson_g12a_usb3_init(priv); - dwc3_meson_g12a_usb_otg_apply_mode(priv); + dwc3_meson_g12a_usb_otg_apply_mode(priv, mode); return 0; } @@ -406,7 +410,7 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, if (ret) return ret; - dwc3_meson_g12a_usb_otg_apply_mode(priv); + dwc3_meson_g12a_usb_otg_apply_mode(priv, mode); return 0; } @@ -553,6 +557,11 @@ static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, return 0; } +static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) +{ + return dwc3_meson_g12a_usb_init_glue(priv, priv->otg_phy_mode); +} + static int dwc3_meson_g12a_probe(struct platform_device *pdev) { struct dwc3_meson_g12a *priv; @@ -620,7 +629,12 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) /* Get dr_mode */ priv->otg_mode = usb_get_dr_mode(dev); - ret = dwc3_meson_g12a_usb_init(priv); + if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) + priv->otg_phy_mode = PHY_MODE_USB_DEVICE; + else + priv->otg_phy_mode = PHY_MODE_USB_HOST; + + ret = priv->drvdata->usb_init(priv); if (ret) goto err_disable_clks; @@ -642,6 +656,12 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) if (ret) goto err_phys_power; + if (priv->drvdata->usb_post_init) { + ret = priv->drvdata->usb_post_init(priv); + if (ret) + goto err_phys_power; + } + ret = dwc3_meson_g12a_otg_init(pdev, priv); if (ret) goto err_phys_power; From patchwork Thu Mar 26 13:45:00 2020 Content-Type: text/plain; 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Thu, 26 Mar 2020 06:45:20 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Subject: [PATCH v2 08/14] usb: dwc3: meson-g12a: support the GXL/GXM DWC3 host phy disconnect Date: Thu, 26 Mar 2020 14:45:00 +0100 Message-Id: <20200326134507.4808-9-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064523_535703_31A46872 X-CRM114-Status: GOOD ( 18.86 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:444 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On the Amlogic GXL/GXM SoCs, the OTG PHY status signals are always connected to the DWC3 controller, thus crashing the controller when switching to OTG mode when port is not populated with a device/cable to Host. Amlogic added a bit to disconnect the OTG PHY status signals from the DWC3 to be used when switching the OTG PHY as Device to the DWC2 controller. The drawback is that it makes the DWC3 port state machine stall and needs a full reset of the DWC3 controller to get connect status to the port connected to the OTG PHY, but not the other one. Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 43b398b7b1f7..f3f247d38606 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -131,6 +131,7 @@ struct dwc3_meson_g12a; struct dwc3_meson_g12a_drvdata { bool otg_switch_supported; + bool otg_phy_host_port_disable; struct clk_bulk_data *clks; int num_clks; const char **phy_names; @@ -155,6 +156,19 @@ static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv); +/* + * For GXL and GXM SoCs: + * USB Phy muxing between the DWC2 Device controller and the DWC3 Host + * controller is buggy when switching from Device to Host when USB port + * is unpopulated, it causes the DWC3 to hard crash. + * When populated (including OTG switching with ID pin), the switch works + * like a charm like on the G12A platforms. + * In order to still switch from Host to Device on an USB Type-A port, + * an U2_PORT_DISABLE bit has been added to disconnect the DWC3 Host + * controller from the port, but when used the DWC3 controller must be + * reset to recover usage of the port. + */ + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, @@ -290,6 +304,13 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv, enum phy_mode mode) { if (mode == PHY_MODE_USB_DEVICE) { + if (priv->otg_mode != USB_DR_MODE_OTG && + priv->drvdata->otg_phy_host_port_disable) + /* Isolate the OTG PHY port from the Host Controller */ + regmap_update_bits(priv->usb_glue_regmap, USB_R1, + USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, + FIELD_PREP(USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, + BIT(USB2_OTG_PHY))); regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, USB_R0_U2D_ACT); regmap_update_bits(priv->usb_glue_regmap, USB_R0, @@ -297,6 +318,12 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv, regmap_update_bits(priv->usb_glue_regmap, USB_R4, USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0); } else { + if (priv->otg_mode != USB_DR_MODE_OTG && + priv->drvdata->otg_phy_host_port_disable) { + regmap_update_bits(priv->usb_glue_regmap, USB_R1, + USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0); + msleep(500); + } regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, 0); regmap_update_bits(priv->usb_glue_regmap, USB_R4, @@ -429,6 +456,13 @@ static int dwc3_meson_g12a_role_set(struct device *dev, enum usb_role role) if (mode == priv->otg_phy_mode) return 0; + if (priv->drvdata->otg_phy_host_port_disable) + dev_warn_once(priv->dev, "Manual OTG switch is broken on this "\ + "SoC, when manual switching from "\ + "Host to device, DWC3 controller "\ + "will need to be resetted in order "\ + "to recover usage of the Host port"); + return dwc3_meson_g12a_otg_mode_set(priv, mode); } From patchwork Thu Mar 26 13:45:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460133 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0322B1668 for ; Thu, 26 Mar 2020 13:48:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4C3A206E6 for ; Thu, 26 Mar 2020 13:48:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="tl/MufN0"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="pGUIJ/Rs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D4C3A206E6 Authentication-Results: mail.kernel.org; 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Thu, 26 Mar 2020 06:45:22 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Subject: [PATCH v2 09/14] usb: dwc3: meson-g12a: add support for GXL and GXM SoCs Date: Thu, 26 Mar 2020 14:45:01 +0100 Message-Id: <20200326134507.4808-10-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064525_005629_24AE144E X-CRM114-Status: GOOD ( 14.94 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:441 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In order to add support for the Amlogic GXL/GXM USB Glue, this adds the corresponding : - PHY names - clock names - USB2 PHY init and mode set - regmap setup Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 102 ++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index f3f247d38606..15b8d9d4accd 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -101,6 +101,11 @@ #define PHY_COUNT 3 #define USB2_OTG_PHY 1 +static struct clk_bulk_data meson_gxl_clocks[] = { + { .id = "usb_ctrl" }, + { .id = "ddr" }, +}; + static struct clk_bulk_data meson_g12a_clocks[] = { { .id = NULL }, }; @@ -111,6 +116,10 @@ static struct clk_bulk_data meson_a1_clocks[] = { { .id = "xtal_usb_ctrl" }, }; +static const char *meson_gxm_phy_names[] = { + "usb2-phy0", "usb2-phy1", "usb2-phy2", +}; + static const char *meson_g12a_phy_names[] = { "usb2-phy0", "usb2-phy1", "usb3-phy0", }; @@ -145,16 +154,53 @@ struct dwc3_meson_g12a_drvdata { int (*usb_post_init)(struct dwc3_meson_g12a *priv); }; +static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base); static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, - enum phy_mode mode); + enum phy_mode mode); +static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); +static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode); static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv); +static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv); + +static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv); + +static struct dwc3_meson_g12a_drvdata gxl_drvdata = { + .otg_switch_supported = true, + .otg_phy_host_port_disable = true, + .clks = meson_gxl_clocks, + .num_clks = ARRAY_SIZE(meson_g12a_clocks), + .phy_names = meson_a1_phy_names, + .num_phys = ARRAY_SIZE(meson_a1_phy_names), + .setup_regmaps = dwc3_meson_gxl_setup_regmaps, + .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy, + .set_phy_mode = dwc3_meson_gxl_set_phy_mode, + .usb_init = dwc3_meson_gxl_usb_init, + .usb_post_init = dwc3_meson_gxl_usb_post_init, +}; + +static struct dwc3_meson_g12a_drvdata gxm_drvdata = { + .otg_switch_supported = true, + .otg_phy_host_port_disable = true, + .clks = meson_gxl_clocks, + .num_clks = ARRAY_SIZE(meson_g12a_clocks), + .phy_names = meson_gxm_phy_names, + .num_phys = ARRAY_SIZE(meson_gxm_phy_names), + .setup_regmaps = dwc3_meson_gxl_setup_regmaps, + .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy, + .set_phy_mode = dwc3_meson_gxl_set_phy_mode, + .usb_init = dwc3_meson_gxl_usb_init, + .usb_post_init = dwc3_meson_gxl_usb_post_init, +}; /* * For GXL and GXM SoCs: @@ -209,6 +255,21 @@ struct dwc3_meson_g12a { const struct dwc3_meson_g12a_drvdata *drvdata; }; +static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode) +{ + return phy_set_mode(priv->phys[i], mode); +} + +static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode) +{ + /* On GXL PHY must be started in device mode for DWC2 init */ + return priv->drvdata->set_phy_mode(priv, i, + (i == USB2_OTG_PHY) ? PHY_MODE_USB_DEVICE + : PHY_MODE_USB_HOST); +} + static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { @@ -556,6 +617,18 @@ static int dwc3_meson_g12a_otg_init(struct platform_device *pdev, return 0; } +static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base) +{ + /* GXL controls the PHY mode in the PHY registers unlike G12A */ + priv->usb_glue_regmap = devm_regmap_init_mmio(priv->dev, base, + &phy_meson_g12a_usb_glue_regmap_conf); + if (IS_ERR(priv->usb_glue_regmap)) + return PTR_ERR(priv->usb_glue_regmap); + + return 0; +} + static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base) { @@ -596,6 +669,25 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) return dwc3_meson_g12a_usb_init_glue(priv, priv->otg_phy_mode); } +static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv) +{ + return dwc3_meson_g12a_usb_init_glue(priv, PHY_MODE_USB_DEVICE); +} + +static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv) +{ + int ret; + + ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY, + priv->otg_phy_mode); + if (ret) + return ret; + + dwc3_meson_g12a_usb_otg_apply_mode(priv, priv->otg_phy_mode); + + return 0; +} + static int dwc3_meson_g12a_probe(struct platform_device *pdev) { struct dwc3_meson_g12a *priv; @@ -825,6 +917,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = { }; static const struct of_device_id dwc3_meson_g12a_match[] = { + { + .compatible = "amlogic,meson-gxl-usb-ctrl", + .data = &gxl_drvdata, + }, + { + .compatible = "amlogic,meson-gxm-usb-ctrl", + .data = &gxm_drvdata, + }, { .compatible = "amlogic,meson-g12a-usb-ctrl", .data = &g12a_drvdata, From patchwork Thu Mar 26 13:45:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460121 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8554D1668 for ; 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Signed-off-by: Martin Blumenstingl Signed-off-by: Neil Armstrong --- .../dts/amlogic/meson-gx-libretech-pc.dtsi | 3 +- .../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 3 +- .../amlogic/meson-gxl-s805x-libretech-ac.dts | 3 +- .../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 3 +- .../amlogic/meson-gxl-s905d-phicomm-n1.dts | 4 ++ .../boot/dts/amlogic/meson-gxl-s905w-p281.dts | 4 ++ .../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 4 ++ .../amlogic/meson-gxl-s905x-khadas-vim.dts | 4 ++ .../amlogic/meson-gxl-s905x-libretech-cc.dts | 3 +- .../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 3 +- .../dts/amlogic/meson-gxl-s905x-p212.dtsi | 3 +- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 45 ++++++++++--------- .../dts/amlogic/meson-gxm-khadas-vim2.dts | 3 +- .../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 3 +- .../boot/dts/amlogic/meson-gxm-vega-s96.dts | 4 ++ arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 7 ++- 16 files changed, 68 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index 248b018c83d5..ed9f89ee86a8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -360,8 +360,9 @@ status = "okay"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; &usb2_phy0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index 12d5e333e5f2..d853981f1ab5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -223,6 +223,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "otg"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index 4d5949496596..2cfea3094f6c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -243,6 +243,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index a1119cfb0280..867e30f1d62b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -216,6 +216,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts index b5667f1fb2c8..9ef210f17b4a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts @@ -29,3 +29,7 @@ &cvbs_vdac_port { status = "disabled"; }; + +&usb { + dr_mode = "host"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts index 6509c4950950..ecc9df7ca023 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts @@ -20,3 +20,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; }; + +&usb { + dr_mode = "host"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts index dd729ac2300d..6705c2082a78 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts @@ -24,3 +24,7 @@ &ir { linux,rc-map-name = "rc-tanix-tx3mini"; }; + +&usb { + dr_mode = "host"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 440bc23c7342..8bcdffdf55d0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -207,3 +207,7 @@ pinctrl-0 = <&uart_ao_b_pins>; pinctrl-names = "default"; }; + +&usb { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index e8348b2728db..e493831a80f0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -272,8 +272,9 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; &usb2_phy0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts index 62dd87821ce5..f1acca5c4434 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -218,6 +218,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi index 43eb7d149e36..93963e1b7fc0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi @@ -188,8 +188,9 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; &usb2_phy0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 259d86399390..95b301a7c725 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -14,26 +14,43 @@ compatible = "amlogic,meson-gxl"; soc { - usb0: usb@c9000000 { - status = "disabled"; - compatible = "amlogic,meson-gxl-dwc3"; + usb: usb@d0078080 { + compatible = "amlogic,meson-gxl-usb-ctrl"; + reg = <0x0 0xd0078080 0x0 0x20>; + interrupts = ; #address-cells = <2>; #size-cells = <2>; ranges; - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "usb_ctrl", "ddr"; resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - dwc3: dwc3@c9000000 { + dr_mode = "otg"; + + phys = <&usb2_phy0>, <&usb2_phy1>; + phy-names = "usb2-phy0", "usb2-phy1"; + + dwc2: usb@c9100000 { + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; + reg = <0x0 0xc9100000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB1>; + clock-names = "otg"; + phys = <&usb2_phy1>; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + }; + + dwc3: usb@c9000000 { compatible = "snps,dwc3"; reg = <0x0 0xc9000000 0x0 0x100000>; interrupts = ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>; }; }; @@ -71,18 +88,6 @@ reset-names = "phy"; status = "okay"; }; - - usb3_phy: phy@78080 { - compatible = "amlogic,meson-gxl-usb3-phy"; - #phy-cells = <0>; - reg = <0x0 0x78080 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "phy", "peripheral"; - resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; - reset-names = "phy", "peripheral"; - status = "okay"; - }; }; &efuse { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index f82f25c1a5f9..4310f01ccc89 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -437,6 +437,7 @@ vref-supply = <&vddio_ao18>; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index c2bd4dbbf38c..83eca3af44ce 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -179,6 +179,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts index 0bdf51d041ae..d3fdba4da9a6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts @@ -39,3 +39,7 @@ &ir { linux,rc-map-name = "rc-vega-s9x"; }; + +&usb { + dr_mode = "host"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index 5ff64a0d2dcf..84399e802188 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -141,8 +141,11 @@ compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; }; -&dwc3 { - phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; +&usb { + compatible = "amlogic,meson-gxm-usb-ctrl"; + + phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2"; + phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; }; &vdec { From patchwork Thu Mar 26 13:45:03 2020 Content-Type: text/plain; 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Thu, 26 Mar 2020 06:45:25 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Subject: [PATCH v2 11/14] phy: amlogic: meson-gxl-usb3: remove code for non-existing PHY Date: Thu, 26 Mar 2020 14:45:03 +0100 Message-Id: <20200326134507.4808-12-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064527_778735_F03641A2 X-CRM114-Status: GOOD ( 17.74 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Martin Blumenstingl The registers which are managed by the meson-gxl-usb3 PHY driver are actually "USB control" registers (which are "glue" registers which manage OTG detection and routing of the OTG capable port between the DWC2 peripheral-only controller and the DWC3 host-only controller). Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-g12a-usb driver supports the USB control registers on GXL and GXM SoCs (these were previously managed by the meson-gxl-usb3 PHY driver). Signed-off-by: Martin Blumenstingl Signed-off-by: Neil Armstrong --- .../bindings/phy/meson-gxl-usb3-phy.txt | 31 -- drivers/phy/amlogic/Kconfig | 12 - drivers/phy/amlogic/Makefile | 1 - drivers/phy/amlogic/phy-meson-gxl-usb3.c | 283 ------------------ 4 files changed, 327 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt delete mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt deleted file mode 100644 index 114947e1de3d..000000000000 --- a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding - -Required properties: -- compatible: Should be "amlogic,meson-gxl-usb3-phy" -- #phys-cells: must be 0 (see phy-bindings.txt in this directory) -- reg: The base address and length of the registers -- interrupts: the interrupt specifier for the OTG detection -- clocks: phandles to the clocks for - - the USB3 PHY - - and peripheral mode/OTG detection -- clock-names: must contain "phy" and "peripheral" -- resets: phandle to the reset lines for: - - the USB3 PHY and - - peripheral mode/OTG detection -- reset-names: must contain "phy" and "peripheral" - -Optional properties: -- phy-supply: see phy-bindings.txt in this directory - - -Example: - usb3_phy0: phy@78080 { - compatible = "amlogic,meson-gxl-usb3-phy"; - #phy-cells = <0>; - reg = <0x0 0x78080 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "phy", "peripheral"; - resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; - reset-names = "phy", "peripheral"; - }; diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig index af774ac2b934..77db9535ac6d 100644 --- a/drivers/phy/amlogic/Kconfig +++ b/drivers/phy/amlogic/Kconfig @@ -26,18 +26,6 @@ config PHY_MESON_GXL_USB2 GXL and GXM SoCs. If unsure, say N. -config PHY_MESON_GXL_USB3 - tristate "Meson GXL and GXM USB3 PHY drivers" - default ARCH_MESON - depends on OF && (ARCH_MESON || COMPILE_TEST) - depends on USB_SUPPORT - select GENERIC_PHY - select REGMAP_MMIO - help - Enable this to support the Meson USB3 PHY and OTG detection - IP block found in Meson GXL and GXM SoCs. - If unsure, say N. - config PHY_MESON_G12A_USB2 tristate "Meson G12A USB2 PHY driver" default ARCH_MESON diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile index 11d1c42ac2be..8552e7153b99 100644 --- a/drivers/phy/amlogic/Makefile +++ b/drivers/phy/amlogic/Makefile @@ -2,5 +2,4 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o -obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb3.c b/drivers/phy/amlogic/phy-meson-gxl-usb3.c deleted file mode 100644 index c0e9e4c16149..000000000000 --- a/drivers/phy/amlogic/phy-meson-gxl-usb3.c +++ /dev/null @@ -1,283 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Meson GXL USB3 PHY and OTG mode detection driver - * - * Copyright (C) 2018 Martin Blumenstingl - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define USB_R0 0x00 - #define USB_R0_P30_FSEL_MASK GENMASK(5, 0) - #define USB_R0_P30_PHY_RESET BIT(6) - #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7) - #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8) - #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9) - #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14) - #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) - #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) - #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) - #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) - #define USB_R0_U2D_ACT BIT(31) - -#define USB_R1 0x04 - #define USB_R1_U3H_BIGENDIAN_GS BIT(0) - #define USB_R1_U3H_PME_ENABLE BIT(1) - #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2) - #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7) - #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12) - #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) - #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) - #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) - #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) - #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) - -#define USB_R2 0x08 - #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0) - #define USB_R2_P30_CR_READ BIT(16) - #define USB_R2_P30_CR_WRITE BIT(17) - #define USB_R2_P30_CR_CAP_ADDR BIT(18) - #define USB_R2_P30_CR_CAP_DATA BIT(19) - #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) - #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) - -#define USB_R3 0x0c - #define USB_R3_P30_SSC_ENABLE BIT(0) - #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) - #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) - #define USB_R3_P30_REF_SSP_EN BIT(13) - #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16) - #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19) - #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24) - -#define USB_R4 0x10 - #define USB_R4_P21_PORT_RESET_0 BIT(0) - #define USB_R4_P21_SLEEP_M0 BIT(1) - #define USB_R4_MEM_PD_MASK GENMASK(3, 2) - #define USB_R4_P21_ONLY BIT(4) - -#define USB_R5 0x14 - #define USB_R5_ID_DIG_SYNC BIT(0) - #define USB_R5_ID_DIG_REG BIT(1) - #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) - #define USB_R5_ID_DIG_EN_0 BIT(4) - #define USB_R5_ID_DIG_EN_1 BIT(5) - #define USB_R5_ID_DIG_CURR BIT(6) - #define USB_R5_ID_DIG_IRQ BIT(7) - #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) - #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) - -/* read-only register */ -#define USB_R6 0x18 - #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0) - #define USB_R6_P30_CR_ACK BIT(16) - -struct phy_meson_gxl_usb3_priv { - struct regmap *regmap; - enum phy_mode mode; - struct clk *clk_phy; - struct clk *clk_peripheral; - struct reset_control *reset; -}; - -static const struct regmap_config phy_meson_gxl_usb3_regmap_conf = { - .reg_bits = 8, - .val_bits = 32, - .reg_stride = 4, - .max_register = USB_R6, -}; - -static int phy_meson_gxl_usb3_power_on(struct phy *phy) -{ - struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); - - regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, - USB_R5_ID_DIG_EN_0); - regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, - USB_R5_ID_DIG_EN_1); - regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_TH_MASK, - FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff)); - - return 0; -} - -static int phy_meson_gxl_usb3_power_off(struct phy *phy) -{ - struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); - - regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, 0); - regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, 0); - - return 0; -} - -static int phy_meson_gxl_usb3_set_mode(struct phy *phy, - enum phy_mode mode, int submode) -{ - struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); - - switch (mode) { - case PHY_MODE_USB_HOST: - regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT, 0); - regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0, - 0); - break; - - case PHY_MODE_USB_DEVICE: - regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT, - USB_R0_U2D_ACT); - regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0, - USB_R4_P21_SLEEP_M0); - break; - - default: - dev_err(&phy->dev, "unsupported PHY mode %d\n", mode); - return -EINVAL; - } - - priv->mode = mode; - - return 0; -} - -static int phy_meson_gxl_usb3_init(struct phy *phy) -{ - struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); - int ret; - - ret = reset_control_reset(priv->reset); - if (ret) - goto err; - - ret = clk_prepare_enable(priv->clk_phy); - if (ret) - goto err; - - ret = clk_prepare_enable(priv->clk_peripheral); - if (ret) - goto err_disable_clk_phy; - - ret = phy_meson_gxl_usb3_set_mode(phy, priv->mode, 0); - if (ret) - goto err_disable_clk_peripheral; - - regmap_update_bits(priv->regmap, USB_R1, - USB_R1_U3H_FLADJ_30MHZ_REG_MASK, - FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20)); - - return 0; - -err_disable_clk_peripheral: - clk_disable_unprepare(priv->clk_peripheral); -err_disable_clk_phy: - clk_disable_unprepare(priv->clk_phy); -err: - return ret; -} - -static int phy_meson_gxl_usb3_exit(struct phy *phy) -{ - struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); - - clk_disable_unprepare(priv->clk_peripheral); - clk_disable_unprepare(priv->clk_phy); - - return 0; -} - -static const struct phy_ops phy_meson_gxl_usb3_ops = { - .power_on = phy_meson_gxl_usb3_power_on, - .power_off = phy_meson_gxl_usb3_power_off, - .set_mode = phy_meson_gxl_usb3_set_mode, - .init = phy_meson_gxl_usb3_init, - .exit = phy_meson_gxl_usb3_exit, - .owner = THIS_MODULE, -}; - -static int phy_meson_gxl_usb3_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct phy_meson_gxl_usb3_priv *priv; - struct resource *res; - struct phy *phy; - struct phy_provider *phy_provider; - void __iomem *base; - int ret; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - priv->regmap = devm_regmap_init_mmio(dev, base, - &phy_meson_gxl_usb3_regmap_conf); - if (IS_ERR(priv->regmap)) - return PTR_ERR(priv->regmap); - - priv->clk_phy = devm_clk_get(dev, "phy"); - if (IS_ERR(priv->clk_phy)) - return PTR_ERR(priv->clk_phy); - - priv->clk_peripheral = devm_clk_get(dev, "peripheral"); - if (IS_ERR(priv->clk_peripheral)) - return PTR_ERR(priv->clk_peripheral); - - priv->reset = devm_reset_control_array_get_shared(dev); - if (IS_ERR(priv->reset)) - return PTR_ERR(priv->reset); - - /* - * default to host mode as hardware defaults and/or boot-loader - * behavior can result in this PHY starting up in device mode. this - * default and the initialization in phy_meson_gxl_usb3_init ensure - * that we reproducibly start in a known mode on all devices. - */ - priv->mode = PHY_MODE_USB_HOST; - - phy = devm_phy_create(dev, np, &phy_meson_gxl_usb3_ops); - if (IS_ERR(phy)) { - ret = PTR_ERR(phy); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to create PHY\n"); - - return ret; - } - - phy_set_drvdata(phy, priv); - - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - - return PTR_ERR_OR_ZERO(phy_provider); -} - -static const struct of_device_id phy_meson_gxl_usb3_of_match[] = { - { .compatible = "amlogic,meson-gxl-usb3-phy", }, - { }, -}; -MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb3_of_match); - -static struct platform_driver phy_meson_gxl_usb3_driver = { - .probe = phy_meson_gxl_usb3_probe, - .driver = { - .name = "phy-meson-gxl-usb3", - .of_match_table = phy_meson_gxl_usb3_of_match, - }, -}; -module_platform_driver(phy_meson_gxl_usb3_driver); - -MODULE_AUTHOR("Martin Blumenstingl "); -MODULE_DESCRIPTION("Meson GXL USB3 PHY and OTG detection driver"); -MODULE_LICENSE("GPL v2"); From patchwork Thu Mar 26 13:45:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2969D161F for ; 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Signed-off-by: Martin Blumenstingl Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-of-simple.c | 30 ++++++------------------------ 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index e64754be47b4..8852fbfdead4 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -27,7 +27,6 @@ struct dwc3_of_simple { struct clk_bulk_data *clks; int num_clocks; struct reset_control *resets; - bool pulse_resets; bool need_reset; }; @@ -38,7 +37,6 @@ static int dwc3_of_simple_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; int ret; - bool shared_resets = false; simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL); if (!simple) @@ -54,13 +52,7 @@ static int dwc3_of_simple_probe(struct platform_device *pdev) if (of_device_is_compatible(np, "rockchip,rk3399-dwc3")) simple->need_reset = true; - if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") || - of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) { - shared_resets = true; - simple->pulse_resets = true; - } - - simple->resets = of_reset_control_array_get(np, shared_resets, true, + simple->resets = of_reset_control_array_get(np, false, true, true); if (IS_ERR(simple->resets)) { ret = PTR_ERR(simple->resets); @@ -68,15 +60,9 @@ static int dwc3_of_simple_probe(struct platform_device *pdev) return ret; } - if (simple->pulse_resets) { - ret = reset_control_reset(simple->resets); - if (ret) - goto err_resetc_put; - } else { - ret = reset_control_deassert(simple->resets); - if (ret) - goto err_resetc_put; - } + ret = reset_control_deassert(simple->resets); + if (ret) + goto err_resetc_put; ret = clk_bulk_get_all(simple->dev, &simple->clks); if (ret < 0) @@ -102,8 +88,7 @@ static int dwc3_of_simple_probe(struct platform_device *pdev) clk_bulk_put_all(simple->num_clocks, simple->clks); err_resetc_assert: - if (!simple->pulse_resets) - reset_control_assert(simple->resets); + reset_control_assert(simple->resets); err_resetc_put: reset_control_put(simple->resets); @@ -118,8 +103,7 @@ static void __dwc3_of_simple_teardown(struct dwc3_of_simple *simple) clk_bulk_put_all(simple->num_clocks, simple->clks); simple->num_clocks = 0; - if (!simple->pulse_resets) - reset_control_assert(simple->resets); + reset_control_assert(simple->resets); reset_control_put(simple->resets); @@ -191,8 +175,6 @@ static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "xlnx,zynqmp-dwc3" }, { .compatible = "cavium,octeon-7130-usb-uctl" }, { .compatible = "sprd,sc9860-dwc3" }, - { .compatible = "amlogic,meson-axg-dwc3" }, - { .compatible = "amlogic,meson-gxl-dwc3" }, { .compatible = "allwinner,sun50i-h6-dwc3" }, { /* Sentinel */ } }; From patchwork Thu Mar 26 13:45:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460149 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE47D161F for ; Thu, 26 Mar 2020 13:49:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A0B0F206E6 for ; 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Thu, 26 Mar 2020 06:45:28 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:5c5f:613e:f775:b6a2]) by smtp.gmail.com with ESMTPSA id h29sm4079617wrc.64.2020.03.26.06.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2020 06:45:27 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com, devicetree@vger.kernel.org Subject: [PATCH v2 13/14] doc: dt: bindings: usb: dwc3: remove amlogic compatible entries Date: Thu, 26 Mar 2020 14:45:05 +0100 Message-Id: <20200326134507.4808-14-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064530_477083_87381C6C X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:343 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Signed-off-by: Neil Armstrong Acked-by: Rob Herring --- Documentation/devicetree/bindings/usb/dwc3.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 66780a47ad85..2ef0bcc30648 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -14,8 +14,6 @@ Required properties: Exception for clocks: clocks are optional if the parent node (i.e. glue-layer) is compatible to one of the following: - "amlogic,meson-axg-dwc3" - "amlogic,meson-gxl-dwc3" "cavium,octeon-7130-usb-uctl" "qcom,dwc3" "samsung,exynos5250-dwusb3" From patchwork Thu Mar 26 13:45:06 2020 Content-Type: text/plain; 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Thu, 26 Mar 2020 06:45:29 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com, devicetree@vger.kernel.org Subject: [PATCH v2 14/14] dt-bindings: usb: dwc3: remove old DWC3 wrapper Date: Thu, 26 Mar 2020 14:45:06 +0100 Message-Id: <20200326134507.4808-15-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064533_827766_2B8D81C6 X-CRM114-Status: GOOD ( 10.55 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:341 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Martin Blumenstingl There is now an updated bindings for these SoCs making the old compatible obsolete. Signed-off-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Acked-by: Rob Herring --- .../devicetree/bindings/usb/amlogic,dwc3.txt | 42 ------------------- 1 file changed, 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt deleted file mode 100644 index 9a8b631904fd..000000000000 --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt +++ /dev/null @@ -1,42 +0,0 @@ -Amlogic Meson GX DWC3 USB SoC controller - -Required properties: -- compatible: depending on the SoC this should contain one of: - * amlogic,meson-axg-dwc3 - * amlogic,meson-gxl-dwc3 -- clocks: a handle for the "USB general" clock -- clock-names: must be "usb_general" -- resets: a handle for the shared "USB OTG" reset line -- reset-names: must be "usb_otg" - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -PHY documentation is provided in the following places: -- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt -- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt - -Example device nodes: - usb0: usb@ff500000 { - compatible = "amlogic,meson-axg-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; - resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - - dwc3: dwc3@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - }; - };