From patchwork Mon Mar 30 16:43:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11466027 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D53892A for ; Mon, 30 Mar 2020 16:44:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D5B5520781 for ; Mon, 30 Mar 2020 16:44:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="A7hYCG+D" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728534AbgC3Qof (ORCPT ); Mon, 30 Mar 2020 12:44:35 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33977 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728445AbgC3Qof (ORCPT ); Mon, 30 Mar 2020 12:44:35 -0400 Received: by mail-wr1-f67.google.com with SMTP id 65so22555055wrl.1 for ; Mon, 30 Mar 2020 09:44:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=NMjjibIIWKkjS3mT8K/LaAOt0umug6ECpFrUMrbf80Q=; b=A7hYCG+DMxsfs+p4dOlPbELVLSBYbonh32fiASwC66wGxegjqq0yAZwOa89o1z2aAb 0zy3AUO0M/juJRdqxZ2K1K8NRmXb2AnWYaLpK4URzN5fPUNjMU5cv6jV8NSMHBwB4a7I AcW3NnqcHqnKM2IEBRxqaL+HRGt6xlt2R1b6UMqhRB2NI5bzRtyy9udI6ukbMxn1xlZY iVxABTawQw2LLvT7vFMGC+alPQwH6aEpSWGmCOf2rUJL3lCYAF+VNEKVtwkhtDl5HN/J tJkzYvKvyPqC0ZFqcdCrc4G5dRtxWYHGM0CdC5sriV9tHa9y1/sk02ReiJ5ozFxIbPoe PlFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=NMjjibIIWKkjS3mT8K/LaAOt0umug6ECpFrUMrbf80Q=; b=X9aDmo/B/o1wp09OJNUmA5InXl55m7900I7zSop0ef6SaZdTheFCIXM41Jke62tED9 vahGcd8GPc2ytCvJEznjAG7Jiw4G0CSYYQ18N4CsjWLi52EuvfLh69/Y2aJVW+5HJm/t ZTEizl/8I6D0pFLvTI9aKuSQNSd2kZJ6ihBYwdl2DTwuNPEOoV+4WcGWK5SKqKgwS7Dn RkC/GlD4Cq771asA+HIOEdy/Rr56Y/TA186F6RYIx32ZOgGcIp/wdN51NlTN+79mU1NV JqF3hBAVZC9oyrRGA/CuDVFh5UbsuCHLjko0VY9j2DOZ0pr8lHBUPHJud1xGnZWtRRsM 4OXg== X-Gm-Message-State: ANhLgQ0WkbZgGJ354QiDOhUtXBWuKcFGDpJ+UFi13QUZ6iXLFyFSjg20 uenD9UrPaTrZPsKeiWSKQJryvA== X-Google-Smtp-Source: ADFU+vs+gLwL7qsbyHwdmX1dM4orp+OrvvzUsH84kvoP5OmJhnkr1ogr21XVfZ/BNVSp588do3EZ8A== X-Received: by 2002:adf:9321:: with SMTP id 30mr15110799wro.330.1585586671677; Mon, 30 Mar 2020 09:44:31 -0700 (PDT) Received: from localhost.localdomain (dh207-96-177.xnet.hr. [88.207.96.177]) by smtp.googlemail.com with ESMTPSA id h2sm146711wmb.16.2020.03.30.09.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 09:44:31 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: John Crispin , Robert Marko , Luka Perkov Subject: [PATCH v5 1/3] phy: add driver for Qualcomm IPQ40xx USB PHY Date: Mon, 30 Mar 2020 18:43:27 +0200 Message-Id: <20200330164328.2944505-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.0 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: John Crispin Add a driver to setup the USB phy on Qualcom Dakota SoCs. The driver sets up HS and SS phys. Signed-off-by: John Crispin Signed-off-by: Robert Marko Cc: Luka Perkov --- Changes from v2 to v3: * Remove magic writes as they are not needed * Correct commit message drivers/phy/qualcomm/Kconfig | 7 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 152 ++++++++++++++++++++ 3 files changed, 160 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index e46824da29f6..964bd5d784d2 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -18,6 +18,13 @@ config PHY_QCOM_APQ8064_SATA depends on OF select GENERIC_PHY +config PHY_QCOM_IPQ4019_USB + tristate "Qualcomm IPQ4019 USB PHY module" + depends on OF && ARCH_QCOM + select GENERIC_PHY + help + Support for the USB PHY on QCOM IPQ4019/Dakota chipsets. + config PHY_QCOM_IPQ806X_SATA tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" depends on ARCH_QCOM diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 283251d6a5d9..8afe6c4f5178 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o +obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c new file mode 100644 index 000000000000..7efebae6b6fd --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 John Crispin + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ipq4019_usb_phy { + struct device *dev; + struct phy *phy; + void __iomem *base; + struct reset_control *por_rst; + struct reset_control *srif_rst; +}; + +static int ipq4019_ss_phy_power_off(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + reset_control_assert(phy->por_rst); + msleep(10); + + return 0; +} + +static int ipq4019_ss_phy_power_on(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + ipq4019_ss_phy_power_off(_phy); + + reset_control_deassert(phy->por_rst); + + return 0; +} + +static struct phy_ops ipq4019_usb_ss_phy_ops = { + .power_on = ipq4019_ss_phy_power_on, + .power_off = ipq4019_ss_phy_power_off, +}; + +static int ipq4019_hs_phy_power_off(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + reset_control_assert(phy->por_rst); + msleep(10); + + reset_control_assert(phy->srif_rst); + msleep(10); + + return 0; +} + +static int ipq4019_hs_phy_power_on(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + ipq4019_hs_phy_power_off(_phy); + + reset_control_deassert(phy->srif_rst); + msleep(10); + + reset_control_deassert(phy->por_rst); + + return 0; +} + +static struct phy_ops ipq4019_usb_hs_phy_ops = { + .power_on = ipq4019_hs_phy_power_on, + .power_off = ipq4019_hs_phy_power_off, +}; + +static const struct of_device_id ipq4019_usb_phy_of_match[] = { + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops}, + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops}, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match); + +static int ipq4019_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct phy_provider *phy_provider; + struct ipq4019_usb_phy *phy; + const struct of_device_id *match; + + match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev); + if (!match) + return -ENODEV; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->dev = &pdev->dev; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + phy->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(phy->base)) { + dev_err(dev, "failed to remap register memory\n"); + return PTR_ERR(phy->base); + } + + phy->por_rst = devm_reset_control_get(phy->dev, "por_rst"); + if (IS_ERR(phy->por_rst)) { + if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER) + dev_err(dev, "POR reset is missing\n"); + return PTR_ERR(phy->por_rst); + } + + phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst"); + if (IS_ERR(phy->srif_rst)) + return PTR_ERR(phy->srif_rst); + + phy->phy = devm_phy_create(dev, NULL, match->data); + if (IS_ERR(phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(phy->phy); + } + phy_set_drvdata(phy->phy, phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver ipq4019_usb_phy_driver = { + .probe = ipq4019_usb_phy_probe, + .driver = { + .of_match_table = ipq4019_usb_phy_of_match, + .name = "ipq4019-usb-phy", + } +}; +module_platform_driver(ipq4019_usb_phy_driver); + +MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); +MODULE_AUTHOR("John Crispin "); +MODULE_LICENSE("GPL v2"); From patchwork Mon Mar 30 16:43:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11466029 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F9C892A for ; Mon, 30 Mar 2020 16:45:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E02F32073B for ; Mon, 30 Mar 2020 16:45:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="wlXWQ6ph" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729864AbgC3Qps (ORCPT ); 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[88.207.96.177]) by smtp.googlemail.com with ESMTPSA id h2sm146711wmb.16.2020.03.30.09.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 09:45:45 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: Robert Marko , John Crispin , Luka Perkov Subject: [PATCH v5 2/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document Date: Mon, 30 Mar 2020 18:43:29 +0200 Message-Id: <20200330164328.2944505-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330164328.2944505-1-robert.marko@sartura.hr> References: <20200330164328.2944505-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the binding documentation for the HS/SS USB PHY found inside Qualcom Dakota SoCs. Signed-off-by: John Crispin Signed-off-by: Robert Marko Cc: Luka Perkov --- Changes from v4 to v5: * Replace tabs with whitespaces * Add maintainer property .../bindings/phy/qcom-usb-ipq4019-phy.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml new file mode 100644 index 000000000000..4a6b5aa83925 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcom IPQ40xx Dakota HS/SS USB PHY + +maintainers: + - Robert Marko + +properties: + compatible: + enum: + - qcom,usb-ss-ipq4019-phy + - qcom,usb-hs-ipq4019-phy + + reg: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: por_rst + - const: srif_rst + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - resets + - reset-names + - "#phy-cells" + +examples: + - | + hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + phy-cells = <0>; + reg = <0xa8000 0x40>; + resets = <&gcc USB2_HSPHY_POR_ARES>, + <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + }; From patchwork Mon Mar 30 16:43:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11466031 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEB091667 for ; Mon, 30 Mar 2020 16:46:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8147E2073B for ; Mon, 30 Mar 2020 16:46:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="DW7/jlyT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729467AbgC3QqB (ORCPT ); Mon, 30 Mar 2020 12:46:01 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:53534 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726085AbgC3QqB (ORCPT ); Mon, 30 Mar 2020 12:46:01 -0400 Received: by mail-wm1-f65.google.com with SMTP id b12so20693440wmj.3 for ; Mon, 30 Mar 2020 09:46:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u01MPjpNUTMHsez0F0H9AHhzrsoSor9pky3lmIVAZDI=; b=DW7/jlyTETqYLrHSlgXGb4d3tNoy5Y5EkVfjvrxMevne+lKoL7RdSRcKV/YxnjuIsY j6LQQbArr/wwBGbKORvp1TRl/KxTuVRT5iOlyyOrG6mgMtmrYbKzrGJ+exhnnyUXblMw OOk/TxraD577MVrYZ85w+3hrnKq2R1xYuTJ2tLr8FbQjAnxS0+aozz36cSXwnjJPcmNw pJrHYiNh3UVwUICHIu3/QqGzOpXQjT788b0ZnS9igtUAfKFW4uhpBnAEAJGN+9YBoG7K AObmGcTmAjJI/O9bHCpBm6h34Iy7Sgi2dg1gsd4d+R5VpBdNzbjb3rTfHsrlNmFe2d9v NbVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u01MPjpNUTMHsez0F0H9AHhzrsoSor9pky3lmIVAZDI=; b=KF1hXg8jhxPsRQeecz9GFqSe6xym9Ec7oErt9fj0fBu7rma7Zng8EjkLLdz/5jXSpN xggSJQtahaWX7E6829ZzUpn+ad/16TIFPuUqTRI8+lMm4JbwUyg+IwjAJ+kWYeqJGazP XLkLcj+dLjodj64+BTF6gDz+Er8rrfLJk3QyhbRH6hP6O74o32fCmIlxY24hr3Kkm1GM HVvKZNBHWA241UKWeUPzBo5KCc2DEUthVbiVw9Gj0JOBatN5WTZJ2v/a9V+tAHKImuve cyEyWbKP8onl73IsIVxmjtuCFleFOll3t7Ky45pIhwEh9GNq6YczdzFYy2sO12Ce9Jgd 6cag== X-Gm-Message-State: ANhLgQ39Mhc7ZAW1m3oebAz28Tk/nPmEzZNFqkvbBrFmOoBkGFoY757f UZHJ8Z19ekvlBCcos2pRhPKdFA== X-Google-Smtp-Source: ADFU+vuLKI27cJ4EToB73D4/54U6nwIjhdYCL+6daR5BNyCULI+4LUEX65XizZCgokPo0e4zUlBmXw== X-Received: by 2002:a1c:a9cf:: with SMTP id s198mr147042wme.115.1585586760265; Mon, 30 Mar 2020 09:46:00 -0700 (PDT) Received: from localhost.localdomain (dh207-96-177.xnet.hr. [88.207.96.177]) by smtp.googlemail.com with ESMTPSA id h2sm146711wmb.16.2020.03.30.09.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 09:45:59 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: John Crispin , Robert Marko , Luka Perkov Subject: [PATCH v5 3/3] ARM: dts: qcom: ipq4019: add USB devicetree nodes Date: Mon, 30 Mar 2020 18:43:31 +0200 Message-Id: <20200330164328.2944505-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330164328.2944505-1-robert.marko@sartura.hr> References: <20200330164328.2944505-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: John Crispin Since we now have driver for the USB PHY, lets add the necessary nodes to DTSI. Signed-off-by: John Crispin Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 418f9a022336..2ee5f05d5a43 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -109,5 +109,25 @@ wifi@a000000 { wifi@a800000 { status = "ok"; }; + + usb3_ss_phy: ssphy@9a000 { + status = "ok"; + }; + + usb3_hs_phy: hsphy@a6000 { + status = "ok"; + }; + + usb3: usb3@8af8800 { + status = "ok"; + }; + + usb2_hs_phy: hsphy@a8000 { + status = "ok"; + }; + + usb2: usb2@60f8800 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bfa9ce4c6e69..ee45253361cb 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -576,5 +576,79 @@ wifi1: wifi@a800000 { "legacy"; status = "disabled"; }; + + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; + reg = <0x9a000 0x800>; + reg-names = "phy_base"; + resets = <&gcc USB3_UNIPHY_PHY_ARES>; + reset-names = "por_rst"; + status = "disabled"; + }; + + usb3_hs_phy: hsphy@a6000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa6000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb3@8af8800 { + compatible = "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB3_MASTER_CLK>, + <&gcc GCC_USB3_SLEEP_CLK>, + <&gcc GCC_USB3_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xf8000>; + interrupts = ; + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + }; + }; + + usb2_hs_phy: hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa8000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb2@60f8800 { + compatible = "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB2_MASTER_CLK>, + <&gcc GCC_USB2_SLEEP_CLK>, + <&gcc GCC_USB2_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@6000000 { + compatible = "snps,dwc3"; + reg = <0x6000000 0xf8000>; + interrupts = ; + phys = <&usb2_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + }; + }; }; };