From patchwork Tue Mar 31 07:55:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11466845 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2040992A for ; Tue, 31 Mar 2020 07:56:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F2D36208E4 for ; Tue, 31 Mar 2020 07:56:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="sYMqquEK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730161AbgCaH4j (ORCPT ); Tue, 31 Mar 2020 03:56:39 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:23447 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729925AbgCaH4i (ORCPT ); Tue, 31 Mar 2020 03:56:38 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1585641398; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=nthYnpwagHT230rYskRhSng5IhNPXUQv68G+VcY197o=; b=sYMqquEKC++JHnv/02CqUEKhInYRCOBaV6NfNxZNHjRzijq5RYXRCq/b2QZdQzkxsXZVu75z k+6Qy6fEkd8g+KDH80VQ+y4MHxpXI9dDMNdcDeC4sLbwKt3jGTNquiN1Gv4WdFVvGk0EJSwI Jj+zlLxeJ6mqxAnehNORnjDSGkI= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e82f7b4.7fb70ed98458-smtp-out-n01; Tue, 31 Mar 2020 07:56:36 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 3A5D8C433D2; Tue, 31 Mar 2020 07:56:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4CB05C433BA; Tue, 31 Mar 2020 07:56:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4CB05C433BA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, Sharat Masetty Subject: [PATCH 1/5] arm64: dts: qcom: sc7180: Add interconnect bindings for GPU Date: Tue, 31 Mar 2020 13:25:49 +0530 Message-Id: <1585641353-23229-2-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> References: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the interconnect bindings to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 1097e8b..51630dd 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1718,6 +1718,8 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From patchwork Tue Mar 31 07:55:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11466857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8AB7392A for ; Tue, 31 Mar 2020 07:56:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6883720748 for ; Tue, 31 Mar 2020 07:56:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="fQXDJkor" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730131AbgCaH4y (ORCPT ); Tue, 31 Mar 2020 03:56:54 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:23447 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729925AbgCaH4x (ORCPT ); Tue, 31 Mar 2020 03:56:53 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1585641413; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=jgvxUaNnnaWHqq0izF2zyxOsOupTAxhxGBrh7lVSzvQ=; b=fQXDJkorNJrYKyPbwHTBkAeekCLuHby9Jgmyf8uKyoY9RrQBe4SAopC/CkwyQxz7P2C0vTz2 1nNvK3X53MdSi2HU6kumxAVFYq3VKqR7L678aR4DV835OL+XfjdFknae89iPp+LIo4lwBFML Q1Uj/gHqD6u0d+fAIfE11pxxKnA= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e82f7b9.7f72ad53a570-smtp-out-n01; Tue, 31 Mar 2020 07:56:41 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id AFC1FC4478F; Tue, 31 Mar 2020 07:56:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5862FC4478C; Tue, 31 Mar 2020 07:56:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5862FC4478C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, Sharat Masetty Subject: [PATCH 2/5] arm64: dts: qcom: sc7180: Add GPU DDR BW opp table Date: Tue, 31 Mar 2020 13:25:50 +0530 Message-Id: <1585641353-23229-3-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> References: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds a new opp table listing the GPU DDR bandwidth opps. Also adds a required_opp binding to the GPUs main OPP table which holds a phandle to a bandwidth opp in the new table. This enables linking the GPU power level opp to the DDR bandwidth opp and helps with scaling DDR along with GPU frequency. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 50 +++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 51630dd..74b023b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1715,7 +1715,8 @@ reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; interrupts = ; iommus = <&adreno_smmu 0>; - operating-points-v2 = <&gpu_opp_table>; + operating-points-v2 = <&gpu_opp_table>, + <&gpu_ddr_bw_opp_table>; qcom,gmu = <&gmu>; interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; @@ -1726,40 +1727,87 @@ opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-level = ; + required-opps = <&gpu_ddr_bw_opp9>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; opp-level = ; + required-opps = <&gpu_ddr_bw_opp8>; }; opp-565000000 { opp-hz = /bits/ 64 <565000000>; opp-level = ; + required-opps = <&gpu_ddr_bw_opp6>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; opp-level = ; + required-opps = <&gpu_ddr_bw_opp6>; }; opp-355000000 { opp-hz = /bits/ 64 <355000000>; opp-level = ; + required-opps = <&gpu_ddr_bw_opp4>; }; opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-level = ; + required-opps = <&gpu_ddr_bw_opp4>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; opp-level = ; + required-opps = <&gpu_ddr_bw_opp2>; }; }; }; + gpu_ddr_bw_opp_table: gpu-ddr-bw-opp-table { + compatible = "operating-points-v2"; + + gpu_ddr_bw_opp1: opp-300000000 { + opp-peak-kBps =/bits/ 32 <1200000>; + }; + + gpu_ddr_bw_opp2: opp-451000000 { + opp-peak-kBps =/bits/ 32 <1804000>; + }; + + gpu_ddr_bw_opp3: opp-547000000 { + opp-peak-kBps =/bits/ 32 <2188000>; + }; + + gpu_ddr_bw_opp4: opp-768000000 { + opp-peak-kBps =/bits/ 32 <3072000>; + }; + + gpu_ddr_bw_opp5: opp-1017000000 { + opp-peak-kBps =/bits/ 32 <4068000>; + }; + + gpu_ddr_bw_opp6: opp-1353000000 { + opp-peak-kBps =/bits/ 32 <5412000>; + }; + + gpu_ddr_bw_opp7: opp-1555000000 { + opp-peak-kBps =/bits/ 32 <6220000>; + }; + + gpu_ddr_bw_opp8: opp-1804000000 { + opp-peak-kBps =/bits/ 32 <7216000>; + }; + + gpu_ddr_bw_opp9: opp-2133000000 { + opp-peak-kBps =/bits/ 32 <8532000>; + }; + }; + adreno_smmu: iommu@5040000 { compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; reg = <0 0x05040000 0 0x10000>; From patchwork Tue Mar 31 07:55:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11466849 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53CDB912 for ; Tue, 31 Mar 2020 07:56:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2A6E42083E for ; Tue, 31 Mar 2020 07:56:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="ckBQCaSS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730076AbgCaH4q (ORCPT ); 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Tue, 31 Mar 2020 07:56:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 86765C0451C; Tue, 31 Mar 2020 07:56:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 86765C0451C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, Sharat Masetty Subject: [PATCH 3/5] drm: msm: scale DDR BW along with GPU frequency Date: Tue, 31 Mar 2020 13:25:51 +0530 Message-Id: <1585641353-23229-4-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> References: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds support to parse the OPP tables attached the GPU device, the main opp table and the DDR bandwidth opp table. Additionally, vote for the GPU->DDR bandwidth when setting the GPU frequency by querying the linked DDR BW opp to the GPU opp. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 41 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 44 +++++++++++++++++++++++++++++---- drivers/gpu/drm/msm/msm_gpu.h | 9 +++++++ 3 files changed, 84 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 748cd37..489d9b6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -100,6 +100,40 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); } +void a6xx_gmu_set_icc_vote(struct msm_gpu *gpu, unsigned long gpu_freq) +{ + struct dev_pm_opp *gpu_opp, *ddr_opp; + struct opp_table **tables = gpu->opp_tables; + unsigned long peak_bw; + + if (!gpu->opp_tables[GPU_DDR_OPP_TABLE_INDEX]) + goto done; + + gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); + if (IS_ERR_OR_NULL(gpu_opp)) + goto done; + + ddr_opp = dev_pm_opp_xlate_required_opp(tables[GPU_OPP_TABLE_INDEX], + tables[GPU_DDR_OPP_TABLE_INDEX], + gpu_opp); + dev_pm_opp_put(gpu_opp); + + if (IS_ERR_OR_NULL(ddr_opp)) + goto done; + + peak_bw = dev_pm_opp_get_bw(ddr_opp, NULL); + dev_pm_opp_put(ddr_opp); + + icc_set_bw(gpu->icc_path, 0, peak_bw); + return; +done: + /* + * If there is a problem, for now leave it at max so that the + * performance is nominal. + */ + icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); +} + static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) { struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); @@ -128,11 +162,8 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) gmu->freq = gmu->gpu_freqs[index]; - /* - * Eventually we will want to scale the path vote with the frequency but - * for now leave it at max so that the performance is nominal. - */ - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + if (gpu->icc_path) + a6xx_gmu_set_icc_vote(gpu, gmu->freq); } void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 2d13694..bbbcc7a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -882,7 +882,7 @@ static int adreno_get_pwrlevels(struct device *dev, { unsigned long freq = ULONG_MAX; struct dev_pm_opp *opp; - int ret; + int ret, i; gpu->fast_rate = 0; @@ -890,9 +890,29 @@ static int adreno_get_pwrlevels(struct device *dev, if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) ret = adreno_get_legacy_pwrlevels(dev); else { - ret = dev_pm_opp_of_add_table(dev); - if (ret) - DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); + int count = of_count_phandle_with_args(dev->of_node, + "operating-points-v2", NULL); + + count = min(count, GPU_DDR_OPP_TABLE_INDEX + 1); + count = max(count, 1); + + for (i = 0; i < count; i++) { + ret = dev_pm_opp_of_add_table_indexed(dev, i); + if (ret) { + DRM_DEV_ERROR(dev, "Add OPP table %d: failed %d\n", + i, ret); + goto err; + } + + gpu->opp_tables[i] = + dev_pm_opp_get_opp_table_indexed(dev, i); + if (!gpu->opp_tables[i]) { + DRM_DEV_ERROR(dev, "Get OPP table failed index %d\n", + i); + ret = -EINVAL; + goto err; + } + } } if (!ret) { @@ -919,12 +939,24 @@ static int adreno_get_pwrlevels(struct device *dev, gpu->icc_path = NULL; return 0; +err: + for (; i >= 0; i--) { + if (gpu->opp_tables[i]) { + dev_pm_opp_put_opp_table(gpu->opp_tables[i]); + gpu->opp_tables[i] = NULL; + } + } + + dev_pm_opp_remove_table(dev); + return ret; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) { + int ret = 0; + struct adreno_platform_config *config = pdev->dev.platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; @@ -945,7 +977,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.nr_rings = nr_rings; - adreno_get_pwrlevels(&pdev->dev, gpu); + ret = adreno_get_pwrlevels(&pdev->dev, gpu); + if (ret) + return ret; pm_runtime_set_autosuspend_delay(&pdev->dev, adreno_gpu->info->inactive_period); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index ab8f0f9c..5b98b48 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -66,6 +66,12 @@ struct msm_gpu_funcs { void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); }; +/* opp table indices */ +enum { + GPU_OPP_TABLE_INDEX, + GPU_DDR_OPP_TABLE_INDEX, +}; + struct msm_gpu { const char *name; struct drm_device *dev; @@ -113,6 +119,9 @@ struct msm_gpu { struct icc_path *icc_path; + /* gpu/ddr opp tables */ + struct opp_table *opp_tables[2]; + /* Hang and Inactivity Detection: */ #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ From patchwork Tue Mar 31 07:55:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11466867 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1E5A17EF for ; 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spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, Sharat Masetty Subject: [PATCH 4/5] drm: msm: a6xx: Fix off by one error when setting GPU freq Date: Tue, 31 Mar 2020 13:25:52 +0530 Message-Id: <1585641353-23229-5-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> References: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch fixes an error in the for loop, thereby allowing search on the full list of possible GPU power levels. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 489d9b6..81b8559 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -176,7 +176,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) if (freq == gmu->freq) return; - for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) + for (perf_index = 0; perf_index < gmu->nr_gpu_freqs; perf_index++) if (freq == gmu->gpu_freqs[perf_index]) break; From patchwork Tue Mar 31 07:55:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11466863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 814F417EF for ; Tue, 31 Mar 2020 07:57:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 583FD20BED for ; Tue, 31 Mar 2020 07:57:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="rvUYpuvv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730255AbgCaH5D (ORCPT ); Tue, 31 Mar 2020 03:57:03 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:23447 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730237AbgCaH5C (ORCPT ); Tue, 31 Mar 2020 03:57:02 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1585641422; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=VT9/ErTi2g1chyk6bUNJTnT/qqr1194jK5RfTnp8tS4=; b=rvUYpuvvq/A2z/VTfnSHylJ/F5ApaTMN8dhCoU98IC6jZ3m8N95WEOUOL1IRF2B8fX9KB1vV zODrLPgF9+ufnAWmHZGZOL0AFZ3dktDy4GsdS3jKznb0NJEW1AtX923YGMVWfDapatBrlhgd 5LWIg3STUmC6jpMPjO7waTO9Suo= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e82f7c9.7f3e5fc79420-smtp-out-n03; Tue, 31 Mar 2020 07:56:57 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 21CD4C4478F; Tue, 31 Mar 2020 07:56:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 39EB0C44795; Tue, 31 Mar 2020 07:56:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 39EB0C44795 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, Sharat Masetty Subject: [PATCH 5/5] dt-bindings: drm/msm/gpu: Document OPP phandle list for the GPU Date: Tue, 31 Mar 2020 13:25:53 +0530 Message-Id: <1585641353-23229-6-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> References: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update the documentation for listing the multiple optional GPU and the DDR OPP tables to help enable DDR scaling. Signed-off-by: Sharat Masetty Reviewed-by: Rob Herring --- .../devicetree/bindings/display/msm/gpu.txt | 63 +++++++++++++++++++++- 1 file changed, 61 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 70025cb..ff3ae1b 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -21,7 +21,10 @@ Required properties: following devices should not list clocks: - qcom,adreno-630.2 - iommus: optional phandle to an adreno iommu instance -- operating-points-v2: optional phandle to the OPP operating points +- operating-points-v2: optional phandles to the OPP operating point tables + one for the GPU OPPs and the other for the GPU->DDR OPPs. Note that if + multiple OPP tables are specified, the GPU OPP table(considered primary) + should be the first in the phandle list. - interconnects: optional phandle to an interconnect provider. See ../interconnect/interconnect.txt for details. - qcom,gmu: For GMU attached devices a phandle to the GMU device that will @@ -75,7 +78,7 @@ Example a6xx (with GMU): iommus = <&adreno_smmu 0>; - operating-points-v2 = <&gpu_opp_table>; + operating-points-v2 = <&gpu_opp_table>, <&gpu_ddr_bw_opp_table>; interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; @@ -85,5 +88,61 @@ Example a6xx (with GMU): memory-region = <&zap_shader_region>; firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn" }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + required-opps = <&gpu_ddr_bw_opp6>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + required-opps = <&gpu_ddr_bw_opp4>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + required-opps = <&gpu_ddr_bw_opp4>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + required-opps = <&gpu_ddr_bw_opp2>; + }; + }; + + gpu_ddr_bw_opp_table: gpu-ddr-bw-opp-table { + compatible = "operating-points-v2"; + + gpu_ddr_bw_opp1: opp-300000000 { + opp-peak-kBps =/bits/ 32 <1200000>; + }; + + gpu_ddr_bw_opp2: opp-451000000 { + opp-peak-kBps =/bits/ 32 <1804000>; + }; + + gpu_ddr_bw_opp3: opp-547000000 { + opp-peak-kBps =/bits/ 32 <2188000>; + }; + + gpu_ddr_bw_opp4: opp-768000000 { + opp-peak-kBps =/bits/ 32 <3072000>; + }; + + gpu_ddr_bw_opp5: opp-1017000000 { + opp-peak-kBps =/bits/ 32 <4068000>; + }; + + gpu_ddr_bw_opp6: opp-1353000000 { + opp-peak-kBps =/bits/ 32 <5412000>; + }; + }; }; };