From patchwork Wed Apr 1 00:41:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11468529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 452721668 for ; Wed, 1 Apr 2020 00:39:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23BCF20787 for ; Wed, 1 Apr 2020 00:39:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23BCF20787 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A35DD6E8AE; Wed, 1 Apr 2020 00:39:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 28F4B6E8AA for ; Wed, 1 Apr 2020 00:39:55 +0000 (UTC) IronPort-SDR: +Wk7MDo8jeQ6D+5XeVgVHhy1A1/n06iG7MzmrH+WjzsGWAM3S1kebw0wAxL7fHX9Ogl7CplBCz zrongFVvw0EA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2020 17:39:54 -0700 IronPort-SDR: g4ReFslKosdzGvQk4bUMmacGwsqf6B7hr2ik7GjsHf+mY/+NXea3ygN12cp183A2Voa7glfhOl EhZ9JidcVtkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,329,1580803200"; d="scan'208";a="295169799" Received: from akahan1-mobl3.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.252.143.47]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2020 17:39:53 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2020 17:41:15 -0700 Message-Id: <20200401004120.408586-1-jose.souza@intel.com> X-Mailer: git-send-email 2.26.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/display: Move out code to return the digital_port of the aux ch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Moving the code to return the digital port of the aux channel also removing the intel_phy_is_tc() to make it generic. digital_port will be needed in icl_tc_phy_aux_power_well_enable() so adding it as a parameter to icl_tc_port_assert_ref_held(). While at at removing the duplicated call to icl_tc_phy_aux_ch() in icl_tc_port_assert_ref_held(). Signed-off-by: José Roberto de Souza Reported-by: kbuild test robot Reported-by: kbuild test robot --- .../drm/i915/display/intel_display_power.c | 38 ++++++++++--------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 433e5a81dd4d..02a07aa710e4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -500,26 +500,14 @@ static int power_well_async_ref_count(struct drm_i915_private *dev_priv, return refs; } -static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static struct intel_digital_port * +aux_ch_to_digital_port(struct drm_i915_private *dev_priv, + enum aux_ch aux_ch) { - enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); struct intel_digital_port *dig_port = NULL; struct intel_encoder *encoder; - /* Bypass the check if all references are released asynchronously */ - if (power_well_async_ref_count(dev_priv, power_well) == - power_well->count) - return; - - aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); - for_each_intel_encoder(&dev_priv->drm, encoder) { - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - - if (!intel_phy_is_tc(dev_priv, phy)) - continue; - /* We'll check the MST primary port */ if (encoder->type == INTEL_OUTPUT_DP_MST) continue; @@ -536,6 +524,18 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, break; } + return dig_port; +} + +static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well, + struct intel_digital_port *dig_port) +{ + /* Bypass the check if all references are released asynchronously */ + if (power_well_async_ref_count(dev_priv, power_well) == + power_well->count) + return; + if (drm_WARN_ON(&dev_priv->drm, !dig_port)) return; @@ -558,9 +558,10 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); + struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch); u32 val; - icl_tc_port_assert_ref_held(dev_priv, power_well); + icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port); val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch)); val &= ~DP_AUX_CH_CTL_TBT_IO; @@ -588,7 +589,10 @@ static void icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - icl_tc_port_assert_ref_held(dev_priv, power_well); + enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); + struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch); + + icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port); hsw_power_well_disable(dev_priv, power_well); } From patchwork Wed Apr 1 00:41:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11468531 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 541101668 for ; Wed, 1 Apr 2020 00:40:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B43220787 for ; Wed, 1 Apr 2020 00:40:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3B43220787 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 824CF6E8AA; Wed, 1 Apr 2020 00:39:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 624196E8AE for ; Wed, 1 Apr 2020 00:39:55 +0000 (UTC) IronPort-SDR: CcAHEjoC0yi1fXTLp4CLl4hheV1J3lsVNnsQ5mSE85I4WbhEY5lQNqrM+e99wx6Ydku7CiEYg3 cjjAIv5IHH8A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2020 17:39:54 -0700 IronPort-SDR: 1wp+ADwOZ0wbwGBQ+X90qjpsaYD0koPpsBuZDfwfLtLumVaYgCi7qHrDV+LSn0q3WwlFdqW60B 5dAj2j3FfPOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,329,1580803200"; d="scan'208";a="295169802" Received: from akahan1-mobl3.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.252.143.47]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2020 17:39:53 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2020 17:41:16 -0700 Message-Id: <20200401004120.408586-2-jose.souza@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200401004120.408586-1-jose.souza@intel.com> References: <20200401004120.408586-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/tc: Export tc_port_live_status_mask() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It will be used by ICL TC cold exit sequence outside of intel_tc. No functional change here. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_tc.c | 10 +++++----- drivers/gpu/drm/i915/display/intel_tc.h | 2 ++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 9b850c11aa78..d944be935423 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -170,7 +170,7 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, dig_port->tc_legacy_port = !dig_port->tc_legacy_port; } -static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) +u32 intel_tc_port_live_status_mask(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); @@ -310,7 +310,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port, * Now we have to re-check the live state, in case the port recently * became disconnected. Not necessary for legacy mode. */ - if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) { + if (!(intel_tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) { DRM_DEBUG_KMS("Port %s: PHY sudden disconnect\n", dig_port->tc_port_name); goto out_set_safe_mode; @@ -377,7 +377,7 @@ static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port) static enum tc_port_mode intel_tc_port_get_current_mode(struct intel_digital_port *dig_port) { - u32 live_status_mask = tc_port_live_status_mask(dig_port); + u32 live_status_mask = intel_tc_port_live_status_mask(dig_port); bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port); enum tc_port_mode mode; @@ -398,7 +398,7 @@ intel_tc_port_get_current_mode(struct intel_digital_port *dig_port) static enum tc_port_mode intel_tc_port_get_target_mode(struct intel_digital_port *dig_port) { - u32 live_status_mask = tc_port_live_status_mask(dig_port); + u32 live_status_mask = intel_tc_port_live_status_mask(dig_port); if (live_status_mask) return fls(live_status_mask) - 1; @@ -489,7 +489,7 @@ bool intel_tc_port_connected(struct intel_digital_port *dig_port) bool is_connected; intel_tc_port_lock(dig_port); - is_connected = tc_port_live_status_mask(dig_port) & + is_connected = intel_tc_port_live_status_mask(dig_port) & BIT(dig_port->tc_mode); intel_tc_port_unlock(dig_port); diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h index 463f1b3c836f..a1afcee48818 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.h +++ b/drivers/gpu/drm/i915/display/intel_tc.h @@ -28,4 +28,6 @@ bool intel_tc_port_ref_held(struct intel_digital_port *dig_port); void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy); +u32 intel_tc_port_live_status_mask(struct intel_digital_port *dig_port); + #endif /* __INTEL_TC_H__ */ From patchwork Wed Apr 1 00:41:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11468537 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 179C61668 for ; Wed, 1 Apr 2020 00:40:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F40D320787 for ; Wed, 1 Apr 2020 00:40:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F40D320787 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C9B3C6E8B3; Wed, 1 Apr 2020 00:39:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B3FD6E8AA for ; Wed, 1 Apr 2020 00:39:55 +0000 (UTC) IronPort-SDR: egRS2ojGqORiw9l9wukgvrT0khcMc0Bg06SOn3rUezs0e7WiZYTo/l/vyCrNkD9YCzhM9DTzMu TLegEGa4BEFQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2020 17:39:54 -0700 IronPort-SDR: U2gzBJcCMN2D5I5vzAZGOJhV4auV8nI5VY5/ko2ojOBAs0b3sayoR9fDpS9ROa0ALHA8FjorMF YZvnmnwAOsdg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,329,1580803200"; d="scan'208";a="295169805" Received: from akahan1-mobl3.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.252.143.47]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2020 17:39:54 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2020 17:41:17 -0700 Message-Id: <20200401004120.408586-3-jose.souza@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200401004120.408586-1-jose.souza@intel.com> References: <20200401004120.408586-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/display: Add intel_aux_ch_to_power_domain() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cooper Chiou , Kai-Heng Feng Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a similar function to intel_aux_power_domain() but it do not care about TBT ports, this will be needed by GEN11 TC sequences. Cc: Imre Deak Cc: Cooper Chiou Cc: Kai-Heng Feng Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++-- drivers/gpu/drm/i915/display/intel_display.h | 2 ++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e09a11b1e509..7e06d2306dcd 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7278,7 +7278,17 @@ intel_aux_power_domain(struct intel_digital_port *dig_port) } } - switch (dig_port->aux_ch) { + return intel_aux_ch_to_power_domain(dig_port->aux_ch); +} + +/* + * Converts aux_ch to power_domain without caring about TBT ports for that use + * intel_aux_power_domain() + */ +enum intel_display_power_domain +intel_aux_ch_to_power_domain(enum aux_ch aux_ch) +{ + switch (aux_ch) { case AUX_CH_A: return POWER_DOMAIN_AUX_A; case AUX_CH_B: @@ -7294,7 +7304,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port) case AUX_CH_G: return POWER_DOMAIN_AUX_G; default: - MISSING_CASE(dig_port->aux_ch); + MISSING_CASE(aux_ch); return POWER_DOMAIN_AUX_A; } } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index adb1225a3480..ad50119c0453 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -579,6 +579,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state); enum intel_display_power_domain intel_port_to_power_domain(enum port port); enum intel_display_power_domain intel_aux_power_domain(struct intel_digital_port *dig_port); +enum intel_display_power_domain +intel_aux_ch_to_power_domain(enum aux_ch aux_ch); void intel_mode_from_pipe_config(struct drm_display_mode *mode, struct intel_crtc_state *pipe_config); void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, From patchwork Wed Apr 1 00:41:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11468539 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09B6014B4 for ; Wed, 1 Apr 2020 00:40:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E649E20787 for ; Wed, 1 Apr 2020 00:40:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E649E20787 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3612C6E8B5; Wed, 1 Apr 2020 00:39:59 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB1576E8AF for ; Wed, 1 Apr 2020 00:39:55 +0000 (UTC) IronPort-SDR: tFMM0cIrVIK5OArS+IqZGCSrg3Ik6OVyCTeFJjqYMTa6yXLI4Z1H2Xolm7C+rC11/BtYors01V hUwUAghcPhRw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2020 17:39:54 -0700 IronPort-SDR: qu9vAtwishrNXoyf+TnDp/yaoeu3nYaPE/UQadF5oK8zHpd2rYp7LqqbwAkVk+aFw44GD7lHnx Scucln2K2VrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,329,1580803200"; d="scan'208";a="295169808" Received: from akahan1-mobl3.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.252.143.47]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2020 17:39:54 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2020 17:41:18 -0700 Message-Id: <20200401004120.408586-4-jose.souza@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200401004120.408586-1-jose.souza@intel.com> References: <20200401004120.408586-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/display: Split hsw_power_well_enable() into two X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a preparation for ICL TC cold exit sequences. Signed-off-by: José Roberto de Souza --- .../drm/i915/display/intel_display_power.c | 39 +++++++++++++++---- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 02a07aa710e4..dbd61517ba63 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -353,16 +353,16 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, SKL_FUSE_PG_DIST_STATUS(pg), 1)); } -static void hsw_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void _hsw_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; int pw_idx = power_well->desc->hsw.idx; - bool wait_fuses = power_well->desc->hsw.has_fuses; - enum skl_power_gate uninitialized_var(pg); u32 val; - if (wait_fuses) { + if (power_well->desc->hsw.has_fuses) { + enum skl_power_gate pg; + pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : SKL_PW_CTL_IDX_TO_PG(pw_idx); /* @@ -379,25 +379,46 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, val = intel_de_read(dev_priv, regs->driver); intel_de_write(dev_priv, regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); +} + +static void _hsw_power_well_continue_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + int pw_idx = power_well->desc->hsw.idx; + hsw_wait_for_power_well_enable(dev_priv, power_well); /* Display WA #1178: cnl */ if (IS_CANNONLAKE(dev_priv) && pw_idx >= GLK_PW_CTL_IDX_AUX_B && pw_idx <= CNL_PW_CTL_IDX_AUX_F) { + u32 val; + val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx)); val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val); } - if (wait_fuses) + if (power_well->desc->hsw.has_fuses) { + enum skl_power_gate pg; + + pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : + SKL_PW_CTL_IDX_TO_PG(pw_idx); gen9_wait_for_power_well_fuses(dev_priv, pg); + } hsw_power_well_post_enable(dev_priv, power_well->desc->hsw.irq_pipe_mask, power_well->desc->hsw.has_vga); } +static void hsw_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + _hsw_power_well_enable(dev_priv, power_well); + _hsw_power_well_continue_enable(dev_priv, power_well); +} + static void hsw_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { @@ -569,7 +590,11 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, val |= DP_AUX_CH_CTL_TBT_IO; intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val); - hsw_power_well_enable(dev_priv, power_well); + _hsw_power_well_enable(dev_priv, power_well); + + /* TODO ICL TC cold handling */ + + _hsw_power_well_continue_enable(dev_priv, power_well); if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) { enum tc_port tc_port; From patchwork Wed Apr 1 00:41:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11468535 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 093C51668 for ; Wed, 1 Apr 2020 00:40:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4BF620787 for ; Wed, 1 Apr 2020 00:40:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E4BF620787 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 812DF6E8B0; Wed, 1 Apr 2020 00:39:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 053BB6E8B0 for ; Wed, 1 Apr 2020 00:39:55 +0000 (UTC) IronPort-SDR: nN0CQ5JZfgCLik6YAuNpo+x7unQ2doEPChsc8y7xHX0wnseBMEbKLzj2mAL4YMOkO2vaSuuFoK EFKS6UOAPfLQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2020 17:39:55 -0700 IronPort-SDR: OJow4Ajj+f1WTIX40Em2jPEIhIASBs7pI++bpLLL+5ccHouF5Ic36+t3LGUVut/97E+Pmvg9Ad Yws2dMzMjhJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,329,1580803200"; d="scan'208";a="295169811" Received: from akahan1-mobl3.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.252.143.47]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2020 17:39:54 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2020 17:41:19 -0700 Message-Id: <20200401004120.408586-5-jose.souza@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200401004120.408586-1-jose.souza@intel.com> References: <20200401004120.408586-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/tc/icl: Implement TC cold sequences X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cooper Chiou , Kai-Heng Feng Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is required for legacy/static TC ports as IOM is not aware of the connection and will not trigger the TC cold exit. Just request PCODE to exit TCCOLD is not enough as it could enter again be driver makes use of the port, to prevent it BSpec states that aux powerwell should be held. So here embedding the TC cold exit sequence into ICL aux enable, it will enable aux, request tc cold exit and depending in the TC live state continue with the regular aux enable sequence. And then turning on aux power well during tc lock and turning off during unlock both depending into the TC port refcount. BSpec: 21750 Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296 Cc: Imre Deak Cc: Cooper Chiou Cc: Kai-Heng Feng Signed-off-by: José Roberto de Souza --- Will run some tests in the office with TBT dockstation to check if it will be a issue keep both aux enabled. Otherwise more changes will be required here. .../drm/i915/display/intel_display_power.c | 12 ++++- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_tc.c | 47 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_tc.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 1 + 5 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index dbd61517ba63..1ccd57d645c7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -592,9 +592,17 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, _hsw_power_well_enable(dev_priv, power_well); - /* TODO ICL TC cold handling */ + if (INTEL_GEN(dev_priv) == 11) + intel_tc_icl_tc_cold_exit(dev_priv); - _hsw_power_well_continue_enable(dev_priv, power_well); + /* + * To avoid power well enable timeouts when disconnected or in TBT mode + * when doing the TC cold exit sequence for GEN11 + */ + if (INTEL_GEN(dev_priv) != 11 || + (intel_tc_port_live_status_mask(dig_port) & + (TC_PORT_LEGACY | TC_PORT_DP_ALT))) + _hsw_power_well_continue_enable(dev_priv, power_well); if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) { enum tc_port tc_port; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 176ab5f1e867..a9a4a3c1b4d7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1391,6 +1391,7 @@ struct intel_digital_port { enum intel_display_power_domain ddi_io_power_domain; struct mutex tc_lock; /* protects the TypeC port mode */ intel_wakeref_t tc_lock_wakeref; + intel_wakeref_t tc_cold_wakeref; int tc_link_refcount; bool tc_legacy_port:1; char tc_port_name[8]; diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index d944be935423..b6d67f069ef7 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -7,6 +7,7 @@ #include "intel_display.h" #include "intel_display_types.h" #include "intel_dp_mst.h" +#include "intel_sideband.h" #include "intel_tc.h" static const char *tc_port_mode_name(enum tc_port_mode mode) @@ -506,6 +507,13 @@ static void __intel_tc_port_lock(struct intel_digital_port *dig_port, mutex_lock(&dig_port->tc_lock); + if (INTEL_GEN(i915) == 11 && dig_port->tc_link_refcount == 0) { + enum intel_display_power_domain aux_domain; + + aux_domain = intel_aux_ch_to_power_domain(dig_port->aux_ch); + dig_port->tc_cold_wakeref = intel_display_power_get(i915, aux_domain); + } + if (!dig_port->tc_link_refcount && intel_tc_port_needs_reset(dig_port)) intel_tc_port_reset_mode(dig_port, required_lanes); @@ -519,15 +527,30 @@ void intel_tc_port_lock(struct intel_digital_port *dig_port) __intel_tc_port_lock(dig_port, 1); } +static void icl_tc_cold_unblock(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + enum intel_display_power_domain aux_domain; + intel_wakeref_t tc_cold_wakeref; + + if (INTEL_GEN(i915) != 11 || dig_port->tc_link_refcount > 0) + return; + + tc_cold_wakeref = fetch_and_zero(&dig_port->tc_cold_wakeref); + aux_domain = intel_aux_ch_to_power_domain(dig_port->aux_ch); + intel_display_power_put_async(i915, aux_domain, tc_cold_wakeref); +} + void intel_tc_port_unlock(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref); + icl_tc_cold_unblock(dig_port); + mutex_unlock(&dig_port->tc_lock); - intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE, - wakeref); + intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); } bool intel_tc_port_ref_held(struct intel_digital_port *dig_port) @@ -548,6 +571,7 @@ void intel_tc_port_put_link(struct intel_digital_port *dig_port) { mutex_lock(&dig_port->tc_lock); dig_port->tc_link_refcount--; + icl_tc_cold_unblock(dig_port); mutex_unlock(&dig_port->tc_lock); } @@ -568,3 +592,22 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) dig_port->tc_link_refcount = 0; tc_port_load_fia_params(i915, dig_port); } + +void intel_tc_icl_tc_cold_exit(struct drm_i915_private *i915) +{ + int ret; + + do { + ret = sandybridge_pcode_write_timeout(i915, + ICL_PCODE_EXIT_TCCOLD, + 0, 250, 1); + + } while (ret == -EAGAIN); + + if (!ret) + msleep(1); + + if (ret) + drm_dbg_kms(&i915->drm, "TC cold block %s\n", + (ret == 0 ? "succeeded" : "failed")); +} diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h index a1afcee48818..168d8896fcfd 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.h +++ b/drivers/gpu/drm/i915/display/intel_tc.h @@ -9,6 +9,7 @@ #include #include +struct drm_i915_private; struct intel_digital_port; bool intel_tc_port_connected(struct intel_digital_port *dig_port); @@ -29,5 +30,6 @@ bool intel_tc_port_ref_held(struct intel_digital_port *dig_port); void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy); u32 intel_tc_port_live_status_mask(struct intel_digital_port *dig_port); +void intel_tc_icl_tc_cold_exit(struct drm_i915_private *i915); #endif /* __INTEL_TC_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 17484345cb80..b111815d6596 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9107,6 +9107,7 @@ enum { #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) #define GEN6_PCODE_READ_D_COMP 0x10 #define GEN6_PCODE_WRITE_D_COMP 0x11 +#define ICL_PCODE_EXIT_TCCOLD 0x12 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 #define DISPLAY_IPS_CONTROL 0x19 /* See also IPS_CTL */ From patchwork Wed Apr 1 00:41:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11468533 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 92B0F14B4 for ; Wed, 1 Apr 2020 00:40:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 791B120787 for ; Wed, 1 Apr 2020 00:40:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 791B120787 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7624C6E8AF; Wed, 1 Apr 2020 00:39:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2B7E96E8AF for ; Wed, 1 Apr 2020 00:39:56 +0000 (UTC) IronPort-SDR: zGjaasKtX1siEt80hnD0FT0dD0DW9ZVyJoqp45nLOY9i0uMiRfVLCh6hCUZ9UC8wG/wI5Ga7wO Lhp7zjcwzZlg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2020 17:39:55 -0700 IronPort-SDR: nWJc9LDba5/Tn+l8k9egHeq7UewDiLA0oDH5ICMOvok3/bcXJLTboIj+MLIG8MpK7y3VDXZXk2 vw/dbuzeKsmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,329,1580803200"; d="scan'208";a="295169816" Received: from akahan1-mobl3.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.252.143.47]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2020 17:39:54 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2020 17:41:20 -0700 Message-Id: <20200401004120.408586-6-jose.souza@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200401004120.408586-1-jose.souza@intel.com> References: <20200401004120.408586-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/tc/tgl: Implement TC cold sequences X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cooper Chiou , Kai-Heng Feng Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" TC ports can enter in TCCOLD to save power and is required to request to PCODE to exit this state before use or read to TC registers. For TGL there is a new MBOX command to do that with a parameter to ask PCODE to exit and block TCCOLD entry or unblock TCCOLD entry. So adding a new power domain to reuse the refcount and only allow TC cold when all TC ports are not in use. BSpec: 49294 Cc: Imre Deak Cc: Cooper Chiou Cc: Kai-Heng Feng Signed-off-by: José Roberto de Souza --- .../drm/i915/display/intel_display_power.c | 46 ++++++++++++++ .../drm/i915/display/intel_display_power.h | 1 + drivers/gpu/drm/i915/display/intel_tc.c | 63 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_tc.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 + 5 files changed, 103 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 1ccd57d645c7..5de115583146 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -2842,6 +2842,8 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, #define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \ BIT_ULL(POWER_DOMAIN_AUX_I_TBT)) +#define TGL_TC_COLD_OFF (BIT_ULL(POWER_DOMAIN_TC_COLD_OFF)) + static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = i9xx_always_on_power_well_noop, @@ -3944,6 +3946,44 @@ static const struct i915_power_well_desc ehl_power_wells[] = { }, }; +static void +tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915, + struct i915_power_well *power_well) +{ + intel_tc_tgl_tc_cold_request(i915, true); +} + +static void +tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915, + struct i915_power_well *power_well) +{ + intel_tc_tgl_tc_cold_request(i915, false); +} + +static void +tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915, + struct i915_power_well *power_well) +{ + if (power_well->count > 0) + tgl_tc_cold_off_power_well_enable(i915, power_well); + else + tgl_tc_cold_off_power_well_disable(i915, power_well); +} + +static bool tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + /* There is no way to just read it from PCODE */ + return false; +} + +static const struct i915_power_well_ops tgl_tc_cold_off_ops = { + .sync_hw = tgl_tc_cold_off_power_well_sync_hw, + .enable = tgl_tc_cold_off_power_well_enable, + .disable = tgl_tc_cold_off_power_well_disable, + .is_enabled = tgl_tc_cold_off_power_well_is_enabled, +}; + static const struct i915_power_well_desc tgl_power_wells[] = { { .name = "always-on", @@ -4271,6 +4311,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = { .hsw.irq_pipe_mask = BIT(PIPE_D), }, }, + { + .name = "TC cold off", + .domains = POWER_DOMAIN_TC_COLD_OFF, + .ops = &tgl_tc_cold_off_ops, + .id = DISP_PW_ID_NONE, + }, }; static int diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index da64a5edae7a..070457e7b948 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -76,6 +76,7 @@ enum intel_display_power_domain { POWER_DOMAIN_MODESET, POWER_DOMAIN_GT_IRQ, POWER_DOMAIN_DPLL_DC_OFF, + POWER_DOMAIN_TC_COLD_OFF, POWER_DOMAIN_INIT, POWER_DOMAIN_NUM, diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index b6d67f069ef7..58f19037411a 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -507,11 +507,16 @@ static void __intel_tc_port_lock(struct intel_digital_port *dig_port, mutex_lock(&dig_port->tc_lock); - if (INTEL_GEN(i915) == 11 && dig_port->tc_link_refcount == 0) { - enum intel_display_power_domain aux_domain; + if (dig_port->tc_link_refcount == 0) { + enum intel_display_power_domain domain; - aux_domain = intel_aux_ch_to_power_domain(dig_port->aux_ch); - dig_port->tc_cold_wakeref = intel_display_power_get(i915, aux_domain); + if (INTEL_GEN(i915) == 11) + domain = intel_aux_ch_to_power_domain(dig_port->aux_ch); + else + domain = POWER_DOMAIN_TC_COLD_OFF; + + dig_port->tc_cold_wakeref = intel_display_power_get(i915, + domain); } if (!dig_port->tc_link_refcount && @@ -527,18 +532,23 @@ void intel_tc_port_lock(struct intel_digital_port *dig_port) __intel_tc_port_lock(dig_port, 1); } -static void icl_tc_cold_unblock(struct intel_digital_port *dig_port) +static void tc_cold_unblock(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - enum intel_display_power_domain aux_domain; + enum intel_display_power_domain domain; intel_wakeref_t tc_cold_wakeref; - if (INTEL_GEN(i915) != 11 || dig_port->tc_link_refcount > 0) + if (dig_port->tc_link_refcount > 0) return; tc_cold_wakeref = fetch_and_zero(&dig_port->tc_cold_wakeref); - aux_domain = intel_aux_ch_to_power_domain(dig_port->aux_ch); - intel_display_power_put_async(i915, aux_domain, tc_cold_wakeref); + + if (INTEL_GEN(i915) == 11) + domain = intel_aux_ch_to_power_domain(dig_port->aux_ch); + else + domain = POWER_DOMAIN_TC_COLD_OFF; + + intel_display_power_put_async(i915, domain, tc_cold_wakeref); } void intel_tc_port_unlock(struct intel_digital_port *dig_port) @@ -546,7 +556,7 @@ void intel_tc_port_unlock(struct intel_digital_port *dig_port) struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref); - icl_tc_cold_unblock(dig_port); + tc_cold_unblock(dig_port); mutex_unlock(&dig_port->tc_lock); @@ -571,7 +581,7 @@ void intel_tc_port_put_link(struct intel_digital_port *dig_port) { mutex_lock(&dig_port->tc_lock); dig_port->tc_link_refcount--; - icl_tc_cold_unblock(dig_port); + tc_cold_unblock(dig_port); mutex_unlock(&dig_port->tc_lock); } @@ -611,3 +621,34 @@ void intel_tc_icl_tc_cold_exit(struct drm_i915_private *i915) drm_dbg_kms(&i915->drm, "TC cold block %s\n", (ret == 0 ? "succeeded" : "failed")); } + +void +intel_tc_tgl_tc_cold_request(struct drm_i915_private *i915, bool block) +{ + u32 low_val, high_val; + u8 tries = 0; + int ret; + + do { + low_val = 0; + high_val = block ? 0 : TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ; + + ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, + &high_val); + if (ret == 0) { + if (block && + (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) + ret = -EIO; + else + break; + } + + if (ret != -EAGAIN) + tries++; + } while (tries < 3); + + if (ret) + drm_dbg_kms(&i915->drm, "TC cold %sblock %s\n", + (block ? "" : "un"), + (ret == 0 ? "succeeded" : "failed")); +} diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h index 168d8896fcfd..8bb358cc8f15 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.h +++ b/drivers/gpu/drm/i915/display/intel_tc.h @@ -31,5 +31,6 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy); u32 intel_tc_port_live_status_mask(struct intel_digital_port *dig_port); void intel_tc_icl_tc_cold_exit(struct drm_i915_private *i915); +void intel_tc_tgl_tc_cold_request(struct drm_i915_private *i915, bool block); #endif /* __INTEL_TC_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b111815d6596..5548f3b56c0b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9110,6 +9110,9 @@ enum { #define ICL_PCODE_EXIT_TCCOLD 0x12 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 #define DISPLAY_IPS_CONTROL 0x19 +#define TGL_PCODE_TCCOLD 0x26 +#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) +#define TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ REG_BIT(0) /* See also IPS_CTL */ #define IPS_PCODE_CONTROL (1 << 30) #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A