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Wed, 3 Oct 2018 09:40:57 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/exynos: decon: Make plane alpha configurable Date: Wed, 3 Oct 2018 11:40:43 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538559644-30269-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm27m6Whyn4NeFVdOuYMsu+EFXoeJkP7LoRpZ5qoNmzmRTKyHS IvGSc2mi2Zi67nNpzqVzWeIyh4QbaUUpZtF+mJe0pkaRltvp8u95n8v3vLx8NCZ1EXPoE0kp vCqJS5STYry+7bsztEpjiV5pfkqi7mongfKd7SJUW1pDIMejWwC9HB8hUeN7G4UK+7Q46n/3 AkcFHwcx5HI9oFDHhSEKmT++JlCXTUeiUtcTESqwthDofmsvhSq/PMRRb1ErQKVFn8jNAaxJ bwKs2ZhDsg0T7wlW376L7ctziNi6m+fZxsLHItZh66ZYjcUIWI9ZFiU+KF5/nE88kcarFBtj xfHXrZlEcrbsTHuRlsoAxtm5gKYhswbevLotF4hpKXMXwLaBfFIYxgBsassjhMED4I+ePCwX +PkSuuIuIAh3ABztdhP/Is5nWsrrIpm1sKf3K+nFgUwwnLxi9CUwpouALkMl7hUCmK0wo20K 9y6CM4tgg3mJ0CCDb505vjY/Zjs02W2+AsgMU9B9LdsnSJg0WKYZJYXAFqgZNYoEHAAHHBZK wPPgr8ZykRC+CGD32Os/L2kBbKnKxQXXOmh+MyDyboExy2CNTSHQEdBtqAfClWbBN8P+Xhqb hoX1JZhAS2B2llRwL4aDFgv5t7bfMw4EzMKSn3pMOJAOwKK+alIL5pf9L6sAwAiC+FS1Mo5X hyXxp1eoOaU6NSluxbFTSjOY/mbPpxxfrWC886gdMDSQz5RYK+uipQSXpj6rtANIY/JAiYab piTHubPpvOrUEVVqIq+2g7k0Lg+S3NbXRkuZOC6FP8nzybzqryqi/eZkAI6ef+CbrCOmVZse bq26vCFjsmNT7SHGvF88GZr5Oa6HL3duPNfcHLrPHVabXLDn4YzAkCfjI0cid8TGxC+8sca0 uvPDpb2HpUvvVRhm7Ov3k3kiF0wkfDME++sUQ+nrm1Y2NCt2Pn1lUqpKf1KKuojirN3pCbtj lOF4i+5VUFTIKjmujufClmMqNfcbM+QuxWIDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRmVeSWpSXmKPExsVy+t/xu7qr+rZEG9y8ymVxa905VovecyeZ LDbOWM9qcXz3UkaLK1/fs1nsfLCL3WLS/QksFi/uXWSx6H/8mtni/PkN7BZnm96wW2x6fI3V 4vKuOWwWM87vY7Lo33GQ1WLtkbvsFgs/bmWxuDv5CKPFjMkv2RyEPdbMW8PosWlVJ5vH9m8P WD3mnQz0uN99nMlj85J6j52T9jJ5HN91i92jb8sqRo/Pm+QCuKL0bIryS0tSFTLyi0tslaIN LYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLLUov07RL0MmbvaGQt6JCrODl5AnsD4yrJLkZO DgkBE4k5Uy8zdjFycQgJLGWUmD77OzNEQkZi3tk+NghbWOLPtS42iKJPjBJnTuwGK2ITMJW4 ffcTWJGIgLLE34mrwCYxCzxklXi/sBMsISzgKtFw7B9LFyMHB4uAqsT2TeogYV4BD4mN206x QCyQk7h5rhNsJqeAp8SaQ7tYQWwhoJqvvzYwTmDkW8DIsIpRJLW0ODc9t9hIrzgxt7g0L10v OT93EyMwtrYd+7llB2PXu+BDjAIcjEo8vAnzN0cLsSaWFVfmHmKU4GBWEuHtSwQK8aYkVlal FuXHF5XmpBYfYjQFumkis5Rocj4w7vNK4g1NDc0tLA3Njc2NzSyUxHnPG1RGCQmkJ5akZqem FqQWwfQxcXBKNTBy/DMJydt+/iSnA6v1PYl9V9qni9/Q2OGWpZzucCPeZpXovJpH1+8sk5N4 a/c85e8q0V/fnlXL/HPs0UuSkVQIWWLtIln6+saCHTLmPrumndli/+ZE3LWqD5HXXyy8+n5P +ulcyZYJLpwS66X3Wt7fGS7DnuQkttT2mNw3IYPz96Rs9uncKrVXYinOSDTUYi4qTgQAbjYu cMMCAAA= Message-Id: <20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa~aD9ubxJ5A1867918679eucas1p1K@eucas1p1.samsung.com> X-CMS-MailID: 20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa X-Msg-Generator: CA X-RootMTR: 20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa References: <1538559644-30269-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Thu, 04 Oct 2018 07:14:20 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , Lowry Li , Sean Paul , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The decon hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TM2 with Exynos 5433 CPU, on top of exynos-drm-next. Signed-off-by: Christoph Manszewski --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 30 +++++++++++++++++++++++++++ drivers/gpu/drm/exynos/regs-decon5433.h | 4 ++++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 94529aa82339..dff540160199 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -84,6 +84,14 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, }; +static const unsigned int capabilities[WINDOWS_NR] = { + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, +}; + static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, u32 val) { @@ -259,6 +267,24 @@ static void decon_commit(struct exynos_drm_crtc *crtc) decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } +static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, + struct drm_framebuffer *fb) +{ + struct exynos_drm_plane plane = ctx->planes[win]; + struct exynos_drm_plane_state *state = + to_exynos_plane_state(plane.base.state); + unsigned int alpha = state->base.alpha; + u32 win_alpha = alpha >> 8; + u32 val = 0; + + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | VIDOSD_Wx_ALPHA_G_F(win_alpha) | + VIDOSD_Wx_ALPHA_B_F(win_alpha); + decon_set_bits(ctx, DECON_VIDOSDxC(win), 0xffffff, val); + decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW); + } +} + static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, struct drm_framebuffer *fb) { @@ -267,6 +293,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val = readl(ctx->addr + DECON_WINCONx(win)); val &= WINCONx_ENWIN_F; + decon_win_set_bldmod(ctx, win, fb); + switch (fb->format->format) { case DRM_FORMAT_XRGB1555: val |= WINCONx_BPPMODE_16BPP_I1555; @@ -288,6 +316,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val |= WINCONx_BPPMODE_32BPP_A8888; val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; val |= WINCONx_BURSTLEN_16WORD; + val |= WINCONx_ALPHA_MUL_F; break; } @@ -561,6 +590,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); ctx->configs[win].zpos = win - ctx->first_win; ctx->configs[win].type = decon_win_types[win]; + ctx->configs[win].capabilities = capabilities[win]; ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, &ctx->configs[win]); diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h index 19ad9e47945e..f42d8f0adf5d 100644 --- a/drivers/gpu/drm/exynos/regs-decon5433.h +++ b/drivers/gpu/drm/exynos/regs-decon5433.h @@ -104,6 +104,7 @@ #define WINCONx_BURSTLEN_16WORD (0x0 << 10) #define WINCONx_BURSTLEN_8WORD (0x1 << 10) #define WINCONx_BURSTLEN_4WORD (0x2 << 10) +#define WINCONx_ALPHA_MUL_F (1 << 7) #define WINCONx_BLD_PIX_F (1 << 6) #define WINCONx_BPPMODE_MASK (0xf << 2) #define WINCONx_BPPMODE_16BPP_565 (0x5 << 2) @@ -206,4 +207,7 @@ #define CRCCTRL_CRCEN (0x1 << 0) #define CRCCTRL_MASK (0x7) +/* BLENDCON */ +#define BLEND_NEW (1 << 0) + #endif /* EXYNOS_REGS_DECON5433_H */ From patchwork Wed Oct 3 09:40:44 2018 Content-Type: text/plain; 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Wed, 3 Oct 2018 09:40:59 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/exynos: decon: Make pixel blend mode configurable Date: Wed, 3 Oct 2018 11:40:44 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538559644-30269-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTURzv7N67XZeL2zQ8qBgtDHtphdKBJAqCbkaQfgk1qJk3tXTKrq4s MNHwnS4FExVt4qulqXOaTrQc5lJxl9LERz7KIB8TKx+klrR5lb79zu/1/5/DITGpmXAmIxSx jFIhj5QJxXhz9xp3vDZbH3xiPXk3Gn1lJtATc48ANRTUEcjUVgHQ4MqiELVOGUQod1KNo5mJ DzjKmZ7HEMfVi1B/kkWEdNNDBBowFAtRAdchQDktnQSq7RoXIc3PJhyN53UBVJA3KzznQNeU 1ABap00X0q9Xpwi6pMefnsw0CejG8kd0a267gDYZRkV0tl4L6CWd21VxkNg3lImMUDFKr7M3 xeETvd+ImEyX+0ZOjyeCLKcMYEdCyhuq1+qJDCAmpVQ1gJaNeZFNkFLLAKbV4bywBGCZec4q kFuJdU7C81UAtuRrMP5gDWxwKZgtLaR84Nj4L6ENO1IH4d+nWmAzYdQAAbkyDW5rcqD84Ke0 BJsHp9xhdWmhiF/JDY6Y07d67KhLsMZo2FoPUgsi2DsyuGWSUCq4YUrH+cAFWJv6W8BjBzhn 0m8XucK+vCycDycDOLo8tN2kBrDzZcZ2+gzUDc8JbBth1GFYZ/Di6fNwsdKC81feA4cX9tpo zApzm59hPC2BaSlS3n0Izuv1wp2xM0srgMc0fDyQAfgHKgaw1diGq8H+wv/DngOgBU5MHBsV xrCnFMw9T1YexcYpwjxvRUfpgPWX9W2alluA4U+IEVAkkNlLWjSNwVJCrmLjo4wAkpjMUZIt t1KSUHn8A0YZfUMZF8mwRuBC4jInSWVJQ7CUCpPHMncZJoZR7qgC0s45ERzIDYLERybJGWrN fjllDstD8wkBk0WWgCq/qsnuadOcd2NBfgA7MSv7UXrUvvpKeojljjs35dVQ5Pq5YyDh8lh5 VvE+oJYEXvSXYf3vvuoDH/qqmq/Frh0b2fU99bT/l/c+qqYXet/VN7dLNB6Kzp5gtPnWrrKi fdTVo6bi+rAMZ8PlJ49gSlb+D0Dz6/VhAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsVy+t/xu7pr+rZEG8yYxWpxa905VovecyeZ LDbOWM9qcXz3UkaLK1/fs1nsfLCL3WLS/QksFi/uXWSx6H/8mtni/PkN7BZnm96wW2x6fI3V 4vKuOWwWM87vY7Lo33GQ1WLtkbvsFgs/bmWxuDv5CKPFjMkv2RyEPdbMW8PosWlVJ5vH9m8P WD3mnQz0uN99nMlj85J6j52T9jJ5HN91i92jb8sqRo/Pm+QCuKL0bIryS0tSFTLyi0tslaIN LYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLLUov07RL0Mu6desJa0C1dcej8FpYGxh7xLkYO DgkBE4lf53m7GDk5hASWMkp8/FYOYksIyEjMO9vHBmELS/y51gVkcwHVfGKU6Nt7mAUkwSZg KnH77iewIhEBZYm/E1cxghQxCzxklXi/sJMNZIGwgJfE1Y46kBoWAVWJFfNnsYPYvAIeEnOf 7WaBWCAncfNcJzOIzSngKbHm0C5WiIM8JL7+2sA4gZFvASPDKkaR1NLi3PTcYkO94sTc4tK8 dL3k/NxNjMC42nbs5+YdjJc2Bh9iFOBgVOLh3bFwc7QQa2JZcWXuIUYJDmYlEd6+RKAQb0pi ZVVqUX58UWlOavEhRlOgoyYyS4km5wNjPq8k3tDU0NzC0tDc2NzYzEJJnPe8QWWUkEB6Yklq dmpqQWoRTB8TB6dUA2P2Re1tM5ZLMiUdX2+7zct9Tlmz1jttG7kHIYJbelR3va4WtS+VTlru cn/fYT5d9oN2HJP2L7losmBSQO/MzHeiXAa3DjQsXNhglclpqyJn1PzzfmSawaa6C8svMF+U OxvxIabEPeTA42WuLb3ZjC1no6z+s/jLK0buk01mTVqXG7D9eFXQMiWW4oxEQy3mouJEAL9O 6frBAgAA Message-Id: <20181003094100eucas1p23bfb9604dbd50ee77f11a85d2c626471~aD9wOUXM61807118071eucas1p2b@eucas1p2.samsung.com> X-CMS-MailID: 20181003094100eucas1p23bfb9604dbd50ee77f11a85d2c626471 X-Msg-Generator: CA X-RootMTR: 20181003094100eucas1p23bfb9604dbd50ee77f11a85d2c626471 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181003094100eucas1p23bfb9604dbd50ee77f11a85d2c626471 References: <1538559644-30269-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Thu, 04 Oct 2018 07:14:20 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , Lowry Li , Sean Paul , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently blend mode is set accordingly to pixel format. Add pixel blend mode property and make that configurable. Decon hardware doesn't support premultiplied mode, chose coverage as default. Tested on TM2 with Exynos 5433 CPU, on top of exynos-drm-next using modetest. Signed-off-by: Christoph Manszewski --- Currently, the driver exposes the "premultiplied" option for pixel blend mode property, and handles it as "coverage". This is due to the fact, that "premultiplied" mode is mandatory and is used as default. The question is - how to correctly deal with hardare that doesn't support premultiplied mode? drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 29 ++++++++++++++++++++++----- drivers/gpu/drm/exynos/regs-decon5433.h | 1 + 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index dff540160199..15609c9f2fda 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -84,12 +84,13 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, }; + static const unsigned int capabilities[WINDOWS_NR] = { EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, }; static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, @@ -276,6 +277,24 @@ static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, unsigned int alpha = state->base.alpha; u32 win_alpha = alpha >> 8; u32 val = 0; + unsigned int pixel_alpha; + + if (fb->format->has_alpha) + pixel_alpha = state->base.pixel_blend_mode; + else + pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; + + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + break; + case DRM_MODE_BLEND_COVERAGE: + default: + val |= WINCONx_ALPHA_SEL_F; + val |= WINCONx_BLD_PIX_F; + val |= WINCONx_ALPHA_MUL_F; + break; + } + decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val); if (alpha != DRM_BLEND_ALPHA_OPAQUE) { val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | VIDOSD_Wx_ALPHA_G_F(win_alpha) | @@ -335,7 +354,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val |= WINCONx_BURSTLEN_8WORD; } - writel(val, ctx->addr + DECON_WINCONx(win)); + decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val); } static void decon_shadow_protect(struct decon_context *ctx, bool protect) diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h index f42d8f0adf5d..17b7324922c1 100644 --- a/drivers/gpu/drm/exynos/regs-decon5433.h +++ b/drivers/gpu/drm/exynos/regs-decon5433.h @@ -117,6 +117,7 @@ #define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2) #define WINCONx_ALPHA_SEL_F (1 << 1) #define WINCONx_ENWIN_F (1 << 0) +#define WINCONx_BLEND_MODE_MASK (0xc2) /* SHADOWCON */ #define SHADOWCON_PROTECT_MASK GENMASK(14, 10)