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[79.52.251.133]) by smtp.googlemail.com with ESMTPSA id j10sm1335981ejv.13.2020.04.02.17.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 17:26:18 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] phy: qualcomm: add qcom dwc3 phy Date: Fri, 3 Apr 2020 02:26:04 +0200 Message-Id: <20200403002608.946-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This has lost in the original push for the dwc3 qcom driver. This is needed for ipq806x SoC as without this the usb ports doesn't work at all. Signed-off-by: Andy Gross Signed-off-by: Ansuel Smith --- drivers/phy/qualcomm/Kconfig | 12 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-dwc3.c | 578 +++++++++++++++++++++++++++ 3 files changed, 591 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-dwc3.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index e46824da29f6..3d45a9156f85 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -91,3 +91,15 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_DWC3 + tristate "QCOM DWC3 USB PHY support" + depends on ARCH_QCOM + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY + help + This option enables support for the Synopsis PHYs present inside the + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS + PHY controllers. + diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 283251d6a5d9..04c5a8da941a 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o diff --git a/drivers/phy/qualcomm/phy-qcom-dwc3.c b/drivers/phy/qualcomm/phy-qcom-dwc3.c new file mode 100644 index 000000000000..f33da199ddde --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* USB QSCRATCH Hardware registers */ +#define QSCRATCH_GENERAL_CFG (0x08) +#define HSUSB_PHY_CTRL_REG (0x10) + +/* PHY_CTRL_REG */ +#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24) +#define HSUSB_CTRL_USB2_SUSPEND BIT(23) +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) +#define HSUSB_CTRL_USE_CLKCORE BIT(18) +#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17) +#define HSUSB_CTRL_COMMONONN BIT(11) +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) +#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8) +#define HSUSB_CTRL_CLAMP_EN BIT(7) +#define HSUSB_CTRL_RETENABLEN BIT(1) +#define HSUSB_CTRL_POR BIT(0) + +/* QSCRATCH_GENERAL_CFG */ +#define HSUSB_GCFG_XHCI_REV BIT(2) + +/* USB QSCRATCH Hardware registers */ +#define SSUSB_PHY_CTRL_REG (0x30) +#define SSUSB_PHY_PARAM_CTRL_1 (0x34) +#define SSUSB_PHY_PARAM_CTRL_2 (0x38) +#define CR_PROTOCOL_DATA_IN_REG (0x3c) +#define CR_PROTOCOL_DATA_OUT_REG (0x40) +#define CR_PROTOCOL_CAP_ADDR_REG (0x44) +#define CR_PROTOCOL_CAP_DATA_REG (0x48) +#define CR_PROTOCOL_READ_REG (0x4c) +#define CR_PROTOCOL_WRITE_REG (0x50) + +/* PHY_CTRL_REG */ +#define SSUSB_CTRL_REF_USE_PAD BIT(28) +#define SSUSB_CTRL_TEST_POWERDOWN BIT(27) +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) +#define SSUSB_CTRL_SS_PHY_EN BIT(8) +#define SSUSB_CTRL_SS_PHY_RESET BIT(7) + +/* SSPHY control registers - Does this need 0x30? */ +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane) +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane) + +/* SSPHY SoC version specific values */ +#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */ +/* Override value for transmit preemphasis */ +#define SSPHY_TX_DEEMPH_3_5DB 23 +#define SSPHY_MPLL_VALUE 0 /* Override value for mpll */ + +/* QSCRATCH PHY_PARAM_CTRL1 fields */ +#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK 0x07f00000u +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK 0x000fc000u +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK 0x00003f00u +#define PHY_PARAM_CTRL1_LOS_BIAS_MASK 0x000000f8u + +#define PHY_PARAM_CTRL1_MASK \ + (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \ + PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \ + PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \ + PHY_PARAM_CTRL1_LOS_BIAS_MASK) + +#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \ + (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK) +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \ + (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK) +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \ + (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK) +#define PHY_PARAM_CTRL1_LOS_BIAS(x) \ + (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK) + +/* RX OVRD IN HI bits */ +#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13) +#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12) +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7) +#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6) +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5) +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018 +#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2) +#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003 + +/* TX OVRD DRV LO register bits */ +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F +#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80 +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7 +#define TX_OVRD_DRV_LO_EN BIT(14) + +/* SS CAP register bits */ +#define SS_CR_CAP_ADDR_REG BIT(0) +#define SS_CR_CAP_DATA_REG BIT(0) +#define SS_CR_READ_REG BIT(0) +#define SS_CR_WRITE_REG BIT(0) + +struct qcom_dwc3_usb_phy { + struct regmap *base; + struct device *dev; + struct clk *xo_clk; + struct clk *ref_clk; + u32 rx_eq; + u32 tx_deamp_3_5db; + u32 mpll; +}; + +struct qcom_dwc3_phy_drvdata { + struct phy_ops ops; + u32 clk_rate; +}; + +/** + * Write register and read back masked value to confirm it is written + * + * @base - QCOM DWC3 PHY base virtual address. + * @offset - register offset. + * @mask - register bitmask specifying what should be updated + * @val - value to write. + */ +static inline void qcom_dwc3_phy_write_readback( + struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset, + const u32 mask, u32 val) +{ + u32 write_val, tmp; + + tmp = regmap_read(phy_dwc3->base, offset, &tmp); + tmp &= ~mask; /* retain other bits */ + write_val = tmp | val; + + regmap_write(phy_dwc3->base, offset, write_val); + + /* Read back to see if val was written */ + regmap_read(phy_dwc3->base, offset, &tmp); + tmp &= mask; /* clear other bits */ + + if (tmp != val) + dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", + val, offset); +} + +static int wait_for_latch(struct regmap *base, u32 addr) +{ + u32 retry = 10, data; + + while (true) { + regmap_read(base, addr, &data); + if (!data) + break; + + if (--retry == 0) + return -ETIMEDOUT; + + usleep_range(10, 20); + } + + return 0; +} + +/** + * Write SSPHY register + * + * @base - QCOM DWC3 PHY base virtual address. + * @addr - SSPHY address to write. + * @val - value to write. + */ +static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3, + u32 addr, u32 val) +{ + int ret; + + regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, addr); + regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG, + SS_CR_CAP_ADDR_REG); + + ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG); + if (ret) + goto err_wait; + + regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, val); + regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG, + SS_CR_CAP_DATA_REG); + + ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG); + if (ret) + goto err_wait; + + regmap_write(phy_dwc3->base, CR_PROTOCOL_WRITE_REG, SS_CR_WRITE_REG); + + ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_WRITE_REG); + +err_wait: + if (ret) + dev_err(phy_dwc3->dev, "timeout waiting for latch\n"); + return ret; +} + +/** + * Read SSPHY register. + * + * @base - QCOM DWC3 PHY base virtual address. + * @addr - SSPHY address to read. + */ +static int qcom_dwc3_ss_read_phycreg(struct regmap *base, u32 addr, u32 *val) +{ + int ret; + + regmap_write(base, CR_PROTOCOL_DATA_IN_REG, addr); + regmap_write(base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG); + + ret = wait_for_latch(base, CR_PROTOCOL_CAP_ADDR_REG); + if (ret) + goto err_wait; + + /* + * Due to hardware bug, first read of SSPHY register might be + * incorrect. Hence as workaround, SW should perform SSPHY register + * read twice, but use only second read and ignore first read. + */ + regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG); + + ret = wait_for_latch(base, CR_PROTOCOL_READ_REG); + if (ret) + goto err_wait; + + /* throwaway read */ + regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, &ret); + + regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG); + + ret = wait_for_latch(base, CR_PROTOCOL_READ_REG); + if (ret) + goto err_wait; + + regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, val); + +err_wait: + return ret; +} + +static int qcom_dwc3_hs_phy_init(struct phy *phy) +{ + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); + int ret; + u32 val; + + ret = clk_prepare_enable(phy_dwc3->xo_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(phy_dwc3->ref_clk); + if (ret) { + clk_disable_unprepare(phy_dwc3->xo_clk); + return ret; + } + + /* + * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel + * enable clamping, and disable RETENTION (power-on default is ENABLED) + */ + val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP | + HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN | + HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP | + HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID | + HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70; + + /* use core clock if external reference is not present */ + if (!phy_dwc3->xo_clk) + val |= HSUSB_CTRL_USE_CLKCORE; + + regmap_write(phy_dwc3->base, HSUSB_PHY_CTRL_REG, val); + usleep_range(2000, 2200); + + /* Disable (bypass) VBUS and ID filters */ + regmap_write(phy_dwc3->base, QSCRATCH_GENERAL_CFG, HSUSB_GCFG_XHCI_REV); + + return 0; +} + +static int qcom_dwc3_hs_phy_exit(struct phy *phy) +{ + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); + + clk_disable_unprepare(phy_dwc3->ref_clk); + clk_disable_unprepare(phy_dwc3->xo_clk); + + return 0; +} + +static int qcom_dwc3_ss_phy_init(struct phy *phy) +{ + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); + int ret; + u32 data = 0; + + ret = clk_prepare_enable(phy_dwc3->xo_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(phy_dwc3->ref_clk); + if (ret) { + clk_disable_unprepare(phy_dwc3->xo_clk); + return ret; + } + + /* reset phy */ + regmap_read(phy_dwc3->base, SSUSB_PHY_CTRL_REG, &data); + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, + data | SSUSB_CTRL_SS_PHY_RESET); + usleep_range(2000, 2200); + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data); + + /* clear REF_PAD if we don't have XO clk */ + if (!phy_dwc3->xo_clk) + data &= ~SSUSB_CTRL_REF_USE_PAD; + else + data |= SSUSB_CTRL_REF_USE_PAD; + + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data); + + /* wait for ref clk to become stable, this can take up to 30ms */ + msleep(30); + + data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT; + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data); + + /* + * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates + * in HS mode instead of SS mode. Workaround it by asserting + * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode + */ + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data); + if (ret) + goto err_phy_trans; + + data |= (1 << 7); + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data); + if (ret) + goto err_phy_trans; + + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data); + if (ret) + goto err_phy_trans; + + data &= ~0xff0; + data |= 0x20; + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data); + if (ret) + goto err_phy_trans; + + /* + * Fix RX Equalization setting as follows + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 + * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 + */ + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, + SSPHY_CTRL_RX_OVRD_IN_HI(0), &data); + if (ret) + goto err_phy_trans; + + data &= ~RX_OVRD_IN_HI_RX_EQ_EN; + data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD; + data &= ~RX_OVRD_IN_HI_RX_EQ_MASK; + data |= phy_dwc3->rx_eq << RX_OVRD_IN_HI_RX_EQ_SHIFT; + data |= RX_OVRD_IN_HI_RX_EQ_OVRD; + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, + SSPHY_CTRL_RX_OVRD_IN_HI(0), data); + if (ret) + goto err_phy_trans; + + /* + * Set EQ and TX launch amplitudes as follows + * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 + * LANE0.TX_OVRD_DRV_LO.EN set to 1. + */ + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, + SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data); + if (ret) + goto err_phy_trans; + + data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK; + data |= phy_dwc3->tx_deamp_3_5db << TX_OVRD_DRV_LO_PREEMPH_SHIFT; + data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK; + data |= 0x6E; + data |= TX_OVRD_DRV_LO_EN; + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, + SSPHY_CTRL_TX_OVRD_DRV_LO(0), data); + if (ret) + goto err_phy_trans; + + qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x30, phy_dwc3->mpll); + + /* + * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows + * TX_FULL_SWING [26:20] amplitude to 110 + * TX_DEEMPH_6DB [19:14] to 32 + * TX_DEEMPH_3_5DB [13:8] set based on SoC version + * LOS_BIAS [7:3] to 9 + */ + regmap_read(phy_dwc3->base, SSUSB_PHY_PARAM_CTRL_1, &data); + + data &= ~PHY_PARAM_CTRL1_MASK; + + data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) | + PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) | + PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) | + PHY_PARAM_CTRL1_LOS_BIAS(0x9); + + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1, + PHY_PARAM_CTRL1_MASK, data); + +err_phy_trans: + return ret; +} + +static int qcom_dwc3_ss_phy_exit(struct phy *phy) +{ + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); + + /* Sequence to put SSPHY in low power state: + * 1. Clear REF_PHY_EN in PHY_CTRL_REG + * 2. Clear REF_USE_PAD in PHY_CTRL_REG + * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention + */ + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, + SSUSB_CTRL_SS_PHY_EN, 0x0); + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, + SSUSB_CTRL_REF_USE_PAD, 0x0); + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, + SSUSB_CTRL_TEST_POWERDOWN, 0x0); + + clk_disable_unprepare(phy_dwc3->ref_clk); + clk_disable_unprepare(phy_dwc3->xo_clk); + + return 0; +} + +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = { + .ops = { + .init = qcom_dwc3_hs_phy_init, + .exit = qcom_dwc3_hs_phy_exit, + .owner = THIS_MODULE, + }, + .clk_rate = 60000000, +}; + +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = { + .ops = { + .init = qcom_dwc3_ss_phy_init, + .exit = qcom_dwc3_ss_phy_exit, + .owner = THIS_MODULE, + }, + .clk_rate = 125000000, +}; + +static const struct of_device_id qcom_dwc3_phy_table[] = { + { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata }, + { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table); + +static int qcom_dwc3_phy_probe(struct platform_device *pdev) +{ + struct qcom_dwc3_usb_phy *phy_dwc3; + struct phy_provider *phy_provider; + struct phy *generic_phy; + struct resource *res; + const struct of_device_id *match; + const struct qcom_dwc3_phy_drvdata *data; + struct device_node *np; + + phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL); + if (!phy_dwc3) + return -ENOMEM; + + match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node); + data = match->data; + + phy_dwc3->dev = &pdev->dev; + + phy_dwc3->base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "regmap"); + if (IS_ERR_OR_NULL(phy_dwc3->base)) + return PTR_ERR_OR_ZERO(phy_dwc3->base) ? : -EINVAL; + + phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref"); + if (IS_ERR(phy_dwc3->ref_clk)) { + dev_dbg(phy_dwc3->dev, "cannot get reference clock\n"); + return PTR_ERR(phy_dwc3->ref_clk); + } + + clk_set_rate(phy_dwc3->ref_clk, data->clk_rate); + + phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo"); + if (IS_ERR(phy_dwc3->xo_clk)) { + dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n"); + phy_dwc3->xo_clk = NULL; + } + + /* Parse device node to probe HSIO settings */ + np = of_node_get(pdev->dev.of_node); + if (!of_compat_cmp(match->compatible, "qcom,dwc3-ss-usb-phy", + strlen(match->compatible))) { + + if (of_property_read_u32(np, "rx_eq", &phy_dwc3->rx_eq) || + of_property_read_u32(np, "tx_deamp_3_5db", + &phy_dwc3->tx_deamp_3_5db) || + of_property_read_u32(np, "mpll", &phy_dwc3->mpll)) { + + dev_err(phy_dwc3->dev, "cannot get HSIO settings from device node, using default values\n"); + + /* Default HSIO settings */ + phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE; + phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB; + phy_dwc3->mpll = SSPHY_MPLL_VALUE; + } + } + + generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, + &data->ops); + + if (IS_ERR(generic_phy)) + return PTR_ERR(generic_phy); + + phy_set_drvdata(generic_phy, phy_dwc3); + platform_set_drvdata(pdev, phy_dwc3); + + phy_provider = devm_of_phy_provider_register(phy_dwc3->dev, + of_phy_simple_xlate); + + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + return 0; +} + +static struct platform_driver qcom_dwc3_phy_driver = { + .probe = qcom_dwc3_phy_probe, + .driver = { + .name = "qcom-dwc3-usb-phy", + .owner = THIS_MODULE, + .of_match_table = qcom_dwc3_phy_table, + }, +}; + +module_platform_driver(qcom_dwc3_phy_driver); + +MODULE_ALIAS("platform:phy-qcom-dwc3"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Andy Gross "); +MODULE_AUTHOR("Ivan T. Ivanov "); +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver"); From patchwork Fri Apr 3 00:26:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11471717 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C9A45912 for ; Fri, 3 Apr 2020 00:26:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D85220787 for ; Fri, 3 Apr 2020 00:26:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WfDLwNIJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390335AbgDCA02 (ORCPT ); Thu, 2 Apr 2020 20:26:28 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:44051 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731842AbgDCA02 (ORCPT ); Thu, 2 Apr 2020 20:26:28 -0400 Received: by mail-ed1-f65.google.com with SMTP id i16so6940516edy.11; Thu, 02 Apr 2020 17:26:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aPFWwf8vkXl+dFMjYxtDZrmI1dHgtdcvjjrsqN4+7bs=; b=WfDLwNIJOwEB3kdveRX4JnqBj/MVNHxKdfVdIlxNCIwkpBudC0cIUIyIy0XzhbPb/Q VaZV6qMGCgORTChI53hpWEYFWla9m57k+GdX9+SnNrAnHZnt3WAdsxK8sIguLvZULzwc 3sfLatjzBFf7DTKXRzaI2A7QiaLAt5ah93XlCvoGHozNt2J+rB8JrXuprHu9m+zLthnp XDC0l+Ec657iuBG2JlYFK5ZJyC/a4I4Lw8TZcBZOpS5nH4CxkZSn3pgGtrSGQXkqo7Np 0GTzl7+7sEiE2HoBxUb+lmaWRWG3Y10+uHdHrKSMSUvQmG2JkhR0tBifKE+qPBbnQTOU ptcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aPFWwf8vkXl+dFMjYxtDZrmI1dHgtdcvjjrsqN4+7bs=; b=gvAfK6U4gdBmuADOjcgsGjuGUUrKXA0EUjMQWuDplcBem5pzP2u3TaAslTklKsn+J1 o79q41FuEHKAhLrGgc6jR/uqQ5icLsIqdwBSYBm9tdjnSXcXYi82GM+fewAreq52k7N1 pEWB67duQXdcwfK21Yd56zneuthscwfhvBjD8xf3HPOLR6mVrSGfV3L7J58XDzb0XAoA sR8GEo3b/Ua/Cua7lHjb4f/hSGafwhR95yeJWfFDJEfoNGgwoNEAs67SMUGLbc68SVRY jsS5bmmTpN9c4t/rGbXG4q73wnVx6L9je/SXOKVM7DMWlTUnHl5iyQHLBOpRFgqE0CnB 3t4g== X-Gm-Message-State: AGi0PubEH46SXTUe7uwX3mCBxRmkc1cfeiZXpFxj6HYefZmfXo8ZQx4v Af1LbF7xzDPk9sfMd5mnGIs= X-Google-Smtp-Source: APiQypIk0yqb/weeyHpGFZmyGyckJM3fIRWZ75YSeoVaCqyuqnXSfWXnBR1isSXxtFR4yIsv1JPNNw== X-Received: by 2002:a05:6402:1ef:: with SMTP id i15mr5782942edy.0.1585873585185; Thu, 02 Apr 2020 17:26:25 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host133-251-dynamic.52-79-r.retail.telecomitalia.it. [79.52.251.133]) by smtp.googlemail.com with ESMTPSA id j10sm1335981ejv.13.2020.04.02.17.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 17:26:24 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] devicetree: bindings: phy: Document dwc3 qcom phy Date: Fri, 3 Apr 2020 02:26:05 +0200 Message-Id: <20200403002608.946-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200403002608.946-1-ansuelsmth@gmail.com> References: <20200403002608.946-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document dwc3 qcom phy hs and ss phy bindings needed to correctly inizialize and use usb on ipq806x SoC Signed-off-by: Ansuel Smith --- .../bindings/phy/qcom,dwc3-hs-usb-phy.yaml | 65 +++++++++++++++++++ .../bindings/phy/qcom,dwc3-ss-usb-phy.yaml | 65 +++++++++++++++++++ 2 files changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml new file mode 100644 index 000000000000..0bb59e3c2ab8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,dwc3-hs-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm DWC3 HS PHY CONTROLLER + +maintainers: + - Ansuel Smith + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers. Each DWC3 PHY controller should have its own node. + +properties: + compatible: + const: qcom,dwc3-hs-usb-phy + + "#phy-cells": + const: 0 + + regmap: + maxItems: 1 + description: phandle to usb3 dts definition + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + description: | + - "ref" Is required + - "xo" Optional external reference clock + items: + - const: ref + - const: xo + +required: + - compatible + - "#phy-cells" + - regmap + - clocks + - clock-names + +examples: + - | + #include + + hs_phy_0: hs_phy_0 { + compatible = "qcom,dwc3-hs-usb-phy"; + regmap = <&usb3_0>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + usb3_0: usb3@110f8800 { + compatible = "qcom,dwc3", "syscon"; + reg = <0x110f8800 0x8000>; + + /* ... */ + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml new file mode 100644 index 000000000000..2f7b0d9db072 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,dwc3-ss-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm DWC3 SS PHY CONTROLLER + +maintainers: + - Ansuel Smith + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers. Each DWC3 PHY controller should have its own node. + +properties: + compatible: + const: qcom,dwc3-ss-usb-phy + + "#phy-cells": + const: 0 + + regmap: + maxItems: 1 + description: phandle to usb3 dts definition + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + description: | + - "ref" Is required + - "xo" Optional external reference clock + items: + - const: ref + - const: xo + +required: + - compatible + - "#phy-cells" + - regmap + - clocks + - clock-names + +examples: + - | + #include + + ss_phy_0: ss_phy_0 { + compatible = "qcom,dwc3-ss-usb-phy"; + regmap = <&usb3_0>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + usb3_0: usb3@110f8800 { + compatible = "qcom,dwc3", "syscon"; + reg = <0x110f8800 0x8000>; + + /* ... */ + };