From patchwork Wed Apr 8 13:46:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 11480143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA5871805 for ; Wed, 8 Apr 2020 13:47:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA99020780 for ; Wed, 8 Apr 2020 13:47:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="X/AnZa1m" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729222AbgDHNrX (ORCPT ); Wed, 8 Apr 2020 09:47:23 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:54943 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729225AbgDHNrW (ORCPT ); Wed, 8 Apr 2020 09:47:22 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1586353641; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=DXWezeadgd/vXlBGVkDB5HbzFgsRvHG2kw4i9AmY/bI=; b=X/AnZa1mlrC6vx3d+ucqPCNFPY/1A3TziP1pPHrjFHrzNe9I6Rt9mDrdTS0EAXQvKPU9aahR U5iDIk9cOr4pG/5Um7/QUiTQWDd3NfHSchZYVUYXtjViYGOzh6EjOvMnI72TDpVEin0Wbe+G cjVNBZIR8Uus9ApDJNl3aHGMwJM= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyIzNzdmZSIsICJsaW51eC1zcGlAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e8dd5e9.7fb08fcc3d18-smtp-out-n01; Wed, 08 Apr 2020 13:47:21 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 95C5AC4478F; Wed, 8 Apr 2020 13:47:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id D5325C433F2; Wed, 8 Apr 2020 13:47:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D5325C433F2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: viresh.kumar@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, agross@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak , Alok Chauhan , Akash Asthana , linux-spi@vger.kernel.org Subject: [PATCH 03/21] spi: spi-geni-qcom: Use OPP API to set clk/perf state Date: Wed, 8 Apr 2020 19:16:29 +0530 Message-Id: <1586353607-32222-4-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586353607-32222-1-git-send-email-rnayak@codeaurora.org> References: <1586353607-32222-1-git-send-email-rnayak@codeaurora.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org geni spi needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak Cc: Alok Chauhan Cc: Akash Asthana Cc: linux-spi@vger.kernel.org --- drivers/spi/spi-geni-qcom.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index c397242..ce387dc 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -95,7 +96,6 @@ static int get_spi_clk_cfg(unsigned int speed_hz, { unsigned long sclk_freq; unsigned int actual_hz; - struct geni_se *se = &mas->se; int ret; ret = geni_se_clk_freq_match(&mas->se, @@ -112,9 +112,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz, dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, actual_hz, sclk_freq, *clk_idx, *clk_div); - ret = clk_set_rate(se->clk, sclk_freq); + ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); if (ret) - dev_err(mas->dev, "clk_set_rate failed %d\n", ret); + dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); return ret; } @@ -553,6 +553,7 @@ static int spi_geni_probe(struct platform_device *pdev) if (!spi) return -ENOMEM; + platform_set_drvdata(pdev, spi); mas = spi_master_get_devdata(spi); mas->irq = irq; @@ -561,6 +562,8 @@ static int spi_geni_probe(struct platform_device *pdev) mas->se.wrapper = dev_get_drvdata(dev->parent); mas->se.base = base; mas->se.clk = clk; + mas->se.opp = dev_pm_opp_set_clkname(&pdev->dev, "se"); + dev_pm_opp_of_add_table(&pdev->dev); spi->bus_num = -1; spi->dev.of_node = dev->of_node; @@ -596,6 +599,7 @@ static int spi_geni_probe(struct platform_device *pdev) spi_geni_probe_runtime_disable: pm_runtime_disable(dev); spi_master_put(spi); + dev_pm_opp_of_remove_table(&pdev->dev); return ret; } @@ -604,6 +608,7 @@ static int spi_geni_remove(struct platform_device *pdev) struct spi_master *spi = platform_get_drvdata(pdev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + dev_pm_opp_of_remove_table(&pdev->dev); /* Unregister _before_ disabling pm_runtime() so we stop transfers */ spi_unregister_master(spi); @@ -617,6 +622,9 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) struct spi_master *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + /* Drop the performance state vote */ + dev_pm_opp_set_rate(dev, 0); + return geni_se_resources_off(&mas->se); } From patchwork Wed Apr 8 13:46:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 11480193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6731912 for ; Wed, 8 Apr 2020 13:48:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 831E62145D for ; Wed, 8 Apr 2020 13:48:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="GESuQDch" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729403AbgDHNsj (ORCPT ); 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Wed, 8 Apr 2020 13:48:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id B0FB0C3856D; Wed, 8 Apr 2020 13:48:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B0FB0C3856D Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: viresh.kumar@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, agross@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak , Alok Chauhan , Akash Asthana , linux-spi@vger.kernel.org Subject: [PATCH 19/21] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Date: Wed, 8 Apr 2020 19:16:45 +0530 Message-Id: <1586353607-32222-20-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586353607-32222-1-git-send-email-rnayak@codeaurora.org> References: <1586353607-32222-1-git-send-email-rnayak@codeaurora.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org QSPI needs to vote on a performance state of a power domain depending on the clock rate. Add support for it by specifying the perf state/clock rate as an OPP table in device tree. Signed-off-by: Rajendra Nayak Cc: Alok Chauhan Cc: Akash Asthana Cc: linux-spi@vger.kernel.org --- drivers/spi/spi-qcom-qspi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index 3c4f83b..42a9511 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -235,7 +236,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master, speed_hz = xfer->speed_hz; /* In regular operation (SBL_EN=1) core must be 4x transfer clock */ - ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4); + ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4); if (ret) { dev_err(ctrl->dev, "Failed to set core clk %d\n", ret); return ret; @@ -481,6 +482,9 @@ static int qcom_qspi_probe(struct platform_device *pdev) master->handle_err = qcom_qspi_handle_err; master->auto_runtime_pm = true; + dev_pm_opp_set_clkname(&pdev->dev, "core"); + dev_pm_opp_of_add_table(&pdev->dev); + pm_runtime_enable(dev); ret = spi_register_master(master); @@ -490,6 +494,7 @@ static int qcom_qspi_probe(struct platform_device *pdev) pm_runtime_disable(dev); exit_probe_master_put: + dev_pm_opp_of_remove_table(&pdev->dev); spi_master_put(master); return ret; @@ -499,6 +504,8 @@ static int qcom_qspi_remove(struct platform_device *pdev) { struct spi_master *master = platform_get_drvdata(pdev); + dev_pm_opp_of_remove_table(&pdev->dev); + /* Unregister _before_ disabling pm_runtime() so we stop transfers */ spi_unregister_master(master); @@ -512,6 +519,7 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); struct qcom_qspi *ctrl = spi_master_get_devdata(master); + dev_pm_opp_set_rate(dev, 0); clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks); return 0;