From patchwork Fri Apr 10 07:17:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Louis Kuo X-Patchwork-Id: 11482799 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD96315AB for ; Fri, 10 Apr 2020 07:17:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 85853216FD for ; Fri, 10 Apr 2020 07:17:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IVtYDc3k" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726666AbgDJHRl (ORCPT ); Fri, 10 Apr 2020 03:17:41 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:33511 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726648AbgDJHRl (ORCPT ); Fri, 10 Apr 2020 03:17:41 -0400 X-UUID: 37f8f89f407d40d5966b6ea8cc4d4d24-20200410 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=kSc1VSUFMhS93AZxKPxNBlcYGw6yPmLBY8gUjRDuIcg=; b=IVtYDc3kg9Cp0KsptcASnXMZhuUYgq5sb0cXEcccQ777kllcmwauRdtPmcS9rflxDzJ0YriHQzW7MOlKPmNc5Ig6IwFftgFdu35jC/Z3qA55Eo6Qoy//n4YAI2wzelA56cDy6tJDBSU2rxXqaPqk5ZCfH8fsspctpWtlyOuNbew=; X-UUID: 37f8f89f407d40d5966b6ea8cc4d4d24-20200410 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 748242160; Fri, 10 Apr 2020 15:17:34 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Apr 2020 15:17:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 10 Apr 2020 15:17:30 +0800 From: Louis Kuo To: , , , , , CC: , , , , , , , , , , , , , Subject: [RFC PATCH V6 2/3] dt-bindings: mt8183: Add sensor interface dt-bindings Date: Fri, 10 Apr 2020 15:17:22 +0800 Message-ID: <20200410071723.19720-3-louis.kuo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200410071723.19720-1-louis.kuo@mediatek.com> References: <20200410071723.19720-1-louis.kuo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds the DT binding documentation for the sensor interface module in Mediatek SoCs. Signed-off-by: Louis Kuo --- .../bindings/media/mediatek-seninf.yaml | 219 ++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-seninf.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek-seninf.yaml new file mode 100644 index 000000000000..c9e5776a2bd0 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-seninf.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek-seninf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek seninf MIPI-CSI2 host driver + +maintainers: + - Louis Kuo + +description: | + Seninf MIPI-CSI2 host driver is a HW camera interface controller. It support + a widely adopted, simple, high-speed protocol primarily intended for + point-to-point image and video transmission between cameras and host devices. + +properties: + compatible: + const: mediatek,mt8183-seninf + + reg: + minItems: 2 + items: + - description: The Seninf main register region + - description: The RX register region + + reg-names: + minItems: 2 + items: + - const: base + - const: rx + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Seninf camsys clock + - description: Seninf top mux clock + + clock-names: + items: + - const: clk_cam_seninf + - const: clk_top_mux_seninf + + # See ./video-interfaces.txt for details + ports: + type: object + additionalProperties: false + + properties: + port@0: + type: object + description: connection point for sensor at port 0 + additionalProperties: false + + properties: + reg: + const: 0 + + patternProperties: + endpoint: + type: object + additionalProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + remote-endpoint: true + + port@1: + type: object + description: connection point for sensor at port 1 + additionalProperties: false + + properties: + reg: + const: 1 + + patternProperties: + endpoint: + type: object + additionalProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + remote-endpoint: true + + port@4: + type: object + description: connection point for camsys + additionalProperties: false + + properties: + reg: + const: 4 + + patternProperties: + endpoint: + type: object + additionalProperties: false + + properties: + remote-endpoint: true + + required: + - port@0 + - port@1 + - port@4 + +required: + - compatible + - interrupts + - clocks + - clock-names + - power-domains + - ports + +additionalProperties: false + +examples: + - | + + #include + #include + #include + #include + + parent0: parent@0 { + #address-cells = <2>; + #size-cells = <2>; + + seninf: seninf@1a040000 { + compatible = "mediatek,mt8183-seninf"; + reg = <0 0x1a040000 0 0x8000>, + <0 0x11c80000 0 0x6000>; + reg-names = "base", "rx"; + interrupts = ; + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>; + clocks = <&camsys CLK_CAM_SENINF>, + <&topckgen CLK_TOP_MUX_SENINF>; + clock-names = "clk_cam_seninf", "clk_top_mux_seninf"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_in_bcam: endpoint { + data-lanes = <0 1 3 4>; + remote-endpoint = <&bcam_out>; + }; + }; + + port@1 { + reg = <1>; + + mipi_in_fcam: endpoint { + data-lanes = <1>; + remote-endpoint = <&fcam_out>; + }; + }; + + port@4 { + reg = <4>; + + seninf_camisp_endpoint: endpoint { + remote-endpoint = <&camisp_endpoint>; + }; + }; + }; + }; + + i2c2: i2c@11009000 { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + wcam: camera@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + + port { + bcam_out: endpoint { + remote-endpoint = <&mipi_in_bcam>; + data-lanes = <0 1 3 4>; + }; + }; + }; + }; + + i2c4: i2c@11008000 { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + ucam: camera@3c { + compatible = "ovti,ov2685"; + reg = <0x3c>; + + port { + fcam_out: endpoint { + remote-endpoint = <&mipi_in_fcam>; + data-lanes = <1>; + }; + }; + }; + }; + }; \ No newline at end of file From patchwork Fri Apr 10 07:17:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Louis Kuo X-Patchwork-Id: 11482803 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B897814B4 for ; Fri, 10 Apr 2020 07:17:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 99EF921655 for ; Fri, 10 Apr 2020 07:17:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HCaRMZW4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726671AbgDJHRo (ORCPT ); Fri, 10 Apr 2020 03:17:44 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:55079 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726650AbgDJHRo (ORCPT ); Fri, 10 Apr 2020 03:17:44 -0400 X-UUID: f31927d3540146769e684233bfe988e4-20200410 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ygWe+eLtAFpl7pbb42yoKAd2QeY0+GuA6Di3Dh7DXzY=; b=HCaRMZW4ivGsHsJ1BJ+bY+/A8A2Nb72V8QzlxhUuMredEpdQOg5hrcwcBFhmPPoTnZLFuF579QEHykwT73qfn6++1trN7FG7cFoD9+uZ6ZIwWkV7jFT1NtNlHlOc/c3waZ6FmSApCwObVqfVW6w4MXGHJv2IAZVaSqbvdSfbybc=; X-UUID: f31927d3540146769e684233bfe988e4-20200410 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1426561054; Fri, 10 Apr 2020 15:17:38 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Apr 2020 15:17:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 10 Apr 2020 15:17:31 +0800 From: Louis Kuo To: , , , , , CC: , , , , , , , , , , , , , Subject: [RFC PATCH V6 3/3] dts: arm64: mt8183: Add sensor interface nodes Date: Fri, 10 Apr 2020 15:17:23 +0800 Message-ID: <20200410071723.19720-4-louis.kuo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200410071723.19720-1-louis.kuo@mediatek.com> References: <20200410071723.19720-1-louis.kuo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add nodes for Mediatek's sensor interface device. Sensor interface module embedded in Mediatek SOCs, works as a HW camera interface controller intended for image and data transmission between cameras and host devices. Signed-off-by: Louis Kuo --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 433c62efab2d..5c7bed5a6f32 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -715,5 +715,30 @@ reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + seninf: seninf@1a040000 { + compatible = "mediatek,mt8183-seninf"; + reg = <0 0x1a040000 0 0x8000>, + <0 0x11c80000 0 0x6000>; + reg-names = "base", "rx"; + interrupts = ; + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>; + clocks = <&camsys CLK_CAM_SENINF>, + <&topckgen CLK_TOP_MUX_SENINF>; + clock-names = "clk_cam_seninf", "clk_top_mux_seninf"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + seninf_camisp_endpoint: endpoint { + remote-endpoint = <&camisp_endpoint>; + }; + }; + }; + }; }; };