From patchwork Tue Apr 14 10:16:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11487185 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 31ED9186E for ; Tue, 14 Apr 2020 10:17:22 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 2ADBE2075E; Tue, 14 Apr 2020 10:17:22 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pj1-f65.google.com (mail-pj1-f65.google.com [209.85.216.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 088B920644; Tue, 14 Apr 2020 10:17:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nvMNYnCv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 088B920644 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=zhang.lyra@gmail.com Received: by mail-pj1-f65.google.com with SMTP id a22so642706pjk.5; Tue, 14 Apr 2020 03:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UUOLAwdQkTXgo8GxSTlp4NyKaqeAihboXxkrwgIJ9RQ=; b=nvMNYnCvxU6AXKDQhE4/xaM6Vq/nl6lCTgWKQvCT5tFYoJOD5/xm+34M2OplTWeqQD hsZ0FguECz5/A18R/Tpb8Udd/StKTYdla6NdnupKLdSmhcB6YWStf3xyFK+XnbSyVxV4 CqrMMqKkrcgBAv2AiHhFeiSChZZ2pX/HAb90OKPHbgI0K6p14VtTmQnQN3jR1Ip1gNoy JHotoaZPV/ga86064t0Schj/CP/DISaD11C5y66w8Ze9JexitsaVYcGpILdy0q7ZxVb5 9KhcZp7wscQ3pXjiB33GyQPQnIiOHmiKpcMek8qaqeaIXC+xzmJupdrUgWWg01p6H0jb 3e+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UUOLAwdQkTXgo8GxSTlp4NyKaqeAihboXxkrwgIJ9RQ=; b=W36/GughzFBZFav0PhsHlRTV0CpC8lu9KorIl0gOKLOvlKWX0uT0RGElqF48xoAG05 ThbalZmTl9w82kRYoLyCxXKQOy4dU7ujg3ue7927SC7+/QwTXUFtXkx8jyns4gaw8zKt P8lhDrFCXlzZHfcxhYT/VMAyl3oPSYXebOE1+y7bye7FCZ8F0HgHIUdOQ4l2+e+d4cNp wjlhOFvNPRB+RFSTlqGQKTBdeJqZubgvBS7xDMGJuC/LsT2CAEL0D3qcAQCkEDLT1WlI bQf4FOMkU6Bz/YlkzSukFmpaEZE9NteAmbF9f9Oppu5gwn2IE84rMQ9CAHRe9JIUCeez EVig== X-Gm-Message-State: AGi0PuaLmOLF70s+aRz6wgNIFdddnHJAU4RfcxdnrZ1ChGndjcrWce1H lmnjuc0+uUUwIiX2dFPZBC7jLsqRVuM= X-Google-Smtp-Source: APiQypJv1NfGPCNfYcDnmJ54hke2+5RWOeQi45K2wFlPc3nsOkE24bFzWV8H1+zcaCryc79RTgEN5g== X-Received: by 2002:a17:90a:7784:: with SMTP id v4mr27999180pjk.30.1586859441192; Tue, 14 Apr 2020 03:17:21 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id r189sm9870182pgr.31.2020.04.14.03.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2020 03:17:20 -0700 (PDT) From: zhang.lyra@gmail.com List-Id: To: soc@kernel.org, Rob Herring , Mark Rutland Cc: Arnd Bergmann , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [RESEND PATCH 1/2] arm64: dts: Add SC9863A clock nodes Date: Tue, 14 Apr 2020 18:16:35 +0800 Message-Id: <20200414101636.24503-2-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200414101636.24503-1-zhang.lyra@gmail.com> References: <20200414101636.24503-1-zhang.lyra@gmail.com> MIME-Version: 1.0 From: Chunyan Zhang add clock devicetree nodes for SC9863A. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 24 ++++ arch/arm64/boot/dts/sprd/sharkl3.dtsi | 164 ++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index 2c590ca1d079..1ad6f6e95bca 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -159,6 +159,30 @@ interrupts = ; }; + ap_clk: clock-controller@21500000 { + compatible = "sprd,sc9863a-ap-clk"; + reg = <0 0x21500000 0 0x1000>; + clocks = <&ext_32k>, <&ext_26m>; + clock-names = "ext-32k", "ext-26m"; + #clock-cells = <1>; + }; + + aon_clk: clock-controller@402d0000 { + compatible = "sprd,sc9863a-aon-clk"; + reg = <0 0x402d0000 0 0x1000>; + clocks = <&ext_26m>, <&rco_100m>, + <&ext_32k>, <&ext_4m>; + clock-names = "ext-26m", "rco-100m", + "ext-32k", "ext-4m"; + #clock-cells = <1>; + }; + + mm_clk: clock-controller@60900000 { + compatible = "sprd,sc9863a-mm-clk"; + reg = <0 0x60900000 0 0x1000>; + #clock-cells = <1>; + }; + funnel@10001000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x10001000 0 0x1000>; diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi index 0222128b10f7..206a4afdab1c 100644 --- a/arch/arm64/boot/dts/sprd/sharkl3.dtsi +++ b/arch/arm64/boot/dts/sprd/sharkl3.dtsi @@ -16,6 +16,149 @@ #size-cells = <2>; ranges; + ap_ahb_regs: syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x20e00000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20e00000 0x4000>; + + apahb_gate: apahb-gate { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; + }; + }; + + pmu_regs: syscon@402b0000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x402b0000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x402b0000 0x4000>; + + pmu_gate: pmu-gate { + compatible = "sprd,sc9863a-pmu-gate"; + reg = <0 0x1200>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + aon_apb_regs: syscon@402e0000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x402e0000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x402e0000 0x4000>; + + aonapb_gate: aonapb-gate { + compatible = "sprd,sc9863a-aonapb-gate"; + reg = <0 0x1100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g2_regs: syscon@40353000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40353000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40353000 0x3000>; + + pll: pll { + compatible = "sprd,sc9863a-pll"; + reg = <0 0x100>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g4_regs: syscon@40359000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40359000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40359000 0x3000>; + + mpll: mpll { + compatible = "sprd,sc9863a-mpll"; + reg = <0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g5_regs: syscon@4035c000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x4035c000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4035c000 0x3000>; + + rpll: rpll { + compatible = "sprd,sc9863a-rpll"; + reg = <0 0x100>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g7_regs: syscon@40363000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40363000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40363000 0x3000>; + + dpll: dpll { + compatible = "sprd,sc9863a-dpll"; + reg = <0 0x100>; + #clock-cells = <1>; + }; + }; + + mm_ahb_regs: syscon@60800000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60800000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60800000 0x3000>; + + mm_gate: mm-gate { + compatible = "sprd,sc9863a-mm-gate"; + reg = <0 0x1100>; + #clock-cells = <1>; + }; + }; + + ap_apb_regs: syscon@71300000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x71300000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x71300000 0x4000>; + + apapb_gate: apapb-gate { + compatible = "sprd,sc9863a-apapb-gate"; + reg = <0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + apb@70000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -75,4 +218,25 @@ clock-frequency = <26000000>; clock-output-names = "ext-26m"; }; + + ext_32k: ext-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ext_4m: ext-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + rco_100m: rco-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; }; From patchwork Tue Apr 14 10:16:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11487187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BAA813B2 for ; Tue, 14 Apr 2020 10:17:26 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 8467C20644; Tue, 14 Apr 2020 10:17:26 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pj1-f66.google.com (mail-pj1-f66.google.com [209.85.216.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E49120732; Tue, 14 Apr 2020 10:17:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pOQVp73D" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5E49120732 Authentication-Results: mail.kernel.org; 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Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index 1ad6f6e95bca..8cf4a6575980 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2019, Unisoc Inc. */ +#include #include #include "sharkl3.dtsi" @@ -543,5 +544,46 @@ }; }; }; + + ap-ahb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdio0: sdio@20300000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20300000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_SDIO0_2X>, + <&apahb_gate CLK_SDIO0_EB>; + assigned-clocks = <&aon_clk CLK_SDIO0_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <4>; + no-sdio; + no-mmc; + }; + + sdio3: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&aon_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + }; + }; }; };