From patchwork Wed Apr 15 02:57:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489651 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1CEFA14DD for ; Wed, 15 Apr 2020 03:00:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 058D720784 for ; Wed, 15 Apr 2020 03:00:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="HwWfGRLR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729065AbgDOC5v (ORCPT ); Tue, 14 Apr 2020 22:57:51 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:12679 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728429AbgDOC5r (ORCPT ); Tue, 14 Apr 2020 22:57:47 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:55:58 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:47 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:47 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:46 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:46 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:46 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 1/9] arm64: tegra: Fix sor powergate clocks and reset Date: Tue, 14 Apr 2020 19:57:35 -0700 Message-ID: <1586919463-30542-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919358; bh=PTc2SyRS9NP+68XdMh+c6cj6nLmKTNHZwxALx6dnzdM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=HwWfGRLRiL3iq1+wLiMWHhw1zeNL5ViLWjAZ5OKqooBpEDkLzHglOp/8xXnqyMBaE tuR88U4kTDTd/OUghr5q2XU593Ks+9lu4Hn2e0SKHd/oT/435j9WmKVNyI5wOmxWm2 6KWX69qlHDH75IIA9/0rL2HGEQ16MyjzBarhAtHeNaUWwIKiUvX7g2cNH9NEc15gub Q3MqIExAegr4iRtOJYuFd6R6vY1QdrKCdOdXfFqekWhr70yY2hx9sXVNk8Mpie4J14 nKD+H3mRLXPE3KucnpaFPQrUK+z1OOErtL/vakd2YN/lN5vWyjx6imuWZYMYHbq18m TRGdD0xjF87DA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 device tree lists csi clock and reset under SOR powergate node. But Tegra210 has csicil in SOR partition and csi in VENC partition. So, this patch includes fix for sor powergate node. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 64c46ce..d0eff92 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -796,7 +796,9 @@ pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, @@ -804,7 +806,6 @@ <&tegra_car TEGRA210_CLK_MIPI_CAL>; resets = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, From patchwork Wed Apr 15 02:57:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E5BDB15AB for ; Wed, 15 Apr 2020 02:59:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDEF2206D5 for ; Wed, 15 Apr 2020 02:59:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="olS8yizg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729258AbgDOC5x (ORCPT ); Tue, 14 Apr 2020 22:57:53 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3762 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728518AbgDOC5r (ORCPT ); Tue, 14 Apr 2020 22:57:47 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:56:49 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:47 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:47 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:47 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:47 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:47 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 2/9] arm64: tegra: Add reset-cells to mc Date: Tue, 14 Apr 2020 19:57:36 -0700 Message-ID: <1586919463-30542-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919409; bh=fypsljnYXUQBk09pkBuzFp0S2nxT0B9eauugx/SlCBI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=olS8yizgERD8wHAiSWF1BE6Ffa/5RT3QVqpY0XJBu4v+ktc5ihhBeJgKbbqYxTUe6 webSQhfmPqqdCcYporhDaV/G73I8YQkcYGmgzpha76wejy56CkYjg2ElyFp8N9kHUU IAdaoCO2QyUgZHRcBuBJXbi5G1/CLZFmtpLinA0mPPF+vfAuGHwp7hxPxNVWCaoMzo SVkt4jVV/ZoZ+teCVDtA7SEXs8IlGYFMSwZIrTP/kz24gx2mKi6hrrMU/KXrMFQMYN 8JCsOxG4Xhqa67DdVORyVmemvvuqBflW8U8IucwMefRFWWR2fA9e27sfgnbT7naYtg q+DWu6DBWqogg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 device tree is missing reset-cells property for mc node. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d0eff92..5b1dfd8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -894,6 +894,7 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; sata@70020000 { From patchwork Wed Apr 15 02:57:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489649 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C97BB14DD for ; Wed, 15 Apr 2020 03:00:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0DA72083B for ; Wed, 15 Apr 2020 03:00:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="HiQvcxYi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393038AbgDOC7x (ORCPT ); Tue, 14 Apr 2020 22:59:53 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17542 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728519AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:57:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:48 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:48 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:48 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:47 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Date: Tue, 14 Apr 2020 19:57:37 -0700 Message-ID: <1586919463-30542-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919455; bh=Aw2TIrfzrAVXZOn1lDfsAGIvwrb7U15QVjnSRgzRbvc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=HiQvcxYik8mYbnombYfB0h0C2bQxXEIKVLvN2QKEW1wh5yN1I6o0QfvzWrJRhYZbX ejNX5ZyRSh3oxbb/bbSiUd/GUnmnz5bTFVzWow1TEEhP7OLUKGNAKo7dFwyAe73v+m MLY2MGJTuQfLohFDR/F2GxDOWq9grbNRL5hJxDKjzhuWxk0hCub4apODo7mHAaOgQO xRajqIWlnwhiMa2YFw0pr38bL8+T9ZC4gutaIQK9wzijCzCfL48AZvkwvrzN4EvBfP qa6ESNJ7iXzoueuW7l9yfjaYJKb5WgmB9q5bGcaevr286T9MT10U4RZ20njnM+P1dM 8lcqd0gW3+qbA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 uses PLLD out internally for CSI TPG. This patch adds clk id for this CSI TPG clock from PLLD. Acked-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra210-car.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b..d8909e0 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -351,7 +351,7 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ +#define TEGRA210_CLK_CSI_TPG 320 /* 321 */ #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 From patchwork Wed Apr 15 02:57:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B943714DD for ; Wed, 15 Apr 2020 02:58:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EBF02072D for ; Wed, 15 Apr 2020 02:58:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="rDd/7f6S" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729355AbgDOC5z (ORCPT ); Tue, 14 Apr 2020 22:57:55 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3768 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728671AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:56:50 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:48 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:48 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:48 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:48 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Tue, 14 Apr 2020 19:57:38 -0700 Message-ID: <1586919463-30542-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919410; bh=/06MYnopqzjyrf2N0nRAUhGBnkcd6r/kBjlHyehzo9I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rDd/7f6Suh9mmisKphr+X2KO6ruiJ6ZTLWX3BH3+/kxfUXwtpR0Y9QDwYTlScgsLr 0dawAxCrd+sqSGmKpGyOfTV2Erlrl2SlgD7yIuz7MsXiVxE5uQ0f9V+HDaxniPsIxA LcDCGAblUvtqycfcEYTHHr/piTWWy0JhJvKrC0teR/6xFdrd24OR9jgv3BLpp2zzQ8 E2U0X9XV8RKxxy18fcAG6cob+BSi3uap30rFeVFuno4xMxVLYGCr8RllL0aKwYgP86 TksnFdicdQjtqazGq54x6sNDSKFcGCu/gLeLbiNGskA2isf0KGFF4BDtBdAaSNLxz9 U7KJviVALddcA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index defe3b7..81a879b 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, From patchwork Wed Apr 15 02:57:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489633 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 431FB14DD for ; Wed, 15 Apr 2020 02:59:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A0A02078B for ; Wed, 15 Apr 2020 02:59:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="DJkGGmuk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391638AbgDOC7R (ORCPT ); Tue, 14 Apr 2020 22:59:17 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:12687 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728780AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:56:00 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:49 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:49 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:49 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:49 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:49 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 5/9] dt-binding: tegra: Add VI and CSI bindings Date: Tue, 14 Apr 2020 19:57:39 -0700 Message-ID: <1586919463-30542-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919360; bh=k0ZY+QpTvuR3ErZcRwZs7p/uzlTM20jhJKkGltc+t5Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DJkGGmuk5ePCZzACD5j8BnNb0Qg/x0QEv416X0R13zg5qjTm/q8TdvcPyYWGLp9fm vGjUzQyRwo3ywx/MtlC7733FfBqw2OHEpXMbAvUGi5GUI0qDsq7BGlPjTTq45uXyyo 3Zat0FU/bJiaGdH1/Pu4h2oSIf7+xMKm2rXP+dfuTj33xZhr7qAwj1Bn86owMziEMG AFpWPNczJrxCi9CjcSQY9W7Tp/Iza/mh63crhpA40N+5AE3vNeK6rgnJrQcYVNxplT RDkpFYoBgG7/+Q0pp6r09ZIVH3CZuPAFKuFMXAU6pLqnmrvLUu4eAnOYaNp8m89pe2 Nf5XxioqCQNZQ== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra contains VI controller which can support up to 6 MIPI CSI camera sensors. Each Tegra CSI port from CSI unit can be one-to-one mapper to VI channel and can capture from an external camera sensor or from built-in test pattern generator. This patch adds dt-bindings for Tegra VI and CSI. Reviewed-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- .../display/tegra/nvidia,tegra20-host1x.txt | 73 ++++++++++++++++++---- 1 file changed, 60 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 9999255..4731921 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -40,14 +40,30 @@ of the following host1x client modules: Required properties: - compatible: "nvidia,tegra-vi" - - reg: Physical base address and length of the controller's registers. + - reg: Physical base address and length of the controller registers. - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. + - clocks: clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vi + - Tegra20/Tegra30/Tegra114/Tegra124: + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - vi + - Tegra210: + - power-domains: Must include venc powergate node as vi is in VE partition. + - Tegra210 has CSI part of VI sharing same host interface and register space. + So, VI device node should have CSI child node. + + - csi: mipi csi interface to vi + + Required properties: + - compatible: "nvidia,tegra210-csi" + - reg: Physical base address offset to parent and length of the controller + registers. + - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. + See ../clocks/clock-bindings.txt for details. + - power-domains: Must include sor powergate node as csicil is in + SOR partition. - epp: encoder pre-processor @@ -309,13 +325,44 @@ Example: reset-names = "mpe"; }; - vi { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 100>; - reset-names = "vi"; + vi@54080000 { + compatible = "nvidia,tegra210-vi"; + reg = <0x0 0x54080000 0x0 0x700>; + interrupts = ; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; epp { From patchwork Wed Apr 15 02:57:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489639 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3F9414DD for ; Wed, 15 Apr 2020 02:59:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B71F20787 for ; Wed, 15 Apr 2020 02:59:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="mkpWpeKx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2634727AbgDOC7P (ORCPT ); Tue, 14 Apr 2020 22:59:15 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3777 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728836AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:56:52 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:50 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:50 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:50 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:50 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:50 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 7/9] MAINTAINERS: Add Tegra Video driver section Date: Tue, 14 Apr 2020 19:57:41 -0700 Message-ID: <1586919463-30542-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919412; bh=b88GH42tRlmFWW/LUhlK8Cl0XZ1rw6pCd4qVM58B0gI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=mkpWpeKx9EJyGv/fiSBOhUBsa9eZ0MM3Hp/VsDUqAZ85LeSy5i6k01niQnZ8mBvL6 I2r9u94/nGOgD4WEK/PoZWFJwkbKYs1pv6vR4zUbub0DuwkJZxL+S9L4rZdR+KHZu+ z1ToIAzI2VWy86l514CYKfztNrG+4CWIMsDCyuSbx5TP8gt/7r7SCxM02inzo6ujZU hulSaTiK0Z4dB3CALGqxiQd9jbXEhi/TWGvigj13OA2bawAr4Oz9Qy43TdKTVj4ff1 Ka1P+cKar9FZf+LoflWo9nrKp36pJfE8DLwS6xSMcrZgW6c0tAUuqUXRaYxfobjkIk TxCCBDoJcmqKA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add maintainers and mailing list entries to Tegra Video driver section. Signed-off-by: Sowjanya Komatineni --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5872577..47be371 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16608,6 +16608,16 @@ M: Laxman Dewangan S: Supported F: drivers/spi/spi-tegra* +TEGRA VIDEO DRIVER +M: Thierry Reding +M: Jonathan Hunter +M: Sowjanya Komatineni +L: linux-media@vger.kernel.org +L: linux-tegra@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +F: drivers/staging/media/tegra/ + TEGRA XUSB PADCTL DRIVER M: JC Kuo S: Supported From patchwork Wed Apr 15 02:57:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489645 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDEF714DD for ; Wed, 15 Apr 2020 02:59:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B67472078B for ; Wed, 15 Apr 2020 02:59:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="J2JBgb+y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393043AbgDOC75 (ORCPT ); Tue, 14 Apr 2020 22:59:57 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17557 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729107AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:57:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:51 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:51 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:50 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Date: Tue, 14 Apr 2020 19:57:42 -0700 Message-ID: <1586919463-30542-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919458; bh=KEZ1lHNwQNYea9tamUq6xhOd3Wa4inGS2Z794lURij8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=J2JBgb+yrKQXv+Yi2bb/8GZfYpN7N6EqfuuPZeCJoBwZhmTgFaNZJSmbo1nAD2t46 l8fS9e+JYRIPgkDUFzs4jfWdDqcF65GlCQgSexlEcUWHcQPyfeFCMrnVbm2UI8ACha t7lbJ/Lm3gcvsAKMNdPH6PlhSlxMtIx3TKMh8j792UfbkLHF3ep3BqObHH0eaNfyS+ WXwWNIbt2YDLFclYTNRBT1F3Kc9sy013xiQu7GRvuGfYs7kywO++jCsfhpvmdLkJuh JHBqHKVaWbWgSdLAMfbdDioy2PzgSt+FXSPgJDTetMoG/Y4IfsVBDq66mgRQUcyvnA uA1w/+ySupKNw== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch adds ID for Tegra210 VI controller reset to use with device tree. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/reset/tegra210-car.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 9dc84ec..8755946 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -10,5 +10,6 @@ #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) +#define TEGRA210_RST_VI 20 #endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */ From patchwork Wed Apr 15 02:57:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11489621 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2658214DD for ; Wed, 15 Apr 2020 02:58:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 05AD22072D for ; Wed, 15 Apr 2020 02:58:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="SziGpGhJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729418AbgDOC54 (ORCPT ); Tue, 14 Apr 2020 22:57:56 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3781 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729115AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:56:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:51 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:51 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:51 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Date: Tue, 14 Apr 2020 19:57:43 -0700 Message-ID: <1586919463-30542-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919413; bh=yB3b29VbNFtTvMcPZCMVxLppaVECoZp9WEY70dWiuUY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=SziGpGhJe980GifGZkqDEWB8sMEsV/YcQhL0tGJ5mSYGCelUxz/IhdB7ZmiVt+vdR 69DcoiLaInltbB98jxe8gLeJxwml0SqzLLPjnMcJVlzzZrsu/35pxuQSqDCucPjPyW FVpAs2RXLycyJBMSW343mL6V7XZIi80gg3o3yKk41QztmmV7y6yLvd0RxorNu97f/t hEVJVcbkrR5FIcCEObYIN8+mmBm2wQ7N5GHmsRul+PkjvbUWp7w0ilRcGj54BiX202 ZkjBR83hGgnb05VgBkrMewCXwnx1xFFN0G6npZxNftn+S+m4lFFo01UulkXiSFFM8E 7Y7COsPM3lDfg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 46 +++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c2..b57d837 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5b1dfd8..cad42a7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,44 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; tsec@54100000 { @@ -839,6 +874,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car TEGRA210_RST_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 {