From patchwork Fri Apr 17 22:17:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11496187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4438913 for ; Fri, 17 Apr 2020 22:23:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9C7F220776 for ; Fri, 17 Apr 2020 22:23:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="itM0c/NF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728771AbgDQWXt (ORCPT ); Fri, 17 Apr 2020 18:23:49 -0400 Received: from plaes.org ([188.166.43.21]:57464 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728617AbgDQWXq (ORCPT ); Fri, 17 Apr 2020 18:23:46 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:9d4d:940e:6b9e:3deb:4]) by plaes.org (Postfix) with ESMTPSA id 14F6940E29; Fri, 17 Apr 2020 22:17:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1587161873; bh=9OnaF3dHK/bJkvPCqojRkILBF7al9aw6MaMXsXHyyK0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=itM0c/NFnkFtDpdiCJTYKu1kSOTX7JKDdQ5nuJrtCDtTfhG+NDleV88SjKY1u+9Va lh9zFOm+dMDnbb61MSngQ2qIa4XygmAAUBwF7l0pUeEDEOqybmbOWwwHWyXKiQA4K7 sqRJcNG9DkpX6x712sQ9AGSOVUUhQgfdUGvR7ofuimj55CiaDGW5LhZkCfz3QGTQRv cZjGOMj9N5M03wHFqJ+wUTko95OohNbtP7tfGJ1gsHXkmA/xShDWsgOTx97qRpuE0A 2Mf/s/+KEeIO2Cq/tcXF+4TjGq5I2riavpZQinnLCE7xstM4cbl2x/kGDNXF/tp+mw 1Ec/xeamHMIqg== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH 1/4] clk: sunxi-ng: a10/a20: rewrite init code to a platform driver Date: Sat, 18 Apr 2020 01:17:27 +0300 Message-Id: <20200417221730.555954-2-plaes@plaes.org> X-Mailer: git-send-email 2.25.2 In-Reply-To: <20200417221730.555954-1-plaes@plaes.org> References: <20200417221730.555954-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In order to register regmap for sun7i CCU, there needs to be a device structure already bound to the CCU device node. Convert the sun4i/sun7i CCU setup to platform driver to use it later as platform device. Signed-off-by: Priit Laes --- drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 77 ++++++++++++++++++++-------- 1 file changed, 56 insertions(+), 21 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c index f32366d9336e..839e9d5a1cff 100644 --- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c @@ -7,7 +7,8 @@ #include #include -#include +#include +#include #include "ccu_common.h" #include "ccu_reset.h" @@ -1425,19 +1426,10 @@ static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = { .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets), }; -static void __init sun4i_ccu_init(struct device_node *node, - const struct sunxi_ccu_desc *desc) +static void bootstrap_clocks(void __iomem *reg) { - void __iomem *reg; u32 val; - reg = of_io_request_and_map(node, 0, of_node_full_name(node)); - if (IS_ERR(reg)) { - pr_err("%s: Could not map the clock registers\n", - of_node_full_name(node)); - return; - } - val = readl(reg + SUN4I_PLL_AUDIO_REG); /* @@ -1463,20 +1455,63 @@ static void __init sun4i_ccu_init(struct device_node *node, val = readl(reg + SUN4I_AHB_REG); val &= ~GENMASK(7, 6); writel(val | (2 << 6), reg + SUN4I_AHB_REG); - - sunxi_ccu_probe(node, reg, desc); } -static void __init sun4i_a10_ccu_setup(struct device_node *node) +static int sun4i_a10_ccu_probe(struct platform_device *pdev) { - sun4i_ccu_init(node, &sun4i_a10_ccu_desc); + struct resource *res; + void __iomem *reg; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + bootstrap_clocks(reg); + + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun4i_a10_ccu_desc); } -CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu", - sun4i_a10_ccu_setup); -static void __init sun7i_a20_ccu_setup(struct device_node *node) +static int sun7i_a20_ccu_probe(struct platform_device *pdev) { - sun4i_ccu_init(node, &sun7i_a20_ccu_desc); + struct resource *res; + void __iomem *reg; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + bootstrap_clocks(reg); + + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun7i_a20_ccu_desc); } -CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu", - sun7i_a20_ccu_setup); + + +static const struct of_device_id sun4i_a10_ccu_ids[] = { + { .compatible = "allwinner,sun4i-a10-ccu"}, + { } +}; + +static struct platform_driver sun4i_a10_ccu_driver = { + .probe = sun4i_a10_ccu_probe, + .driver = { + .name = "sun4i-a10-ccu", + .of_match_table = sun4i_a10_ccu_ids, + }, +}; +builtin_platform_driver(sun4i_a10_ccu_driver); + +static const struct of_device_id sun7i_a20_ccu_ids[] = { + { .compatible = "allwinner,sun7i-a20-ccu"}, + { } +}; + +static struct platform_driver sun7i_a20_ccu_driver = { + .probe = sun7i_a20_ccu_probe, + .driver = { + .name = "sun7i-a20-ccu", + .of_match_table = sun7i_a20_ccu_ids, + }, +}; +builtin_platform_driver(sun7i_a20_ccu_driver); From patchwork Fri Apr 17 22:17:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11496189 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 414FC913 for ; Fri, 17 Apr 2020 22:23:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2AF3922240 for ; Fri, 17 Apr 2020 22:23:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="TZclkyba" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728680AbgDQWXq (ORCPT ); Fri, 17 Apr 2020 18:23:46 -0400 Received: from plaes.org ([188.166.43.21]:57460 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728517AbgDQWXq (ORCPT ); Fri, 17 Apr 2020 18:23:46 -0400 X-Greylist: delayed 350 seconds by postgrey-1.27 at vger.kernel.org; Fri, 17 Apr 2020 18:23:45 EDT Received: from localhost (unknown [IPv6:2001:1530:1000:9d4d:940e:6b9e:3deb:4]) by plaes.org (Postfix) with ESMTPSA id A7D8840F77; Fri, 17 Apr 2020 22:17:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1587161875; bh=R/e4AeS+hYtR1SV4lPnHnWWGgqogYvwGJXb2bJni8Gs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TZclkybauT9AxtT/TF3Gf+6lkIYgIDJ33SAAPA7Z1QS2G+JfTqiHhragEBFO3DhFS OfUoqA4fOMbc5KFs9+r3FpQLDgaFVWdr3dMj5h+Gl8u1njA4Rw8oUzRVddcgTdUJGi yCKykq9IOyV7KLmIszFsL69mqkL3vTNhmE7zydscV2AlVepJgGL9832h8TD2dUaofB onfU46E8V+TyUsQg6k8UN7Qk+nlmqSNNA/RCPybFbkTu0am88SnX18QAJN4m3UqLgQ BgiZ7wwuHfUJ019K34mfd9zZDYNqF3ALiyU+aKhyAKARtd5Gvnzt2X+voW8qTld69L RNhCre324KBBg== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH 2/4] clk: sunxi-ng: a20: export a regmap to access the GMAC register Date: Sat, 18 Apr 2020 01:17:28 +0300 Message-Id: <20200417221730.555954-3-plaes@plaes.org> X-Mailer: git-send-email 2.25.2 In-Reply-To: <20200417221730.555954-1-plaes@plaes.org> References: <20200417221730.555954-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Only GMAC register is allowed to be written, read access to registers is not restricted. Export a regmap of the CCU. Signed-off-by: Priit Laes --- drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c index 839e9d5a1cff..cba51c2c7eba 100644 --- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c @@ -1426,6 +1426,30 @@ static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = { .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets), }; +/* + * Add regmap for the GMAC driver (dwmac-sun8i) to allow access to + * GMAC configuration register. + */ + +#define SUN7I_A20_GMAC_CFG_REG 0x164 +static bool sun7i_a20_ccu_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUN7I_A20_GMAC_CFG_REG) + return true; + return false; +} + +static struct regmap_config sun7i_a20_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x1f4, /* clk_out_b */ + + .readable_reg = sun7i_a20_ccu_regmap_accessible_reg, + .writeable_reg = sun7i_a20_ccu_regmap_accessible_reg, +}; + static void bootstrap_clocks(void __iomem *reg) { u32 val; @@ -1474,6 +1498,7 @@ static int sun4i_a10_ccu_probe(struct platform_device *pdev) static int sun7i_a20_ccu_probe(struct platform_device *pdev) { + struct regmap *regmap; struct resource *res; void __iomem *reg; @@ -1484,6 +1509,12 @@ static int sun7i_a20_ccu_probe(struct platform_device *pdev) bootstrap_clocks(reg); + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun7i_a20_ccu_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun7i_a20_ccu_desc); } From patchwork Fri Apr 17 22:17:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11496201 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30022913 for ; Fri, 17 Apr 2020 22:29:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 13811214D8 for ; Fri, 17 Apr 2020 22:29:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="af1IWOXx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728912AbgDQW3R (ORCPT ); Fri, 17 Apr 2020 18:29:17 -0400 Received: from plaes.org ([188.166.43.21]:57504 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728470AbgDQW3Q (ORCPT ); Fri, 17 Apr 2020 18:29:16 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:9d4d:940e:6b9e:3deb:4]) by plaes.org (Postfix) with ESMTPSA id 32A4E4125A; Fri, 17 Apr 2020 22:17:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1587161876; bh=B67BSstoliZJd4PmHe0yq3zW5vKkysNKwBTuxR2rqNg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=af1IWOXxI0lpIUosVpoZq3rzh1E6KKhS3HqyIJn3X4fZEPZZf+o31wYanifmvwmh5 lR0odqnMfuGhG2du6WnkuHvDFUpVYOM1/rbbxBW3xIWd/WVnD13UYZqsVooTvk74Cn uZMCMkYcMX5Ev7EBHfhPcTOshYqYyGDKsv10DnbkwCM2/OI9MLmd+mIf8El7Woa4Uq uWW7wdgKmqQOuzkpcwgy253QmtEvaDOBp7vQ81vpabr71oyv0FFiOwOKWt3Di1hYK1 AUKkLFgNKA3BSVW7alM88sTwKiT5Msm1gV5/zH+tsG0L/kc5rpHlniC9d4xHEPW1Tt qVtgBb4SNBgug== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH 3/4] net: stmmac: dwmac-sunxi: Implement syscon-based clock handling Date: Sat, 18 Apr 2020 01:17:29 +0300 Message-Id: <20200417221730.555954-4-plaes@plaes.org> X-Mailer: git-send-email 2.25.2 In-Reply-To: <20200417221730.555954-1-plaes@plaes.org> References: <20200417221730.555954-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert the sun7i-gmac driver to use a regmap-based driver, instead of relying on the custom clock implementation. This allows to get rid of the last custom clock in the sun7i device tree making the sun7i fully CCU-compatible. Compatibility with existing devicetrees is retained. Signed-off-by: Priit Laes --- .../net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 124 ++++++++++++++++-- 1 file changed, 116 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c index 0e1ca2cba3c7..3476920bc762 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c @@ -12,8 +12,11 @@ #include #include #include +#include #include #include +#include +#include #include "stmmac_platform.h" @@ -22,10 +25,20 @@ struct sunxi_priv_data { int clk_enabled; struct clk *tx_clk; struct regulator *regulator; + struct regmap_field *regmap_field; +}; + +/* EMAC clock register @ 0x164 in the CCU address range */ +static const struct reg_field ccu_reg_field = { + .reg = 0x164, + .lsb = 0, + .msb = 31, }; #define SUN7I_GMAC_GMII_RGMII_RATE 125000000 #define SUN7I_GMAC_MII_RATE 25000000 +#define SUN7I_A20_RGMII_CLK ((3 << 1) | (1 << 12)) +#define SUN7I_A20_MII_CLK (1 << 12) static int sun7i_gmac_init(struct platform_device *pdev, void *priv) { @@ -38,7 +51,20 @@ static int sun7i_gmac_init(struct platform_device *pdev, void *priv) return ret; } - /* Set GMAC interface port mode + if (gmac->regmap_field) { + if (phy_interface_mode_is_rgmii(gmac->interface)) { + regmap_field_write(gmac->regmap_field, + SUN7I_A20_RGMII_CLK); + return clk_prepare_enable(gmac->tx_clk); + } + regmap_field_write(gmac->regmap_field, SUN7I_A20_MII_CLK); + return clk_enable(gmac->tx_clk); + } + + /* Legacy devicetree support */ + + /* + * Set GMAC interface port mode * * The GMAC TX clock lines are configured by setting the clock * rate, which then uses the auto-reparenting feature of the @@ -62,9 +88,15 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) { struct sunxi_priv_data *gmac = priv; - if (gmac->clk_enabled) { + if (gmac->regmap_field) { + regmap_field_write(gmac->regmap_field, 0); clk_disable(gmac->tx_clk); - gmac->clk_enabled = 0; + } else { + /* Legacy devicetree support */ + if (gmac->clk_enabled) { + clk_disable(gmac->tx_clk); + gmac->clk_enabled = 0; + } } clk_unprepare(gmac->tx_clk); @@ -72,10 +104,53 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) regulator_disable(gmac->regulator); } +static struct regmap *sun7i_gmac_get_syscon_from_dev(struct device_node *node) +{ + struct device_node *syscon_node; + struct platform_device *syscon_pdev; + struct regmap *regmap = NULL; + + syscon_node = of_parse_phandle(node, "syscon", 0); + if (!syscon_node) + return ERR_PTR(-ENODEV); + + syscon_pdev = of_find_device_by_node(syscon_node); + if (!syscon_pdev) { + /* platform device might not be probed yet */ + regmap = ERR_PTR(-EPROBE_DEFER); + goto out_put_node; + } + + /* If no regmap is found then the other device driver is at fault */ + regmap = dev_get_regmap(&syscon_pdev->dev, NULL); + if (!regmap) + regmap = ERR_PTR(-EINVAL); + + platform_device_put(syscon_pdev); +out_put_node: + of_node_put(syscon_node); + return regmap; +} + static void sun7i_fix_speed(void *priv, unsigned int speed) { struct sunxi_priv_data *gmac = priv; + if (gmac->regmap_field) { + clk_disable(gmac->tx_clk); + clk_unprepare(gmac->tx_clk); + if (speed == 1000) + regmap_field_write(gmac->regmap_field, + SUN7I_A20_RGMII_CLK); + else + regmap_field_write(gmac->regmap_field, + SUN7I_A20_MII_CLK); + clk_prepare_enable(gmac->tx_clk); + return; + } + + /* Legacy devicetree support... */ + /* only GMII mode requires us to reconfigure the clock lines */ if (gmac->interface != PHY_INTERFACE_MODE_GMII) return; @@ -102,6 +177,8 @@ static int sun7i_gmac_probe(struct platform_device *pdev) struct stmmac_resources stmmac_res; struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; + struct device_node *syscon_node; + struct regmap *regmap = NULL; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -124,11 +201,42 @@ static int sun7i_gmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } - gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); - if (IS_ERR(gmac->tx_clk)) { - dev_err(dev, "could not get tx clock\n"); - ret = PTR_ERR(gmac->tx_clk); - goto err_remove_config_dt; + /* Attempt to fetch syscon node... */ + syscon_node = of_parse_phandle(dev->of_node, "syscon", 0); + if (syscon_node) { + gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "Could not get TX clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + + regmap = sun7i_gmac_get_syscon_from_dev(pdev->dev.of_node); + if (IS_ERR(regmap)) + regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); + goto err_remove_config_dt; + } + + gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, ccu_reg_field); + + if (IS_ERR(gmac->regmap_field)) { + ret = PTR_ERR(gmac->regmap_field); + dev_err(dev, "Unable to map syscon register: %d\n", ret); + goto err_remove_config_dt; + } + /* ...or fall back to legacy clock setup */ + } else { + dev_info(dev, "Falling back to legacy devicetree support!\n"); + gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "could not get tx clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } } /* Optional regulator for PHY */ From patchwork Fri Apr 17 22:17:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11496199 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ABA72913 for ; Fri, 17 Apr 2020 22:29:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 87707221E9 for ; Fri, 17 Apr 2020 22:29:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="lZETRBcX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728671AbgDQW3Q (ORCPT ); Fri, 17 Apr 2020 18:29:16 -0400 Received: from plaes.org ([188.166.43.21]:57506 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728496AbgDQW3Q (ORCPT ); Fri, 17 Apr 2020 18:29:16 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:9d4d:940e:6b9e:3deb:4]) by plaes.org (Postfix) with ESMTPSA id C54B6412C2; Fri, 17 Apr 2020 22:17:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1587161878; bh=CuWTSWogL5JToClyKPKUHBYOUHXu6/mkEKPAV4YLbVw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lZETRBcXeQXm8yzTNezI5LpsawhmT8InxOuYc/djy0Tr2ewY2eL3Q+CgV/M37HiTY Ok5hFWQ1wLhPv9cQyKOStSWzVJECt3nCDoVnfLaJymnL7tNDHDfYUgofkRBISORYZX YTGqG+6yh+QsHUxyvv2R9w5PGq758CdpEN2AxZ4WGZHJMSI4OZB8M4CEsCq7GoCUQZ AO1JX/rsW7h7DA5GdvIV9JNnZHAVv3TMtr3uHtDi+M2WTvv99yvTs/NpqwaN3gMoHQ wBSjctLImhQRE6JQ6TsAsjOKKEDxr9+Bm+T6QjHN8iIl30QWBRj6bovCWEtQLLTbqI 4gY/XgaRPPfmA== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH 4/4] ARM: dts: sun7i: Use syscon-based implementation for gmac Date: Sat, 18 Apr 2020 01:17:30 +0300 Message-Id: <20200417221730.555954-5-plaes@plaes.org> X-Mailer: git-send-email 2.25.2 In-Reply-To: <20200417221730.555954-1-plaes@plaes.org> References: <20200417221730.555954-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use syscon-based approach to access gmac clock configuration register, instead of relying on a custom clock driver. As a bonus, we can now drop the custom clock implementation and dummy clocks making sun7i fully CCU-compatible. Signed-off-by: Priit Laes --- arch/arm/boot/dts/sun7i-a20.dtsi | 36 +++----------------------------- 1 file changed, 3 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index ffe1d10a1a84..750962a94fad 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -219,37 +219,6 @@ osc32k: clk-32k { clock-frequency = <32768>; clock-output-names = "osc32k"; }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; }; @@ -1511,11 +1480,12 @@ mali: gpu@1c40000 { gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&ccu>; reg = <0x01c50000 0x10000>; interrupts = ; interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ccu CLK_AHB_GMAC>; + clock-names = "stmmaceth"; snps,pbl = <2>; snps,fixed-burst; snps,force_sf_dma_mode;