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Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT010.mail.protection.outlook.com (10.152.75.50) with Microsoft SMTP Server id 15.20.2921.25 via Frontend Transport; Mon, 20 Apr 2020 21:21:12 +0000 Received: from [149.199.38.66] (port=60257 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1jQdpt-0007rg-6z; Mon, 20 Apr 2020 14:20:13 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1jQdqq-0003Iv-7L; Mon, 20 Apr 2020 14:21:12 -0700 Received: from [172.23.62.221] (helo=xhdrdevl201.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jQdqj-0003FI-Sk; Mon, 20 Apr 2020 14:21:06 -0700 From: Venkateshwar Rao Gannavarapu To: hyun.kwon@xilinx.com, laurent.pinchart@ideasonboard.com, dri-devel@lists.freedesktop.org Subject: [RFC PATCH 1/2] dt-bindings: display: xlnx: Add Xilinx DSI TX subsystem bindings Date: Tue, 21 Apr 2020 02:50:55 +0530 Message-Id: <1587417656-48078-2-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587417656-48078-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> References: <1587417656-48078-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6361 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sandipk@xilinx.com, Venkateshwar Rao Gannavarapu , airlied@linux.ie, linux-kernel@vger.kernel.org, vgannava@xilinx.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This add a dt binding for Xilinx DSI TX subsystem. The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) based display interface. It supports the interface with the programmable logic (FPGA). Signed-off-by: Venkateshwar Rao Gannavarapu --- .../devicetree/bindings/display/xlnx/xlnx,dsi.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt new file mode 100644 index 0000000..ef69729 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Xilinx MIPI DSI Tx IP core + +The IP core supports transmission of video data in MIPI DSI protocol. + +Required properties: + - compatible: Should be "xlnx-dsi". + - reg: physical base address and length of the registers set for the device. + - xlnx,dsi-num-lanes: Possible number of DSI lanes for the Tx controller. + The values should be 1, 2, 3 or 4. Based on xlnx,dsi-num-lanes and + line rate for the MIPI D-PHY core in Mbps, the AXI4-stream received by + Xilinx MIPI DSI Tx IP core adds markers as per DSI protocol and the packet + thus framed is convered to serial data by MIPI D-PHY core. Please refer + Xilinx pg238 for more details. This value should be equal to the number + of lanes supported by the connected DSI panel. Panel has to support this + value or has to be programmed to the same value that DSI Tx controller is + configured to. + - xlnx,dsi-datatype: Color format. The value should be one of "MIPI_DSI_FMT_RGB888", + "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or "MIPI_DSI_FMT_RGB565". + - #address-cells, #size-cells: should be set respectively to <1> and <0> + according to DSI host bindings (see MIPI DSI bindings [1]) + - clock-names: Must contain "s_axis_aclk" and "dphy_clk_200M" in same order as + clocks listed in clocks property. + - clocks: List of phandles to Video and 200Mhz DPHY clocks. + - port: Logical block can be used / connected independently with + external device. In the display controller port nodes, topology + for entire pipeline should be described using the DT bindings defined in + Documentation/devicetree/bindings/graph.txt. + - simple_panel: The subnode for connected panel. This represents the + DSI peripheral connected to the DSI host node. Please refer to + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt. The + simple-panel driver has auo,b101uan01 panel timing parameters added along + with other existing panels. DSI driver derive the required Tx IP controller + timing values from the panel timing parameters. + +Required simple_panel properties: + - compatible: Value should be one of the panel names in + Documentation/devicetree/bindings/display/panel/. e.g. "auo,b101uan01". + For available panel compatible strings, please refer to bindings in + Documentation/devicetree/bindings/display/panel/ + +Optional properties: + - xlnx,dsi-cmd-mode: denotes command mode enable. + +[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt +[2]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + + mipi_dsi_tx_subsystem@80000000 { + compatible = "xlnx,dsi"; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,dsi-num-lanes = <4>; + xlnx,dsi-data-type = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "dphy_clk_200M", "s_axis_aclk"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + encoder_dsi_port: port@0 { + reg = <0>; + dsi_encoder: endpoint { + remote-endpoint = <&xdsi_ep>; + }; + }; + simple_panel: simple-panel@0 { + compatible = "auo,b101uan01"; + reg = <0>; + }; + }; From patchwork Mon Apr 20 21:20:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkateshwar Rao Gannavarapu X-Patchwork-Id: 11499905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA0DF81 for ; Mon, 20 Apr 2020 21:21:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A7E2A207FC for ; Mon, 20 Apr 2020 21:21:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="MVLWJf6v" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A7E2A207FC Authentication-Results: mail.kernel.org; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2764 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sandipk@xilinx.com, Venkateshwar Rao Gannavarapu , airlied@linux.ie, linux-kernel@vger.kernel.org, vgannava@xilinx.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video data from AXI-4 stream interface. It supports upto 4 lanes, optional register interface for the DPHY, multiple RGB color formats, command mode and video mode. This is a MIPI-DSI host driver and provides DSI bus for panels. This driver also helps to communicate with its panel using panel framework. Signed-off-by: Venkateshwar Rao Gannavarapu --- drivers/gpu/drm/xlnx/Kconfig | 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 768 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig index aa6cd88..73873cf 100644 --- a/drivers/gpu/drm/xlnx/Kconfig +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose this option if you have a Xilinx ZynqMP SoC with DisplayPort subsystem. + +config DRM_XLNX_DSI + tristate "Xilinx DRM DSI Subsystem Driver" + select DRM_MIPI_DSI + select DRM_PANEL + select DRM_PANEL_SIMPLE + help + This enables support for Xilinx MIPI-DSI. + This is a DRM/KMS driver for Xilinx programmable DSI controller. + Choose this option if you have a Xilinx MIPI DSI-TX controller + subsytem. diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile index 2b844c6..b7ee6ef 100644 --- a/drivers/gpu/drm/xlnx/Makefile +++ b/drivers/gpu/drm/xlnx/Makefile @@ -1,2 +1,4 @@ zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o + +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c new file mode 100644 index 0000000..b8cae59 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx FPGA MIPI DSI Tx Controller driver + * + * Copyright (C) 2017 - 2019 Xilinx, Inc. + * + * Authors: + * - Saurabh Sengar + * - Venkateshwar Rao Gannavarapu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include