From patchwork Wed Apr 22 16:32:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11504249 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ECA46912 for ; Wed, 22 Apr 2020 16:32:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D47C4214AF for ; Wed, 22 Apr 2020 16:32:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ZIBBWpNS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726625AbgDVQce (ORCPT ); Wed, 22 Apr 2020 12:32:34 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:19873 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726582AbgDVQcd (ORCPT ); Wed, 22 Apr 2020 12:32:33 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 22 Apr 2020 09:31:30 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 22 Apr 2020 09:32:32 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 22 Apr 2020 09:32:32 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 22 Apr 2020 16:32:32 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 22 Apr 2020 16:32:32 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 22 Apr 2020 09:32:32 -0700 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , Subject: [PATCH 5.4.33 1/2] sdhci: tegra: Implement Tegra specific set_timeout callback Date: Wed, 22 Apr 2020 09:32:28 -0700 Message-ID: <1587573149-30269-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587573149-30269-1-git-send-email-skomatineni@nvidia.com> References: <1587573149-30269-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587573090; bh=kYhxxXI3LV4oeArlKvtdIWzgGCgrp9TkYQa4roEyFZw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ZIBBWpNS8T3rNedF9IGJF+a/2IIHbW8Pk/EMmgsdH3W0/TGaJmJkHzZaFBDRlqWnY M5U4vPtx2NFS2sIG4IeRR4G8yJXB0JiXjnT5oxUhdXyvJqIUOz8dHfIrVk5o9py3PI KDzaJeKDg36SP8qbvSIq4lXIQiLhCM5AdxVsD/047/EadO525wt5o6TOVk28G66y9v 9DkqOHkSmFr3XI5TDNOJfJdS6/WeMhV5Jx5wAbA4swlL6GznfdpfVPXdM4/m8ZiXTz c4lpOBJ8QdX/tScB8o3lPUyPCiMLmH/VXVAyXdO7A0NvGS0Oulr8zetdpiwtrFHV6+ S8nlIY+FnGaeQ== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org commit 5e958e4aacf4 ("sdhci: tegra: Implement Tegra specific set_timeout callback") Tegra host supports HW busy detection and timeouts based on the count programmed in SDHCI_TIMEOUT_CONTROL register and max busy timeout it supports is 11s in finite busy wait mode. Some operations like SLEEP_AWAKE, ERASE and flush cache through SWITCH commands take longer than 11s and Tegra host supports infinite HW busy wait mode where HW waits forever till the card is busy without HW timeout. This patch implements Tegra specific set_timeout sdhci_ops to allow switching between finite and infinite HW busy detection wait modes based on the device command expected operation time. Cc: Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a25c3a4..fa8f6a4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -45,6 +45,7 @@ #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 +#define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 @@ -1227,6 +1228,34 @@ static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) return 0; } +static void tegra_sdhci_set_timeout(struct sdhci_host *host, + struct mmc_command *cmd) +{ + u32 val; + + /* + * HW busy detection timeout is based on programmed data timeout + * counter and maximum supported timeout is 11s which may not be + * enough for long operations like cache flush, sleep awake, erase. + * + * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows + * host controller to wait for busy state until the card is busy + * without HW timeout. + * + * So, use infinite busy wait mode for operations that may take + * more than maximum HW busy timeout of 11s otherwise use finite + * busy wait mode. + */ + val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); + if (cmd && cmd->busy_timeout >= 11 * HZ) + val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; + else + val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; + sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); + + __sdhci_set_timeout(host, cmd); +} + static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { .write_l = tegra_cqhci_writel, .enable = sdhci_tegra_cqe_enable, @@ -1366,6 +1395,7 @@ static const struct sdhci_ops tegra210_sdhci_ops = { .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, .voltage_switch = tegra_sdhci_voltage_switch, .get_max_clock = tegra_sdhci_get_max_clock, + .set_timeout = tegra_sdhci_set_timeout, }; static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { @@ -1403,6 +1433,7 @@ static const struct sdhci_ops tegra186_sdhci_ops = { .voltage_switch = tegra_sdhci_voltage_switch, .get_max_clock = tegra_sdhci_get_max_clock, .irq = sdhci_tegra_cqhci_irq, + .set_timeout = tegra_sdhci_set_timeout, }; static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { From patchwork Wed Apr 22 16:32:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11504247 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D1A80912 for ; Wed, 22 Apr 2020 16:32:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7C0121473 for ; Wed, 22 Apr 2020 16:32:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Q+aOwso/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726750AbgDVQcf (ORCPT ); Wed, 22 Apr 2020 12:32:35 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:3302 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726105AbgDVQce (ORCPT ); Wed, 22 Apr 2020 12:32:34 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 22 Apr 2020 09:32:21 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 22 Apr 2020 09:32:33 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 22 Apr 2020 09:32:33 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 22 Apr 2020 16:32:33 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 22 Apr 2020 16:32:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 22 Apr 2020 09:32:33 -0700 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , Subject: [PATCH 5.4.33 2/2] sdhci: tegra: Enable MMC_CAP_WAIT_WHILE_BUSY host capability Date: Wed, 22 Apr 2020 09:32:29 -0700 Message-ID: <1587573149-30269-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587573149-30269-1-git-send-email-skomatineni@nvidia.com> References: <1587573149-30269-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587573141; bh=AI2k/GeOJka+x5ydpwPpmWF5ssDecgtebTTmy/odja0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Q+aOwso//9q/gPBeXksB5egUqJegSFWCyFX80F1/NwPCodYcBTfoGSN3tUWNQUkjO /7r0YyeGW9fq1ELEX2gP7xtFWYilCBBbVc2Zl8gi8EuNZlg1+oqWhT/q9MfV5JzAvU EKJ0XUIP7RSjebfPEvrp++WkvtHMlJM4WiZr8zGzGKJW53xhM6++RFg17mdEDOSCOy JzJ/MTZDkKHjFGeCCUCbOV1GcLODeJotn8kMkqcOpsoTqbNusjucuOyOM89k5hPbtu fdYYGWm6UGHbpKkiOPfqn2KzhOd26Df0YzfpiQVkIMECH7LWkXdacFDqWk1DtxWYX7 Im5IHCYAZ0RoA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org commit ff124c31ccd7 ("sdhci: tegra: Enable MMC_CAP_WAIT_WHILE_BUSY host capability") Tegra sdhci host supports HW busy detection of the device busy signaling over data0 lane. So, this patch enables host capability MMC_CAP_wAIT_WHILE_BUSY. Cc: Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index fa8f6a4..1c381f8 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1580,6 +1580,8 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_parse_dt; + host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; + if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) host->mmc->caps |= MMC_CAP_1_8V_DDR;