From patchwork Thu Apr 23 07:23:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11505133 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 27E491392 for ; Thu, 23 Apr 2020 07:23:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10A61215A4 for ; Thu, 23 Apr 2020 07:23:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="gTXDOuQG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726576AbgDWHXs (ORCPT ); Thu, 23 Apr 2020 03:23:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbgDWHXs (ORCPT ); Thu, 23 Apr 2020 03:23:48 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22386C03C1AB for ; Thu, 23 Apr 2020 00:23:48 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id u127so5386346wmg.1 for ; Thu, 23 Apr 2020 00:23:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R3THRl3KgnbLuD68f3CjfeAS6X01pZTMWvpwEQpO/84=; b=gTXDOuQGgDIW37QUoud9nCFARAGDbYsmzD4aPH2j+I0F7omVFghkWJLvocqNWFPhI7 //cg/jL9NIg88quvfhtY+/X6UvVaFeyoXQFVYaPVjv94b6FEelTLfHmFyPkeIJdpzZST R3ieepgmqe8SCPe6bc8VPkgqBw50RtORM15Ag= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R3THRl3KgnbLuD68f3CjfeAS6X01pZTMWvpwEQpO/84=; b=m3JlTynY15KXHj0pSmYlJf1Ge3azAb/X80KXXe3bvzenbYwdZ/WmlWeXIlB0MHz01K fc+fv1ZVeEbRf1RM0zhmSbII/50kkv4buurVCiNIWxRsln3Nn8RQLWyMfTTLJqOutq3i zjJf1igADuesvLWCq9G9gF4Vf3jCNoUSiq9TN3UC2r2jfwXDd5HVZ9HkJDdOrhbc92Uq A3iGsvcSFnl3fkqVXDmsfVpiAHFVErf2wKoQszxN5NuGgtCdv131oW9nUqX0PhOhUf38 GAYS21XRktJ8/8vHk8qgbCeOc72N+7J/JfM5QkQKhur3E+Akz7RWo2rwd8zaRD+ooO4X qvlw== X-Gm-Message-State: AGi0PuaN8i92ryCOlfFjteijv5hRsViy7Py/UKKdN3sFqAYpZ6Ma/Kzx gHg93//YFSDwX4kwoTZvtwpYQtwTKTnyejk25f/nagqvqna0aA9ICSLO/YXBRnREzQ0EtE7/rGV N8a+C/AX3XpNqtJemqHsIMO5C2CBV9Ml02+4pbvvEj/9PN9a9551cNt6xN0UTS+D9q00TqciIwx sSxfl4IB//WBZhdldOBgkT X-Google-Smtp-Source: APiQypJ1JylOvNw6VoiyrPIPY+/3JAcogUqnne+M6LQqtgDgFF6TN7m0BZvxBM1fadMOw/OHwrj8Iw== X-Received: by 2002:a7b:cdf7:: with SMTP id p23mr2643328wmj.33.1587626626296; Thu, 23 Apr 2020 00:23:46 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id l4sm2336130wrw.25.2020.04.23.00.23.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Apr 2020 00:23:45 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu , Christoph Hellwig Subject: [v2 1/5] mpt3sas: don't change the dma coherent mask after allocations Date: Thu, 23 Apr 2020 03:23:12 -0400 Message-Id: <1587626596-1044-2-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Christoph Hellwig The DMA layer does not allow changing the DMA coherent mask after there are outstanding allocations. Reported-by: Abdul Haleem Signed-off-by: Christoph Hellwig Signed-off-by: Suganath Prabu --- v2: Initial patch was always setting dma coherent mask to 32 bit, now dma coherent mask is setting to either 32 bit or 63/64 bit based on controller capability. drivers/scsi/mpt3sas/mpt3sas_base.c | 67 +++++++++++-------------------------- drivers/scsi/mpt3sas/mpt3sas_base.h | 2 -- 2 files changed, 19 insertions(+), 50 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 663782b..b8679c2 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2806,58 +2806,38 @@ _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, static int _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) { - u64 required_mask, coherent_mask; struct sysinfo s; - /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ - int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64; - - if (ioc->is_mcpu_endpoint) - goto try_32bit; + int dma_mask; - required_mask = dma_get_required_mask(&pdev->dev); - if (sizeof(dma_addr_t) == 4 || required_mask == 32) - goto try_32bit; - - if (ioc->dma_mask) - coherent_mask = DMA_BIT_MASK(dma_mask); + if (ioc->is_mcpu_endpoint || + sizeof(dma_addr_t) == 4 || + dma_get_required_mask(&pdev->dev) <= 32) + dma_mask = 32; + /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ + else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) + dma_mask = 63; else - coherent_mask = DMA_BIT_MASK(32); + dma_mask = 64; if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) || - dma_set_coherent_mask(&pdev->dev, coherent_mask)) - goto try_32bit; - - ioc->base_add_sg_single = &_base_add_sg_single_64; - ioc->sge_size = sizeof(Mpi2SGESimple64_t); - ioc->dma_mask = dma_mask; - goto out; - - try_32bit: - if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(dma_mask))) return -ENODEV; - ioc->base_add_sg_single = &_base_add_sg_single_32; - ioc->sge_size = sizeof(Mpi2SGESimple32_t); - ioc->dma_mask = 32; - out: + if (dma_mask > 32) { + ioc->base_add_sg_single = &_base_add_sg_single_64; + ioc->sge_size = sizeof(Mpi2SGESimple64_t); + } else { + ioc->base_add_sg_single = &_base_add_sg_single_32; + ioc->sge_size = sizeof(Mpi2SGESimple32_t); + } + si_meminfo(&s); ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", - ioc->dma_mask, convert_to_kb(s.totalram)); + dma_mask, convert_to_kb(s.totalram)); return 0; } -static int -_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, - struct pci_dev *pdev) -{ - if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) { - if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) - return -ENODEV; - } - return 0; -} - /** * _base_check_enable_msix - checks MSIX capabable. * @ioc: per adapter object @@ -5169,14 +5149,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) total_sz += sz; } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); - if (ioc->dma_mask > 32) { - if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { - ioc_warn(ioc, "no suitable consistent DMA mask for %s\n", - pci_name(ioc->pdev)); - goto out; - } - } - ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; @@ -7158,7 +7130,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) ioc->smp_affinity_enable = smp_affinity_enable; ioc->rdpq_array_enable_assigned = 0; - ioc->dma_mask = 0; if (ioc->is_aero_ioc) ioc->base_readl = &_base_readl_aero; else diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index e719715..caae040 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -1026,7 +1026,6 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc); * @ir_firmware: IR firmware present * @bars: bitmask of BAR's that must be configured * @mask_interrupts: ignore interrupt - * @dma_mask: used to set the consistent dma mask * @pci_access_mutex: Mutex to synchronize ioctl, sysfs show path and * pci resource handling * @fault_reset_work_q_name: fw fault work queue @@ -1205,7 +1204,6 @@ struct MPT3SAS_ADAPTER { u8 ir_firmware; int bars; u8 mask_interrupts; - int dma_mask; /* fw fault handler */ char fault_reset_work_q_name[20]; From patchwork Thu Apr 23 07:23:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11505135 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BCA3A1392 for ; Thu, 23 Apr 2020 07:23:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A41A420736 for ; Thu, 23 Apr 2020 07:23:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="R9jsRlRy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726819AbgDWHXv (ORCPT ); Thu, 23 Apr 2020 03:23:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbgDWHXv (ORCPT ); Thu, 23 Apr 2020 03:23:51 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C54C8C03C1AB for ; Thu, 23 Apr 2020 00:23:50 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id t63so5233194wmt.3 for ; Thu, 23 Apr 2020 00:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=np3nzB74b6mNE2OsMR/DOSPMVbD8D/J0W6kdkLETr38=; b=R9jsRlRy7xiNEIispPtUzwY7RFwnG+Df5wAFe9GiEMgQREE7sYWCIBo74osYJLhkpu r21sx7JqeSFWZ2bKSOBJw3tQ0+SCKo+i+FINDG4wuLzb3HNgrEeN7jSG2O1wnWwLEpdL kxdB/LXUzP1Ry5OGJKc6Qv/1wWHA9Z9Q6Lr1k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=np3nzB74b6mNE2OsMR/DOSPMVbD8D/J0W6kdkLETr38=; b=MCh+nrlvwtFOW/BoYy88VBoisBIi9RZQo7U4drG3cKE2hS9xz2dwVwRrRs2cDMsNK6 iETJ1LQevAFbiiOYEr/yiQ/OHzHm8dNizQN9wO7INlvP/crtNWCZw6KutD/kDzQuY1Mm gsMPSMR1NYDuISueIW+sS/jKHnVvoPOwoC2GuPt/mc9aY9KsN0BO/YO7aNmwML+71akC FN9tHsgn/eUK0VSDlhCWuTlEN+UspA/FnACPb6IwgOKYDO5TMvcfO/O+bAgFioazZmSk K2vagBnBxXbAKCiCM68nNBSlmhPoayvEGILBs99DZYOe+mTFgftMfaNJwcV0+/nRAGNW 7mxw== X-Gm-Message-State: AGi0Puaj1QKsEwu/dKzD5hCJjjVIjdrlHex9iWF36GJjHLEga8LlCGg4 P7DVEp4+OHawkWFdxSemR7j5SUC8zclVf13G5wbRYQ2GWZt5adwWwf22C5pNFQWrHpDB1b4Oj9g iLa4idQoZwkrXv3SJRskqr/v/cgp0XKUjTQecp7r1SQhOsfAxW4aSAL5wWjx4jT3SOGr0rAgxN6 /SsoT/KANiecLiiP+SZtxB X-Google-Smtp-Source: APiQypIuIKLxGI5PjHwslKQbGnoQLKe3Nu5WnPLYnJwfjhBdyXno9tHrSzB9yQshVzly8OyOsGtsRA== X-Received: by 2002:a1c:7d04:: with SMTP id y4mr2556228wmc.10.1587626629119; Thu, 23 Apr 2020 00:23:49 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id l4sm2336130wrw.25.2020.04.23.00.23.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Apr 2020 00:23:48 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu Subject: [v2 2/5] mpt3sas: Rename function name is_MSB_are_same Date: Thu, 23 Apr 2020 03:23:13 -0400 Message-Id: <1587626596-1044-3-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Rename is_MSB_are_same() to mpt3sas_check_same_4gb_region() for better readability. Signed-off-by: Suganath Prabu Reviewed-by: Christoph Hellwig --- drivers/scsi/mpt3sas/mpt3sas_base.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index b8679c2..f98c7f6 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4915,7 +4915,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) } /** - * is_MSB_are_same - checks whether all reply queues in a set are + * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are * having same upper 32bits in their base memory address. * @reply_pool_start_address: Base address of a reply queue set * @pool_sz: Size of single Reply Descriptor Post Queues pool size @@ -4925,7 +4925,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) */ static int -is_MSB_are_same(long reply_pool_start_address, u32 pool_sz) +mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) { long reply_pool_end_address; @@ -5377,7 +5377,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) * Actual requirement is not alignment, but we need start and end of * DMA address must have same upper 32 bit address. */ - if (!is_MSB_are_same((long)ioc->sense, sz)) { + if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) { //Release Sense pool & Reallocate dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); dma_pool_destroy(ioc->sense_dma_pool); From patchwork Thu Apr 23 07:23:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11505137 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 83F3C1392 for ; Thu, 23 Apr 2020 07:23:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C854215A4 for ; Thu, 23 Apr 2020 07:23:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="BiuKwomK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726834AbgDWHXy (ORCPT ); Thu, 23 Apr 2020 03:23:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbgDWHXx (ORCPT ); Thu, 23 Apr 2020 03:23:53 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91F87C03C1AB for ; Thu, 23 Apr 2020 00:23:53 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id k1so5563207wrx.4 for ; Thu, 23 Apr 2020 00:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lG2q/QVtnvqMp4mcm6tsbyphrWNYMrYVz4nqzr6vz2Q=; b=BiuKwomKvsPSS6HeRgk3ySQ52wPr04Tnon/4ypUoMNISXYbNXZb0yghNPbGsXA4Kcd FaQ5XAyrbzYX1v6mKZfQdpfsnlVaS3gHnIB8qaJr48Mnl3wQ+eKY3ai0wvV418KODdO0 x5lTW6gn4VAnsUWGLsfCj67sNV2IOe7/rJDfQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lG2q/QVtnvqMp4mcm6tsbyphrWNYMrYVz4nqzr6vz2Q=; b=MSMX/YtcwVMFcsYmi7JTSQztBU8MGZ41KdXRxOxQppFl10EdCqR9O2RSIwrRtfOEiE A/WWRneUtfJ+/ayuMk+PWdfwf264Z7nPTx+hpe1zARcXYRjVAVv1PktzCg56qaHH2Zkj HsfYhBbll4yz+luTlYwWj4S9BFQ5RFpAGB/gtnsZMT+tkkqpBiV025DiN28CDXdxdNAg w57ehUAncPP/62GKlXTQJT9c9Gsq4edHG0I3hZvHRK6tbR4S5CJM0kYuLXNKE9i3T7o2 akrJqq1pQZe2iagFx5O16NXSi64V1DUALXipOdZEPK2xQ8dj59Ic7EkIbw7NYqcfB8nT qfng== X-Gm-Message-State: AGi0PuZDYdIC1DdmCmNJG7QXjtbIBn+AXzo2pr4MZNOL5rF9XXQEisPY 8TTYauAvKZKBdlEzh0utoDfDuuTXc61mcBs7nARqhgbQCZhVLUFEtoQXeuFLaGmHa9xxOo4KWdD O1LMAcaJf8L5CNOo9Sqa0EqR6OC4TfP5hDmuCIFUIpduOj+6/+qYiqWjMg/xq2jSY3Q0O6xKSZu bD5AXdg5YAoSyKYnsmzzL6 X-Google-Smtp-Source: APiQypLTmWyElN7lS8w4J0cja8/fZ1pGtjEwabDJX0/Toalf92yqIOYr13QXzbf1FMLHJ8h2206Rbg== X-Received: by 2002:adf:f0cb:: with SMTP id x11mr3330874wro.266.1587626631908; Thu, 23 Apr 2020 00:23:51 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id l4sm2336130wrw.25.2020.04.23.00.23.49 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Apr 2020 00:23:51 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu Subject: [v2 3/5] mpt3sas: Separate out RDPQ allocation to new function. Date: Thu, 23 Apr 2020 03:23:14 -0400 Message-Id: <1587626596-1044-4-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org For readability separate out RDPQ allocations to new function base_alloc_rdpq_dma_pool(). Signed-off-by: Suganath Prabu Reviewed-by: Christoph Hellwig --- drivers/scsi/mpt3sas/mpt3sas_base.c | 79 +++++++++++++++++++++---------------- 1 file changed, 45 insertions(+), 34 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index f98c7f6..0588941 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4939,6 +4939,49 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) } /** + * base_alloc_rdpq_dma_pool - Allocating DMA'able memory + * for reply queues. + * @ioc: per adapter object + * @sz: DMA Pool size + * Return: 0 for success, non-zero for failure. + */ +static int +base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) +{ + int i; + int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; + + ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct), + GFP_KERNEL); + if (!ioc->reply_post) + return -ENOMEM; + ioc->reply_post_free_dma_pool = + dma_pool_create("reply_post_free pool", + &ioc->pdev->dev, sz, 16, 0); + if (!ioc->reply_post_free_dma_pool) + return -ENOMEM; + i = 0; + do { + ioc->reply_post[i].reply_post_free = + dma_pool_zalloc(ioc->reply_post_free_dma_pool, + GFP_KERNEL, + &ioc->reply_post[i].reply_post_free_dma); + if (!ioc->reply_post[i].reply_post_free) + return -ENOMEM; + dinitprintk(ioc, + ioc_info(ioc, "reply post free pool (0x%p): depth(%d)," + "element_size(%d), pool_size(%d kB)\n", + ioc->reply_post[i].reply_post_free, + ioc->reply_post_queue_depth, 8, sz / 1024)); + dinitprintk(ioc, + ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", + (u64)ioc->reply_post[i].reply_post_free_dma)); + + } while (ioc->rdpq_array_enable && ++i < ioc->reply_queue_count); + return 0; +} + +/** * _base_allocate_memory_pools - allocate start of day memory pools * @ioc: per adapter object * @@ -5113,41 +5156,9 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) sz = reply_post_free_sz; if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) sz *= ioc->reply_queue_count; - - ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? - (ioc->reply_queue_count):1, - sizeof(struct reply_post_struct), GFP_KERNEL); - - if (!ioc->reply_post) { - ioc_err(ioc, "reply_post_free pool: kcalloc failed\n"); + if (base_alloc_rdpq_dma_pool(ioc, sz)) goto out; - } - ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", - &ioc->pdev->dev, sz, 16, 0); - if (!ioc->reply_post_free_dma_pool) { - ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n"); - goto out; - } - i = 0; - do { - ioc->reply_post[i].reply_post_free = - dma_pool_zalloc(ioc->reply_post_free_dma_pool, - GFP_KERNEL, - &ioc->reply_post[i].reply_post_free_dma); - if (!ioc->reply_post[i].reply_post_free) { - ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n"); - goto out; - } - dinitprintk(ioc, - ioc_info(ioc, "reply post free pool (0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", - ioc->reply_post[i].reply_post_free, - ioc->reply_post_queue_depth, - 8, sz / 1024)); - dinitprintk(ioc, - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", - (u64)ioc->reply_post[i].reply_post_free_dma)); - total_sz += sz; - } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); + total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count); ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; From patchwork Thu Apr 23 07:23:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11505139 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 772581667 for ; Thu, 23 Apr 2020 07:23:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C42121582 for ; Thu, 23 Apr 2020 07:23:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="NGtgD+85" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726849AbgDWHX5 (ORCPT ); Thu, 23 Apr 2020 03:23:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbgDWHX4 (ORCPT ); Thu, 23 Apr 2020 03:23:56 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E7B6C03C1AB for ; Thu, 23 Apr 2020 00:23:56 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id i10so5532326wrv.10 for ; Thu, 23 Apr 2020 00:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=71d2BUe+VSk8JTME6IGpGQkmFtDmt3GICZG+udoKs2w=; b=NGtgD+850+uaTbYZxKPm4itiX5i/sTAuuc+N8oOisH7yXUN2J6KohoY8KMuyG7MprM 0+Tb3GkgFJOInM9EhaQRPWX3kbHlA06V9KQ95rhV/yrHzfWA+j+lBg3RkVFlPV9IUKAx 4tbny/32i73HfE0UyN+q3jJxoteJIH5PHqOnU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=71d2BUe+VSk8JTME6IGpGQkmFtDmt3GICZG+udoKs2w=; b=NLmdC8iS/nmMSDG0DY8nw3q40/UdKbbUgizY6Y/p6VWTLCYnA++0v3BoK3S6rAjSZq kGk1O1WP9hlqdQ1oEDZM3kvhFfxYPfb/L+Qu03FN2SX+K1LUvJfoJisUnv+JsWj8Yhmo KHxjV9NZHXtyEeXZ/1AXTecP4vaHK30LJ7f7RgQqW/9PfRMLE/Ft+PPI6JSl6/QIuG2o YA9qwEyuq+xEYkAcImaMC2ZgTqXe7j+iUDzsj5QAao0cAVnwZ3RPANKwhyVtHHJTHFsO qkX2911w9e3HL7kyF2DyK8OKZBFbRWlRvagm15NUhGbO3YbJBjmMCLU6p6uqWtDEPDVE 293Q== X-Gm-Message-State: AGi0PuYxDoNnmodNzD+CAlhkVJ4e5IuD8PFu+QykrCQdPo1x7U9nLYvP pGnJzyzOf77zbmZQ2EGIIA1eBtrxI9ecKlJsFHieQoP/8UG/bCvDBA5Cz8KOY4N7ELT78vE47ee jtTYLD8BCFVCwXlMnJe+IkVtWOvfXe+3T8HUthgVXlJsTvzj1iK0SmiQNJnJBXe0OKoHCI7VhMK DjrsKBDRuxoe7tKNfpcDiN X-Google-Smtp-Source: APiQypJTM53HgZktrDdaj0RtR2dYb1KHnUXpaWuuNb7pbVsCTFVzdTNjsf63QtkdbIs3wqh4whzNvw== X-Received: by 2002:adf:e552:: with SMTP id z18mr3236515wrm.244.1587626634490; Thu, 23 Apr 2020 00:23:54 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id l4sm2336130wrw.25.2020.04.23.00.23.52 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Apr 2020 00:23:54 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu Subject: [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region Date: Thu, 23 Apr 2020 03:23:15 -0400 Message-Id: <1587626596-1044-5-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org For INVADER_SERIES each set of 8 reply queues (0 - 7, 8 - 15,..) and VENTURA_SERIES each set of 16 reply queues (0 - 15, 16 - 31,..) should be within 4 GB boundary. Driver uses limitation of VENTURA_SERIES to manage INVADER_SERIES as well. So here driver is allocating the DMA able memory for RDPQ's accordingly. 1) At driver load, set DMA Mask to 64 and allocate memory for RDPQ's. 2) Check if allocated resources for RDPQ are in the same 4GB range. 3) If #2 is true, continue with 64 bit DMA and go to #6 4) If #2 is false, then free all the resources from #1. 5) Set DMA mask to 32 and allocate RDPQ's. 6) Proceed with driver loading and other allocations Reviewed-by: Christoph Hellwig --- v1 Change log: 1) Use one dma pool for RDPQ's, thus removes the logic of using second dma pool with align. v2 Change log: Added flag use_32bit_dma. If this flag is true, 32 bit coharent dma is used. Signed-off-by: Suganath Prabu Reviewed-by: Christoph Hellwig --- drivers/scsi/mpt3sas/mpt3sas_base.c | 152 +++++++++++++++++++++++++----------- drivers/scsi/mpt3sas/mpt3sas_base.h | 3 + 2 files changed, 109 insertions(+), 46 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 0588941..af30e74 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2810,7 +2810,7 @@ _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) int dma_mask; if (ioc->is_mcpu_endpoint || - sizeof(dma_addr_t) == 4 || + sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma || dma_get_required_mask(&pdev->dev) <= 32) dma_mask = 32; /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ @@ -4807,8 +4807,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) { int i = 0; int j = 0; + int dma_alloc_count = 0; struct chain_tracker *ct; - struct reply_post_struct *rps; dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); @@ -4850,29 +4850,34 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) } if (ioc->reply_post) { - do { - rps = &ioc->reply_post[i]; - if (rps->reply_post_free) { - dma_pool_free( - ioc->reply_post_free_dma_pool, - rps->reply_post_free, - rps->reply_post_free_dma); - dexitprintk(ioc, - ioc_info(ioc, "reply_post_free_pool(0x%p): free\n", - rps->reply_post_free)); - rps->reply_post_free = NULL; + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count, + RDPQ_MAX_INDEX_IN_ONE_CHUNK); + for (i = 0; i < ioc->reply_queue_count; i++) { + if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0 + && dma_alloc_count) { + if (ioc->reply_post[i].reply_post_free) { + dma_pool_free( + ioc->reply_post_free_dma_pool, + ioc->reply_post[i].reply_post_free, + ioc->reply_post[i].reply_post_free_dma); + dexitprintk(ioc, ioc_info(ioc, + "reply_post_free_pool(0x%p): free\n", + ioc->reply_post[i].reply_post_free)); + ioc->reply_post[i].reply_post_free = + NULL; + } + --dma_alloc_count; } - } while (ioc->rdpq_array_enable && - (++i < ioc->reply_queue_count)); + } + dma_pool_destroy(ioc->reply_post_free_dma_pool); if (ioc->reply_post_free_array && ioc->rdpq_array_enable) { dma_pool_free(ioc->reply_post_free_array_dma_pool, - ioc->reply_post_free_array, - ioc->reply_post_free_array_dma); + ioc->reply_post_free_array, + ioc->reply_post_free_array_dma); ioc->reply_post_free_array = NULL; } dma_pool_destroy(ioc->reply_post_free_array_dma_pool); - dma_pool_destroy(ioc->reply_post_free_dma_pool); kfree(ioc->reply_post); } @@ -4948,36 +4953,75 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) static int base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) { - int i; + int i = 0; + u32 dma_alloc_count = 0; + int reply_post_free_sz = ioc->reply_post_queue_depth * + sizeof(Mpi2DefaultReplyDescriptor_t); int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct), GFP_KERNEL); if (!ioc->reply_post) return -ENOMEM; + /* + * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and + * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should + * be within 4GB boundary i.e reply queues in a set must have same + * upper 32-bits in their memory address. so here driver is allocating + * the DMA'able memory for reply queues according. + * Driver uses limitation of + * VENTURA_SERIES to manage INVADER_SERIES as well. + */ + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count, + RDPQ_MAX_INDEX_IN_ONE_CHUNK); ioc->reply_post_free_dma_pool = - dma_pool_create("reply_post_free pool", - &ioc->pdev->dev, sz, 16, 0); + dma_pool_create("reply_post_free pool", + &ioc->pdev->dev, sz, 16, 0); if (!ioc->reply_post_free_dma_pool) return -ENOMEM; - i = 0; - do { - ioc->reply_post[i].reply_post_free = - dma_pool_zalloc(ioc->reply_post_free_dma_pool, - GFP_KERNEL, - &ioc->reply_post[i].reply_post_free_dma); - if (!ioc->reply_post[i].reply_post_free) - return -ENOMEM; - dinitprintk(ioc, - ioc_info(ioc, "reply post free pool (0x%p): depth(%d)," - "element_size(%d), pool_size(%d kB)\n", - ioc->reply_post[i].reply_post_free, - ioc->reply_post_queue_depth, 8, sz / 1024)); - dinitprintk(ioc, - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", - (u64)ioc->reply_post[i].reply_post_free_dma)); + for (i = 0; i < ioc->reply_queue_count; i++) { + if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) { + ioc->reply_post[i].reply_post_free = + dma_pool_alloc(ioc->reply_post_free_dma_pool, + GFP_KERNEL, + &ioc->reply_post[i].reply_post_free_dma); + if (!ioc->reply_post[i].reply_post_free) + return -ENOMEM; + /* + * Each set of RDPQ pool must satisfy 4gb boundary + * restriction. + * 1) Check if allocated resources for RDPQ pool are in + * the same 4GB range. + * 2) If #1 is true, continue with 64 bit DMA. + * 3) If #1 is false, return 1. which means free all the + * resources and set DMA mask to 32 and allocate. + */ + if (!mpt3sas_check_same_4gb_region( + (long)ioc->reply_post[i].reply_post_free, sz)) { + dinitprintk(ioc, + ioc_err(ioc, "bad Replypost free pool(0x%p)" + "reply_post_free_dma = (0x%llx)\n", + ioc->reply_post[i].reply_post_free, + (unsigned long long) + ioc->reply_post[i].reply_post_free_dma)); + return -EAGAIN; + } + memset(ioc->reply_post[i].reply_post_free, 0, + RDPQ_MAX_INDEX_IN_ONE_CHUNK * + reply_post_free_sz); + dma_alloc_count--; - } while (ioc->rdpq_array_enable && ++i < ioc->reply_queue_count); + } else { + ioc->reply_post[i].reply_post_free = + (Mpi2ReplyDescriptorsUnion_t *) + ((long)ioc->reply_post[i-1].reply_post_free + + reply_post_free_sz); + ioc->reply_post[i].reply_post_free_dma = + (dma_addr_t) + (ioc->reply_post[i-1].reply_post_free_dma + + reply_post_free_sz); + } + } return 0; } @@ -4995,10 +5039,12 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) u16 chains_needed_per_io; u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; u32 retry_sz; + u32 rdpq_sz = 0; u16 max_request_credit, nvme_blocks_needed; unsigned short sg_tablesize; u16 sge_size; int i, j; + int ret = 0; struct chain_tracker *ct; dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); @@ -5152,14 +5198,28 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) /* reply post queue, 16 byte align */ reply_post_free_sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t); - - sz = reply_post_free_sz; + rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK; if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) - sz *= ioc->reply_queue_count; - if (base_alloc_rdpq_dma_pool(ioc, sz)) - goto out; - total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count); - + rdpq_sz = reply_post_free_sz * ioc->reply_queue_count; + ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz); + if (ret == -EAGAIN) { + /* + * Free allocated bad RDPQ memory pools. + * Change dma coherent mask to 32 bit and reallocate RDPQ + */ + _base_release_memory_pools(ioc); + ioc->use_32bit_dma = true; + if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { + ioc_err(ioc, + "32 DMA mask failed %s\n", pci_name(ioc->pdev)); + return -ENODEV; + } + if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz)) + return -ENOMEM; + } else if (ret == -ENOMEM) + return -ENOMEM; + total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 : + DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK)); ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; @@ -5171,7 +5231,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc_info(ioc, "scsi host: can_queue depth (%d)\n", ioc->shost->can_queue)); - /* contiguous pool for request and chains, 16 byte align, one extra " * "frame for smid=0 */ @@ -7141,6 +7200,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) ioc->smp_affinity_enable = smp_affinity_enable; ioc->rdpq_array_enable_assigned = 0; + ioc->use_32bit_dma = 0; if (ioc->is_aero_ioc) ioc->base_readl = &_base_readl_aero; else diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index caae040..5a83971 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -367,6 +367,7 @@ struct mpt3sas_nvme_cmd { #define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8 #define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16 #define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128 +#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16 /* OEM Specific Flags will come from OEM specific header files */ struct Mpi2ManufacturingPage10_t { @@ -1063,6 +1064,7 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc); * @thresh_hold: Max number of reply descriptors processed * before updating Host Index * @drv_support_bitmap: driver's supported feature bit map + * @use_32bit_dma: Flag to use 32 bit consistent dma mask * @scsi_io_cb_idx: shost generated commands * @tm_cb_idx: task management commands * @scsih_cb_idx: scsih internal commands @@ -1252,6 +1254,7 @@ struct MPT3SAS_ADAPTER { u8 high_iops_queues; u32 drv_support_bitmap; bool enable_sdev_max_qd; + bool use_32bit_dma; /* internal commands, callback index */ u8 scsi_io_cb_idx; From patchwork Thu Apr 23 07:23:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11505141 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1D741392 for ; Thu, 23 Apr 2020 07:23:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA6CA21582 for ; Thu, 23 Apr 2020 07:23:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="fvVAb2HI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726904AbgDWHX7 (ORCPT ); Thu, 23 Apr 2020 03:23:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbgDWHX7 (ORCPT ); Thu, 23 Apr 2020 03:23:59 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0320C03C1AB for ; Thu, 23 Apr 2020 00:23:58 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id d17so5523116wrg.11 for ; Thu, 23 Apr 2020 00:23:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WeErXdmvBpS/99pytbGEcH6lwN0v1sHycZ3XqJLGIkw=; b=fvVAb2HItGwOPQFS4Qs6pQpxtI2xQh9RjZFISbTsWDEr8u9TcwFE8jwoYVChwewZnL KAGRKmMcuW7UhsA8LpDI6cx7epx5C5Ff6Mfi6V0OWlJxxO697qa5FdXuWIUXvCNET0x2 axY2hnO6ztPL31dAktMkUnEC0Bntw5zdF1epo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WeErXdmvBpS/99pytbGEcH6lwN0v1sHycZ3XqJLGIkw=; b=Bk+u2dwcEbSfFpSGUKwEey8+pEMRRUBIIadCBpAa2fIasgWYOiXfqvUqbm01e32Guj Uly6JQT9cV3cKDJEwiOKzjACwNYmqG2E2pafE2mKJAugBrmwex8vTP+T5/L+MfJS8gQ6 BDO9X8p7lE5c/VoGKc1Akf6zPSjGr54uogDumJYnQ+ePoLmEgq4JPrTVrpsoSAFDTfDN UPzh8x9F/9ykzqZXaUvaCGtNc84hszACum6fTI5o6+C9f7o10/YB6+pnWDb13tCV127a LpZJS7jXcdkFQIr6sdOJSiUaQeyCYkVo5SLMJocMOgxmYjJEET1kksayYVDNelvs4EMR 4SQw== X-Gm-Message-State: AGi0Pua691G0u/VwJ9oKBqv4MXAl1EfvqQ1mvcwZ3HvPOhJcle9uWW2k 6ahu9xtlRpF0YNOSjwTkRowdZNqsyVxMR0p2xwyTZ0v1HYlJ+v94+sJIe30KiQbpKK5h6q7bToW abpkI/FNBc++uyg+12y6EdWbx11gi3vkxiu26y0R9LH1E1OkVikNKqIXEq4Whca8pxhBI0IJyrp u9H1GjbJPBW7CQH9t2YZbG X-Google-Smtp-Source: APiQypIpg8X/M6aEojjbe/jRMTFII57Whu86TpryRoB51Xqz4TkcyTScv8lHawXLlEtSvQhsm9agAA== X-Received: by 2002:a5d:4702:: with SMTP id y2mr3234771wrq.15.1587626637220; Thu, 23 Apr 2020 00:23:57 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id l4sm2336130wrw.25.2020.04.23.00.23.54 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Apr 2020 00:23:56 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu Subject: [v2 5/5] mpt3sas: Update mpt3sas version to 33.101.00.00 Date: Thu, 23 Apr 2020 03:23:16 -0400 Message-Id: <1587626596-1044-6-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1587626596-1044-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Update mpt3sas driver version from 33.100.00.00 to 33.101.00.00 Signed-off-by: Suganath Prabu --- drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index 5a83971..c574379 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -76,9 +76,9 @@ #define MPT3SAS_DRIVER_NAME "mpt3sas" #define MPT3SAS_AUTHOR "Avago Technologies " #define MPT3SAS_DESCRIPTION "LSI MPT Fusion SAS 3.0 Device Driver" -#define MPT3SAS_DRIVER_VERSION "33.100.00.00" +#define MPT3SAS_DRIVER_VERSION "33.101.00.00" #define MPT3SAS_MAJOR_VERSION 33 -#define MPT3SAS_MINOR_VERSION 100 +#define MPT3SAS_MINOR_VERSION 101 #define MPT3SAS_BUILD_VERSION 0 #define MPT3SAS_RELEASE_VERSION 00