From patchwork Fri Apr 24 03:55:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11507015 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8A29913 for ; Fri, 24 Apr 2020 03:56:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C05B920776 for ; Fri, 24 Apr 2020 03:56:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="K9ofKEQj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726413AbgDXDzU (ORCPT ); Thu, 23 Apr 2020 23:55:20 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4605 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726364AbgDXDzT (ORCPT ); Thu, 23 Apr 2020 23:55:19 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:54:16 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:19 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Apr 2020 20:55:19 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:19 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:18 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Apr 2020 20:55:18 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 1/9] arm64: tegra: Fix sor powergate clocks and reset Date: Thu, 23 Apr 2020 20:55:05 -0700 Message-ID: <1587700513-28449-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700456; bh=PTc2SyRS9NP+68XdMh+c6cj6nLmKTNHZwxALx6dnzdM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=K9ofKEQjPdSxxcxucsmQiiOs6uPzCnyu/RYzv2Fyc4btmStIXjN735plZNX1FsQ3J 8ms81wzi60fZTglWnQdDdpWmGZ5Yk72UP/m40Fz3nyvx++4QokV6wLAjyPZefOmGqc DD3isBLtRRww0UWnwgZEhxSfQKnOJPF/j5i1OqHUImZ9NF1Js/Kgjndq6B5jkvy8rD pKiUnUVdc34I7JQU+UnJPKjIxBNmrLBJlhH1h/auR0PEFSRby6CB6YdRtHt+X+GZ5J n8dSs5IlA14+QUnWdtaEZTPK4XY5tqx4bNMIkyxPXeSsx59uBa8x6eMT+PO1/2w0nU AKKGrq6KZkk2A== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 device tree lists csi clock and reset under SOR powergate node. But Tegra210 has csicil in SOR partition and csi in VENC partition. So, this patch includes fix for sor powergate node. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 64c46ce..d0eff92 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -796,7 +796,9 @@ pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, @@ -804,7 +806,6 @@ <&tegra_car TEGRA210_CLK_MIPI_CAL>; resets = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, From patchwork Fri Apr 24 03:55:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11507011 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E29C5912 for ; Fri, 24 Apr 2020 03:56:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BFE5820857 for ; Fri, 24 Apr 2020 03:56:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="AsokAc8o" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726489AbgDXDzX (ORCPT ); Thu, 23 Apr 2020 23:55:23 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:10764 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726473AbgDXDzW (ORCPT ); Thu, 23 Apr 2020 23:55:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:53:24 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Apr 2020 20:55:21 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:21 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Apr 2020 20:55:20 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Date: Thu, 23 Apr 2020 20:55:07 -0700 Message-ID: <1587700513-28449-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700404; bh=Aw2TIrfzrAVXZOn1lDfsAGIvwrb7U15QVjnSRgzRbvc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=AsokAc8oTHwGnGdDwDHlGI0qfSZUcdQxWbHKrSCVhbGFdBGAu/kNQ+Z9Bq5MbrRmT mpX7XjmCKz8pWChqNy5b5D+zqeGhZtVzzXt3zc6KFXdymR8QcU425tvnehu8DqLojy UFWUa5xytTc6V9z9MI0QIdHkzVEvVUF8sqwk56MYSXZaJ7MHcUCGoBNjbQ6X8RDELR ZxtGSB6lg/TmqVStfKjiRMN6H85c9RBjJcFU914bCQ3QsmryQdUlOOAolYLr6D2S5d pdbQZPrwubWgnbAbaF+d+quLY/6HUouloD1W4Bf416R4msvoPLGIwGRO43+M+D505D ZfkC7YXZTRXCg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 uses PLLD out internally for CSI TPG. This patch adds clk id for this CSI TPG clock from PLLD. Acked-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra210-car.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b..d8909e0 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -351,7 +351,7 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ +#define TEGRA210_CLK_CSI_TPG 320 /* 321 */ #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 From patchwork Fri Apr 24 03:55:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11506983 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02706912 for ; Fri, 24 Apr 2020 03:55:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D43D720CC7 for ; Fri, 24 Apr 2020 03:55:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="F4UQ1v1b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726512AbgDXDzX (ORCPT ); Thu, 23 Apr 2020 23:55:23 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10171 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726364AbgDXDzX (ORCPT ); Thu, 23 Apr 2020 23:55:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:55:10 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Apr 2020 20:55:22 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:22 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:22 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Apr 2020 20:55:21 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Thu, 23 Apr 2020 20:55:08 -0700 Message-ID: <1587700513-28449-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700510; bh=/06MYnopqzjyrf2N0nRAUhGBnkcd6r/kBjlHyehzo9I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=F4UQ1v1bB3nYBGTUCsx8GYrB0gASzlutZmT3SyaKvYUGAiGxhboRhuWIVcVhoOak9 0mWFNjb2yTa166ojO9g5/n7vr8hlZpiiko/4oKOg3vO1cdKHgSUZWmBYCWMG5wln7i /8+NMNKVm2BS/1uYBO+Xce5pFfORGap2a3ScuEXFy75rpgckZJAwGZs4rX+m6Y4Ea1 2y4Iz5uCCybTGsDX/etuTyiROvbXKnA2YG9OF1V2yGp7oX6rO6GubjbydM7vedCV5f UuxB6/FZPKKCHQ7BQzMSXb5kLNMZ74lm4IWyyRmMi5SwECnjvGbboWI5+ctK5qhGmy yNm2kzVRAQxDA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index defe3b7..81a879b 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, From patchwork Fri Apr 24 03:55:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11507007 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3124B913 for ; Fri, 24 Apr 2020 03:56:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 08C4920776 for ; Fri, 24 Apr 2020 03:56:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="XjKjpNG6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726690AbgDXDz6 (ORCPT ); Thu, 23 Apr 2020 23:55:58 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4615 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726519AbgDXDzY (ORCPT ); Thu, 23 Apr 2020 23:55:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:54:20 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:23 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Apr 2020 20:55:23 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:23 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:23 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Apr 2020 20:55:23 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 5/9] dt-binding: tegra: Add VI and CSI bindings Date: Thu, 23 Apr 2020 20:55:09 -0700 Message-ID: <1587700513-28449-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700460; bh=c1+1RY3DNymVc+W/nvOMO+FEXi1aSIH/IA3CL9uJZY0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=XjKjpNG60JcWlgsuaFscjrkEBxDXrUUCwiYUgUwFSpMFrv3IgeyHZyy1rymEL8ec7 a2uRXoZS3d6XdGh8da1L9XZ3zr3WeumMu3pOCEbU4WkoaQFaKPglmO9TI17VDCCiRe 4RJm04MlogvgUTcFaxLbvq9AcgYCJU53HF1W4Y0sVTNho28/mXgsCR+P8mB60nbmxo RA2RXDAY5uKUGa4wt2J4Ec3wYJ6vDMHfIyVg1OYKrHwqU5AYuWs58xuCMQG6Q7O9JN Xktuk+40hrV3Q//VtNfo5EuO+AjvdnfwZIJOBiK1KHhuaYrwFJD7M89Exrdeke8IBl N8zFjJlrVGmNg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra contains VI controller which can support up to 6 MIPI CSI camera sensors. Each Tegra CSI port from CSI unit can be one-to-one mapper to VI channel and can capture from an external camera sensor or from built-in test pattern generator. This patch adds dt-bindings for Tegra VI and CSI. Acked-by: Thierry Reding Reviewed-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- .../display/tegra/nvidia,tegra20-host1x.txt | 73 ++++++++++++++++++---- 1 file changed, 60 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 9999255..4731921 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -40,14 +40,30 @@ of the following host1x client modules: Required properties: - compatible: "nvidia,tegra-vi" - - reg: Physical base address and length of the controller's registers. + - reg: Physical base address and length of the controller registers. - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. + - clocks: clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vi + - Tegra20/Tegra30/Tegra114/Tegra124: + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - vi + - Tegra210: + - power-domains: Must include venc powergate node as vi is in VE partition. + - Tegra210 has CSI part of VI sharing same host interface and register space. + So, VI device node should have CSI child node. + + - csi: mipi csi interface to vi + + Required properties: + - compatible: "nvidia,tegra210-csi" + - reg: Physical base address offset to parent and length of the controller + registers. + - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. + See ../clocks/clock-bindings.txt for details. + - power-domains: Must include sor powergate node as csicil is in + SOR partition. - epp: encoder pre-processor @@ -309,13 +325,44 @@ Example: reset-names = "mpe"; }; - vi { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 100>; - reset-names = "vi"; + vi@54080000 { + compatible = "nvidia,tegra210-vi"; + reg = <0x0 0x54080000 0x0 0x700>; + interrupts = ; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; epp { From patchwork Fri Apr 24 03:55:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11506999 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5829F912 for ; Fri, 24 Apr 2020 03:55:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40AC22084D for ; Fri, 24 Apr 2020 03:55:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="f5EN0UcO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726383AbgDXDzr (ORCPT ); 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Thu, 23 Apr 2020 20:55:25 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 7/9] MAINTAINERS: Add Tegra Video driver section Date: Thu, 23 Apr 2020 20:55:11 -0700 Message-ID: <1587700513-28449-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700463; bh=BMQVVr+zunu9dob90MEf4wUgkZwVcUqgaAtE7fDWMfE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=f5EN0UcOMSIv3t36rmln5EqxjNU+A+dYHTnq9aFbrgdOGRCRvio4/bezLObDmxqKR RwBezvk/V3tc7bVpG8OzZtCUJTtJEMD7w4/opJ0l6bc9F+WuRd+ciJ7m6qBDAXvJhs UIAAZhqrmtg5nkTaaKpeyu1Ub2cx2Rh5C4KeLC3q6SUoTNY9Dk/E0H95aqAWcAHMYA s1TTMswpqTBI0pMzQL8mbgRIyABLeLofC2MEOTKc1pbdhZSfNSqQWoigGwXA7y8a6t KfgBppyi1xU508L7vWDQDDZvChXC7fObirA8PRou+INTOZOFHDb/ptmkF9xUHRF/Cj fuLCbyjylknAw== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add maintainers and mailing list entries to Tegra Video driver section. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 973b7db..795b201 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16644,6 +16644,16 @@ M: Laxman Dewangan S: Supported F: drivers/spi/spi-tegra* +TEGRA VIDEO DRIVER +M: Thierry Reding +M: Jonathan Hunter +M: Sowjanya Komatineni +L: linux-media@vger.kernel.org +L: linux-tegra@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +F: drivers/staging/media/tegra/ + TEGRA XUSB PADCTL DRIVER M: JC Kuo S: Supported From patchwork Fri Apr 24 03:55:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11506991 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 219BD912 for ; Fri, 24 Apr 2020 03:55:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0101B2176D for ; Fri, 24 Apr 2020 03:55:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ncMOXkoQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726585AbgDXDzb (ORCPT ); Thu, 23 Apr 2020 23:55:31 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10180 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726565AbgDXDz2 (ORCPT ); Thu, 23 Apr 2020 23:55:28 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:55:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:27 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 23 Apr 2020 20:55:27 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:27 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:27 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Apr 2020 20:55:26 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Date: Thu, 23 Apr 2020 20:55:12 -0700 Message-ID: <1587700513-28449-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700515; bh=KEZ1lHNwQNYea9tamUq6xhOd3Wa4inGS2Z794lURij8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ncMOXkoQgz34dfn7yyo9E6OnmCDtW2lGwJxCjCL4ly93JM9W/N3dFFs7Yv/etZkDh NqcViAQRVpUot7xZ9gUjrEPOlnRC8x2bRUvjN/tD9gWgzJlzRcN9pBNLp9nnCJ8zv9 2O980BWI29IBqAxzRBvEoNZ65dJg7HgmvYKyl5l2p31O4ag8bjEdiOeRhSCfA8gzsn ob+ME80BekKLTjYDSfI+HyWcW21hsDqZUJ8dnL0cOdp4CSiUoL61wMu2CFo6dkf/Ns geWCZXIC7IIj1rhn2AxVvBDq5V2rKIozmbeCL5mLL1CttHVPDMucRDicXb0ijL2Anh 5zqho6E/SPVxA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch adds ID for Tegra210 VI controller reset to use with device tree. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/reset/tegra210-car.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 9dc84ec..8755946 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -10,5 +10,6 @@ #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) +#define TEGRA210_RST_VI 20 #endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */ From patchwork Fri Apr 24 03:55:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11506993 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDDE9912 for ; Fri, 24 Apr 2020 03:55:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C4CC4214AF for ; Fri, 24 Apr 2020 03:55:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="iqSmrp/N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726582AbgDXDza (ORCPT ); Thu, 23 Apr 2020 23:55:30 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:10781 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726415AbgDXDz3 (ORCPT ); Thu, 23 Apr 2020 23:55:29 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:53:31 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:29 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 23 Apr 2020 20:55:29 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:28 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:28 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Apr 2020 20:55:28 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Date: Thu, 23 Apr 2020 20:55:13 -0700 Message-ID: <1587700513-28449-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700411; bh=yB3b29VbNFtTvMcPZCMVxLppaVECoZp9WEY70dWiuUY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=iqSmrp/Ne420fwoyhZcPRvEsQyinRRopiqKbMQSWo0UKHHywUe9gLZicgJggH3o7M lxpBRaOMeWVlI3Vmedyw59i3LJfhEHFyUkwc4PFig/BxkNOmGbR9agcojO1HRI/EFF 13c3Dw3P42KyMp6mw7wFUc9YYU16c1kNdKPoCYEwUQBQFrPnKmiLki4q5yrZ5/K0nv lvIS7OJpMRCL9dcJ2TJboATI5SHrurCqSSe1NBuEzb0QqeeBUbweVJMdK2Dw2mxZ8E 2SUETHqRk6uRFIqFNB5TG2PxPdsW31Lrb7/XRc0dgQ46+vjFX8ygti8gLDrDN0rAt2 w+dkc/QZd+gKQ== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 46 +++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c2..b57d837 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5b1dfd8..cad42a7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,44 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; tsec@54100000 { @@ -839,6 +874,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car TEGRA210_RST_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 {