From patchwork Fri Apr 24 06:35:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernard Zhao X-Patchwork-Id: 11507239 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3818914DD for ; Fri, 24 Apr 2020 07:15:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 204FC20774 for ; Fri, 24 Apr 2020 07:15:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 204FC20774 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=vivo.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 432ED6EA7D; Fri, 24 Apr 2020 07:15:40 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-m17613.qiye.163.com (mail-m17613.qiye.163.com [59.111.176.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id B65DD6E441 for ; Fri, 24 Apr 2020 06:36:26 +0000 (UTC) Received: from ubuntu.localdomain (unknown [157.0.31.122]) by mail-m17613.qiye.163.com (Hmail) with ESMTPA id C0A69482514; Fri, 24 Apr 2020 14:36:12 +0800 (CST) From: Bernard Zhao To: Liviu Dudau , Brian Starkey , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] drm/arm: fixes pixel clock enabled with wrong format Date: Thu, 23 Apr 2020 23:35:51 -0700 Message-Id: <20200424063551.14336-1-bernard@vivo.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgYFAkeWUFZTlVOS01CQkJCTUJPQ0lPSVlXWShZQU hPN1dZLVlBSVdZCQ4XHghZQVk1NCk2OjckKS43PlkG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PxQ6Ijo*PTg*HlYTM0IQNSIQ HBQaCSJVSlVKTkNMTEpLSkxNS09IVTMWGhIXVRkeCRUaCR87DRINFFUYFBZFWVdZEgtZQVlKTkxV S1VISlVKSUlZV1kIAVlBSElPTTcG X-HM-Tid: 0a71aae69f0d93bakuwsc0a69482514 X-Mailman-Approved-At: Fri, 24 Apr 2020 07:15:40 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: opensource.kernel@vivo.com, Bernard Zhao Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The pixel clock is still enabled when the format is wrong. no error branch handle, and also some register is not set in this case, e.g: HDLCD_REG__SELECT. Maybe we should disable this clock and throw an warn message when this happened. With this change, the code maybe a bit more readable. Signed-off-by: Bernard Zhao Changes since V1: *add format error handle, if format is not correct, throw an warning message and disable this clock. Link for V1: *https://lore.kernel.org/patchwork/patch/1228501/ --- drivers/gpu/drm/arm/hdlcd_crtc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index af67fefed38d..f3945dee2b7d 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -96,7 +96,7 @@ static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) } if (WARN_ON(!format)) - return 0; + return -EINVAL; /* HDLCD uses 'bytes per pixel', zero means 1 byte */ btpp = (format->bits_per_pixel + 7) / 8; @@ -125,7 +125,7 @@ static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) return 0; } -static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) +static int hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); struct drm_display_mode *m = &crtc->state->adjusted_mode; @@ -162,9 +162,10 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) err = hdlcd_set_pxl_fmt(crtc); if (err) - return; + return err; clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); + return 0; } static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, @@ -173,7 +174,11 @@ static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); clk_prepare_enable(hdlcd->clk); - hdlcd_crtc_mode_set_nofb(crtc); + if (hdlcd_crtc_mode_set_nofb(crtc)) { + DRM_DEBUG_KMS("Invalid format, pixel clock enable failed!\n"); + clk_disable_unprepare(hdlcd->clk); + return; + } hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); drm_crtc_vblank_on(crtc); }