From patchwork Fri Apr 24 10:45:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507509 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2485D1575 for ; Fri, 24 Apr 2020 10:46:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15FA32064A for ; Fri, 24 Apr 2020 10:46:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbgDXKqA (ORCPT ); Fri, 24 Apr 2020 06:46:00 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:10104 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726489AbgDXKqA (ORCPT ); Fri, 24 Apr 2020 06:46:00 -0400 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03OAXdCF038456; Fri, 24 Apr 2020 06:45:59 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 30kpq45x80-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 06:45:58 -0400 Received: from m0098417.ppops.net (m0098417.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 03OAZP4c046995; Fri, 24 Apr 2020 06:45:58 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 30kpq45x78-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 06:45:58 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 03OAjTqe022195; Fri, 24 Apr 2020 10:45:56 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma03ams.nl.ibm.com with ESMTP id 30fs65921v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 10:45:56 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03OAjsrW1179926 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 24 Apr 2020 10:45:54 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9764FA4040; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4560DA4053; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 01/10] s390x: saving regs for interrupts Date: Fri, 24 Apr 2020 12:45:43 +0200 Message-Id: <1587725152-25569-2-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=1 mlxscore=0 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 mlxlogscore=950 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240082 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If we use multiple source of interrupts, for example, using SCLP console to print information while using I/O interrupts, we need to have a re-entrant register saving interruption handling. Instead of saving at a static memory address, let's save the base registers and the floating point registers on the stack. Note that we keep the static register saving to recover from the RESET tests. Signed-off-by: Pierre Morel --- s390x/cstart64.S | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 9af6bb3..ba2e67c 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -118,6 +118,36 @@ memsetxc: lmg %r0, %r15, GEN_LC_SW_INT_GRS .endm +/* Save registers on the stack (r15), so we can have stacked interrupts. */ + .macro SAVE_IRQ_REGS + /* Allocate a stack frame for 15 integer registers */ + slgfi %r15, 15 * 8 + /* Store all registers from r0 to r14 on the stack */ + stmg %r0, %r14, 0(%r15) + /* Allocate a stack frame for 16 floating point registers */ + /* The size of a FP register is the size of an integer */ + slgfi %r15, 16 * 8 + /* Save fp register on stack: offset to SP is multiple of reg number */ + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + std \i, \i * 8(%r15) + .endr + .endm + +/* Restore the register in reverse order */ + .macro RESTORE_IRQ_REGS + /* Restore fp register from stack: SP still where it was left */ + /* and offset to SP is a multile of reg number */ + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ld \i, \i * 8(%r15) + .endr + /* Now it is done, rewind the stack pointer by 16 integers */ + algfi %r15, 16 * 8 + /* Load the registers from stack */ + lmg %r0, %r14, 0(%r15) + /* Rewind the stack by 15 integers */ + algfi %r15, 15 * 8 + .endm + .section .text /* * load_reset calling convention: @@ -182,9 +212,9 @@ mcck_int: lpswe GEN_LC_MCCK_OLD_PSW io_int: - SAVE_REGS + SAVE_IRQ_REGS brasl %r14, handle_io_int - RESTORE_REGS + RESTORE_IRQ_REGS lpswe GEN_LC_IO_OLD_PSW svc_int: From patchwork Fri Apr 24 10:45:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507517 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 149CD13B2 for ; Fri, 24 Apr 2020 10:46:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 07A0A20776 for ; Fri, 24 Apr 2020 10:46:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726994AbgDXKqE (ORCPT ); Fri, 24 Apr 2020 06:46:04 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:26142 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726888AbgDXKqD (ORCPT ); Fri, 24 Apr 2020 06:46:03 -0400 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03OAY9pm026097 for ; Fri, 24 Apr 2020 06:46:02 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 30kk5tb6qt-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 24 Apr 2020 06:46:01 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 24 Apr 2020 11:45:05 +0100 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03OAjtSv57802940 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 24 Apr 2020 10:45:55 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 10FF8A404D; Fri, 24 Apr 2020 10:45:55 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AA00FA4051; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 02/10] s390x: Use PSW bits definitions in cstart Date: Fri, 24 Apr 2020 12:45:44 +0200 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20042410-0016-0000-0000-0000030A3169 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20042410-0017-0000-0000-0000336E579F Message-Id: <1587725152-25569-3-git-send-email-pmorel@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 suspectscore=1 impostorscore=0 malwarescore=0 mlxlogscore=834 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240082 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This patch defines the PSW bits EA/BA used to initialize the PSW masks for exceptions. Since some PSW mask definitions exist already in arch_def.h we add these definitions there. We move all PSW definitions together and protect assembler code against C syntax. Signed-off-by: Pierre Morel --- lib/s390x/asm/arch_def.h | 16 ++++++++++++---- s390x/cstart64.S | 15 ++++++++------- 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index 15a4d49..c54409a 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -10,15 +10,22 @@ #ifndef _ASM_S390X_ARCH_DEF_H_ #define _ASM_S390X_ARCH_DEF_H_ +#define PSW_MASK_EXT 0x0100000000000000UL +#define PSW_MASK_DAT 0x0400000000000000UL +#define PSW_MASK_SHORT_PSW 0x0008000000000000UL +#define PSW_MASK_PSTATE 0x0001000000000000UL +#define PSW_MASK_BA 0x0000000080000000UL +#define PSW_MASK_EA 0x0000000100000000UL + +#define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) +#define PSW_RESET_MASK (PSW_EXCEPTION_MASK | PSW_MASK_SHORT_PSW) + +#ifndef __ASSEMBLER__ struct psw { uint64_t mask; uint64_t addr; }; -#define PSW_MASK_EXT 0x0100000000000000UL -#define PSW_MASK_DAT 0x0400000000000000UL -#define PSW_MASK_PSTATE 0x0001000000000000UL - #define CR0_EXTM_SCLP 0X0000000000000200UL #define CR0_EXTM_EXTC 0X0000000000002000UL #define CR0_EXTM_EMGC 0X0000000000004000UL @@ -297,4 +304,5 @@ static inline uint32_t get_prefix(void) return current_prefix; } +#endif /* __ASSEMBLER */ #endif diff --git a/s390x/cstart64.S b/s390x/cstart64.S index ba2e67c..e394b3a 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -12,6 +12,7 @@ */ #include #include +#include .section .init @@ -225,19 +226,19 @@ svc_int: .align 8 reset_psw: - .quad 0x0008000180000000 + .quad PSW_RESET_MASK initial_psw: - .quad 0x0000000180000000, clear_bss_start + .quad PSW_EXCEPTION_MASK, clear_bss_start pgm_int_psw: - .quad 0x0000000180000000, pgm_int + .quad PSW_EXCEPTION_MASK, pgm_int ext_int_psw: - .quad 0x0000000180000000, ext_int + .quad PSW_EXCEPTION_MASK, ext_int mcck_int_psw: - .quad 0x0000000180000000, mcck_int + .quad PSW_EXCEPTION_MASK, mcck_int io_int_psw: - .quad 0x0000000180000000, io_int + .quad PSW_EXCEPTION_MASK, io_int svc_int_psw: - .quad 0x0000000180000000, svc_int + .quad PSW_EXCEPTION_MASK, svc_int initial_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ .quad 0x0000000000040000 From patchwork Fri Apr 24 10:45:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507525 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DEE0D13B2 for ; Fri, 24 Apr 2020 10:46:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBB032064A for ; Fri, 24 Apr 2020 10:46:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726941AbgDXKqD (ORCPT ); Fri, 24 Apr 2020 06:46:03 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:20864 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726842AbgDXKqC (ORCPT ); Fri, 24 Apr 2020 06:46:02 -0400 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03OAXG4q106498 for ; Fri, 24 Apr 2020 06:46:01 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0b-001b2d01.pphosted.com with ESMTP id 30kx0jh397-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 24 Apr 2020 06:46:00 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 24 Apr 2020 11:45:18 +0100 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03OAjtiv57802946 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 24 Apr 2020 10:45:55 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 74F1BA4053; Fri, 24 Apr 2020 10:45:55 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 26208A4051; Fri, 24 Apr 2020 10:45:55 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:55 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 03/10] s390x: Move control register bit definitions and add AFP to them Date: Fri, 24 Apr 2020 12:45:45 +0200 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20042410-0008-0000-0000-0000037678AD X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20042410-0009-0000-0000-00004A984912 Message-Id: <1587725152-25569-4-git-send-email-pmorel@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=1 adultscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240078 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org While adding the definition for the AFP-Register control bit, move all existing definitions for CR0 out of the C zone to the assmbler zone to keep the definitions concerning CR0 together. Signed-off-by: Pierre Morel Reviewed-by: David Hildenbrand Reviewed-by: Janosch Frank Reviewed-by: Cornelia Huck --- lib/s390x/asm/arch_def.h | 11 ++++++----- s390x/cstart64.S | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index c54409a..a0d2362 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -20,17 +20,18 @@ #define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) #define PSW_RESET_MASK (PSW_EXCEPTION_MASK | PSW_MASK_SHORT_PSW) +#define CR0_EXTM_SCLP 0X0000000000000200UL +#define CR0_EXTM_EXTC 0X0000000000002000UL +#define CR0_EXTM_EMGC 0X0000000000004000UL +#define CR0_EXTM_MASK 0X0000000000006200UL +#define CR0_AFP_REG_CRTL 0x0000000000040000UL + #ifndef __ASSEMBLER__ struct psw { uint64_t mask; uint64_t addr; }; -#define CR0_EXTM_SCLP 0X0000000000000200UL -#define CR0_EXTM_EXTC 0X0000000000002000UL -#define CR0_EXTM_EMGC 0X0000000000004000UL -#define CR0_EXTM_MASK 0X0000000000006200UL - struct lowcore { uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ uint32_t ext_int_param; /* 0x0080 */ diff --git a/s390x/cstart64.S b/s390x/cstart64.S index e394b3a..2906e39 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -241,4 +241,4 @@ svc_int_psw: .quad PSW_EXCEPTION_MASK, svc_int initial_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ - .quad 0x0000000000040000 + .quad CR0_AFP_REG_CRTL From patchwork Fri Apr 24 10:45:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507527 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3906C15AB for ; Fri, 24 Apr 2020 10:46:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B53B20776 for ; Fri, 24 Apr 2020 10:46:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726904AbgDXKqC (ORCPT ); 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Fri, 24 Apr 2020 10:45:55 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:55 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 04/10] s390x: interrupt registration Date: Fri, 24 Apr 2020 12:45:46 +0200 Message-Id: <1587725152-25569-5-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 spamscore=0 mlxlogscore=777 bulkscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=1 impostorscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240082 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Let's make it possible to add and remove a custom io interrupt handler, that can be used instead of the normal one. Signed-off-by: Pierre Morel Reviewed-by: Thomas Huth Reviewed-by: David Hildenbrand Reviewed-by: Janosch Frank --- lib/s390x/interrupt.c | 23 ++++++++++++++++++++++- lib/s390x/interrupt.h | 8 ++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 lib/s390x/interrupt.h diff --git a/lib/s390x/interrupt.c b/lib/s390x/interrupt.c index 3a40cac..243b9c2 100644 --- a/lib/s390x/interrupt.c +++ b/lib/s390x/interrupt.c @@ -10,9 +10,9 @@ * under the terms of the GNU Library General Public License version 2. */ #include -#include #include #include +#include static bool pgm_int_expected; static bool ext_int_expected; @@ -144,12 +144,33 @@ void handle_mcck_int(void) stap(), lc->mcck_old_psw.addr); } +static void (*io_int_func)(void); + void handle_io_int(void) { + if (io_int_func) + return io_int_func(); + report_abort("Unexpected io interrupt: on cpu %d at %#lx", stap(), lc->io_old_psw.addr); } +int register_io_int_func(void (*f)(void)) +{ + if (io_int_func) + return -1; + io_int_func = f; + return 0; +} + +int unregister_io_int_func(void (*f)(void)) +{ + if (io_int_func != f) + return -1; + io_int_func = NULL; + return 0; +} + void handle_svc_int(void) { report_abort("Unexpected supervisor call interrupt: on cpu %d at %#lx", diff --git a/lib/s390x/interrupt.h b/lib/s390x/interrupt.h new file mode 100644 index 0000000..323258d --- /dev/null +++ b/lib/s390x/interrupt.h @@ -0,0 +1,8 @@ +#ifndef __INTERRUPT_H +#define __INTERRUPT_H +#include + +int register_io_int_func(void (*f)(void)); +int unregister_io_int_func(void (*f)(void)); + +#endif /* __INTERRUPT_H */ From patchwork Fri Apr 24 10:45:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B5C9413B2 for ; Fri, 24 Apr 2020 10:46:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E53220776 for ; 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Fri, 24 Apr 2020 10:45:55 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:55 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 05/10] s390x: Library resources for CSS tests Date: Fri, 24 Apr 2020 12:45:47 +0200 Message-Id: <1587725152-25569-6-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=1 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240078 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org These are the include and library utilities for the css tests patch series. Debug function can be activated by defining DEBUG_CSS before the inclusion of the css.h header file. Signed-off-by: Pierre Morel --- lib/s390x/css.h | 256 +++++++++++++++++++++++++++++++++++++++++++ lib/s390x/css_dump.c | 157 ++++++++++++++++++++++++++ 2 files changed, 413 insertions(+) create mode 100644 lib/s390x/css.h create mode 100644 lib/s390x/css_dump.c diff --git a/lib/s390x/css.h b/lib/s390x/css.h new file mode 100644 index 0000000..bab0dd5 --- /dev/null +++ b/lib/s390x/css.h @@ -0,0 +1,256 @@ +/* + * CSS definitions + * + * Copyright IBM, Corp. 2020 + * Author: Pierre Morel + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at + * your option) any later version. See the COPYING file in the top-level + * directory. + */ + +#ifndef CSS_H +#define CSS_H + +#define CCW_F_CD 0x80 +#define CCW_F_CC 0x40 +#define CCW_F_SLI 0x20 +#define CCW_F_SKP 0x10 +#define CCW_F_PCI 0x08 +#define CCW_F_IDA 0x04 +#define CCW_F_S 0x02 +#define CCW_F_MIDA 0x01 + +#define CCW_C_NOP 0x03 +#define CCW_C_TIC 0x08 + +struct ccw1 { + unsigned char code; + unsigned char flags; + unsigned short count; + uint32_t data_address; +} __attribute__ ((aligned(4))); + +#define ORB_M_KEY 0xf0000000 +#define ORB_F_SUSPEND 0x08000000 +#define ORB_F_STREAMING 0x04000000 +#define ORB_F_MODIFCTRL 0x02000000 +#define ORB_F_SYNC 0x01000000 +#define ORB_F_FORMAT 0x00800000 +#define ORB_F_PREFETCH 0x00400000 +#define ORB_F_INIT_IRQ 0x00200000 +#define ORB_F_ADDRLIMIT 0x00100000 +#define ORB_F_SUSP_IRQ 0x00080000 +#define ORB_F_TRANSPORT 0x00040000 +#define ORB_F_IDAW2 0x00020000 +#define ORB_F_IDAW_2K 0x00010000 +#define ORB_M_LPM 0x0000ff00 +#define ORB_F_LPM_DFLT 0x00008000 +#define ORB_F_ILSM 0x00000080 +#define ORB_F_CCW_IND 0x00000040 +#define ORB_F_ORB_EXT 0x00000001 + +struct orb { + uint32_t intparm; + uint32_t ctrl; + uint32_t cpa; + uint32_t prio; + uint32_t reserved[4]; +} __attribute__ ((aligned(4))); + +struct scsw { + uint32_t ctrl; + uint32_t ccw_addr; + uint8_t dev_stat; + uint8_t sch_stat; + uint16_t count; +}; + +struct pmcw { + uint32_t intparm; +#define PMCW_DNV 0x0001 +#define PMCW_ENABLE 0x0080 + uint16_t flags; + uint16_t devnum; + uint8_t lpm; + uint8_t pnom; + uint8_t lpum; + uint8_t pim; + uint16_t mbi; + uint8_t pom; + uint8_t pam; + uint8_t chpid[8]; + uint32_t flags2; +}; + +struct schib { + struct pmcw pmcw; + struct scsw scsw; + uint8_t md[12]; +} __attribute__ ((aligned(4))); + +struct irb { + struct scsw scsw; + uint32_t esw[5]; + uint32_t ecw[8]; + uint32_t emw[8]; +} __attribute__ ((aligned(4))); + +/* CSS low level access functions */ + +static inline int ssch(unsigned long schid, struct orb *addr) +{ + register long long reg1 asm("1") = schid; + int cc; + + asm volatile( + " ssch 0(%2)\n" + " ipm %0\n" + " srl %0,28\n" + : "=d" (cc) + : "d" (reg1), "a" (addr), "m" (*addr) + : "cc", "memory"); + return cc; +} + +static inline int stsch(unsigned long schid, struct schib *addr) +{ + register unsigned long reg1 asm ("1") = schid; + int cc; + + asm volatile( + " stsch 0(%3)\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc), "=m" (*addr) + : "d" (reg1), "a" (addr) + : "cc"); + return cc; +} + +static inline int msch(unsigned long schid, struct schib *addr) +{ + register unsigned long reg1 asm ("1") = schid; + int cc; + + asm volatile( + " msch 0(%3)\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc), "=m" (*addr) + : "d" (reg1), "a" (addr) + : "cc"); + return cc; +} + +static inline int tsch(unsigned long schid, struct irb *addr) +{ + register unsigned long reg1 asm ("1") = schid; + int cc; + + asm volatile( + " tsch 0(%3)\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc), "=m" (*addr) + : "d" (reg1), "a" (addr) + : "cc"); + return cc; +} + +static inline int hsch(unsigned long schid) +{ + register unsigned long reg1 asm("1") = schid; + int cc; + + asm volatile( + " hsch\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc) + : "d" (reg1) + : "cc"); + return cc; +} + +static inline int xsch(unsigned long schid) +{ + register unsigned long reg1 asm("1") = schid; + int cc; + + asm volatile( + " xsch\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc) + : "d" (reg1) + : "cc"); + return cc; +} + +static inline int csch(unsigned long schid) +{ + register unsigned long reg1 asm("1") = schid; + int cc; + + asm volatile( + " csch\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc) + : "d" (reg1) + : "cc"); + return cc; +} + +static inline int rsch(unsigned long schid) +{ + register unsigned long reg1 asm("1") = schid; + int cc; + + asm volatile( + " rsch\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc) + : "d" (reg1) + : "cc"); + return cc; +} + +static inline int rchp(unsigned long chpid) +{ + register unsigned long reg1 asm("1") = chpid; + int cc; + + asm volatile( + " rchp\n" + " ipm %0\n" + " srl %0,28" + : "=d" (cc) + : "d" (reg1) + : "cc"); + return cc; +} + +/* Debug functions */ +char *dump_pmcw_flags(uint16_t f); +char *dump_scsw_flags(uint32_t f); + +#ifdef DEBUG_CSS +void dump_scsw(struct scsw *); +void dump_irb(struct irb *irbp); +void dump_schib(struct schib *sch); +struct ccw *dump_ccw(struct ccw *cp); +#else +static inline void dump_scsw(struct scsw *scsw) {} +static inline void dump_irb(struct irb *irbp) {} +static inline void dump_pmcw(struct pmcw *p) {} +static inline void dump_schib(struct schib *sch) {} +static inline void dump_orb(struct orb *op) {} +static inline struct ccw *dump_ccw(struct ccw *cp) +{ + return NULL; +} +#endif /* DEBUG_CSS */ +#endif diff --git a/lib/s390x/css_dump.c b/lib/s390x/css_dump.c new file mode 100644 index 0000000..2f33fab --- /dev/null +++ b/lib/s390x/css_dump.c @@ -0,0 +1,157 @@ +/* + * Channel subsystem structures dumping + * + * Copyright (c) 2020 IBM Corp. + * + * Authors: + * Pierre Morel + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2. + * + * Description: + * Provides the dumping functions for various structures used by subchannels: + * - ORB : Operation request block, describes the I/O operation and points to + * a CCW chain + * - CCW : Channel Command Word, describes the data and flow control + * - IRB : Interuption response Block, describes the result of an operation + * holds a SCSW and model-dependent data. + * - SCHIB: SubCHannel Information Block composed of: + * - SCSW: SubChannel Status Word, status of the channel. + * - PMCW: Path Management Control Word + * You need the QEMU ccw-pong device in QEMU to answer the I/O transfers. + */ + +#include +#include +#include +#include + +#undef DEBUG_CSS +#include + +/* + * Try to have a more human representation of the SCSW flags: + * each letter in the two strings represent the first + * letter of the associated bit in the flag fields. + */ +static const char *scsw_str = "kkkkslccfpixuzen"; +static const char *scsw_str2 = "1SHCrshcsdsAIPSs"; +static char scsw_line[64] = {}; + +char *dump_scsw_flags(uint32_t f) +{ + int i; + + for (i = 0; i < 16; i++) { + if ((f << i) & 0x80000000) + scsw_line[i] = scsw_str[i]; + else + scsw_line[i] = '_'; + } + scsw_line[i] = ' '; + for (; i < 32; i++) { + if ((f << i) & 0x80000000) + scsw_line[i + 1] = scsw_str2[i - 16]; + else + scsw_line[i + 1] = '_'; + } + return scsw_line; +} + +/* + * Try o have a more human representation of the PMCW flags + * each letter in the string represent the first + * letter of the associated bit in the flag fields. + */ +static const char *pmcw_str = "11iii111ellmmdtv"; +static char pcmw_line[32] = {}; +char *dump_pmcw_flags(uint16_t f) +{ + int i; + + for (i = 0; i < 16; i++) { + if ((f << i) & 0x8000) + pcmw_line[i] = pmcw_str[i]; + else + pcmw_line[i] = '_'; + } + return pcmw_line; +} + +#ifdef DEBUG_CSS +void dump_scsw(struct scsw *s) +{ + dump_scsw_flags(s->ctrl); + printf("scsw->flags: %s\n", line); + printf("scsw->addr : %08x\n", s->addr); + printf("scsw->devs : %02x\n", s->devs); + printf("scsw->schs : %02x\n", s->schs); + printf("scsw->count: %04x\n", s->count); +} + +void dump_irb(struct irb *irbp) +{ + int i; + uint32_t *p = (uint32_t *)irbp; + + dump_scsw(&irbp->scsw); + for (i = 0; i < sizeof(*irbp)/sizeof(*p); i++, p++) + printf("irb[%02x] : %08x\n", i, *p); +} + +void dump_pmcw(struct pmcw *p) +{ + int i; + + printf("pmcw->intparm : %08x\n", p->intparm); + printf("pmcw->flags : %04x\n", p->flags); + dump_pmcw_flags(p->flags); + printf("pmcw->devnum : %04x\n", p->devnum); + printf("pmcw->lpm : %02x\n", p->lpm); + printf("pmcw->pnom : %02x\n", p->pnom); + printf("pmcw->lpum : %02x\n", p->lpum); + printf("pmcw->pim : %02x\n", p->pim); + printf("pmcw->mbi : %04x\n", p->mbi); + printf("pmcw->pom : %02x\n", p->pom); + printf("pmcw->pam : %02x\n", p->pam); + printf("pmcw->mbi : %04x\n", p->mbi); + for (i = 0; i < 8; i++) + printf("pmcw->chpid[%d]: %02x\n", i, p->chpid[i]); + printf("pmcw->flags2 : %08x\n", p->flags2); +} + +void dump_schib(struct schib *sch) +{ + struct pmcw *p = &sch->pmcw; + struct scsw *s = &sch->scsw; + + printf("--SCHIB--\n"); + dump_pmcw(p); + dump_scsw(s); +} + +struct ccw *dump_ccw(struct ccw *cp) +{ + printf("CCW: code: %02x flags: %02x count: %04x data: %08x\n", cp->code, + cp->flags, cp->count, cp->data); + + if (cp->code == CCW_C_TIC) + return (struct ccw *)(long)cp->data; + + return (cp->flags & CCW_F_CC) ? cp + 1 : NULL; +} + +void dump_orb(struct orb *op) +{ + struct ccw *cp; + + printf("ORB: intparm : %08x\n", op->intparm); + printf("ORB: ctrl : %08x\n", op->ctrl); + printf("ORB: prio : %08x\n", op->prio); + cp = (struct ccw *)(long) (op->cpa); + while (cp) + cp = dump_ccw(cp); +} + +#endif From patchwork Fri Apr 24 10:45:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AECD81575 for ; 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Fri, 24 Apr 2020 10:45:56 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5F80AA4057; Fri, 24 Apr 2020 10:45:56 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:56 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 06/10] s390x: css: stsch, enumeration test Date: Fri, 24 Apr 2020 12:45:48 +0200 Message-Id: <1587725152-25569-7-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 phishscore=0 suspectscore=1 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240078 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org First step for testing the channel subsystem is to enumerate the css and retrieve the css devices. This tests the success of STSCH I/O instruction, we do not test the reaction of the VM for an instruction with wrong parameters. Signed-off-by: Pierre Morel --- lib/s390x/css.h | 1 + s390x/Makefile | 2 + s390x/css.c | 92 +++++++++++++++++++++++++++++++++++++++++++++ s390x/unittests.cfg | 4 ++ 4 files changed, 99 insertions(+) create mode 100644 s390x/css.c diff --git a/lib/s390x/css.h b/lib/s390x/css.h index bab0dd5..9417541 100644 --- a/lib/s390x/css.h +++ b/lib/s390x/css.h @@ -82,6 +82,7 @@ struct pmcw { uint8_t chpid[8]; uint32_t flags2; }; +#define PMCW_CHANNEL_TYPE(pmcw) (pmcw->flags2 >> 21) struct schib { struct pmcw pmcw; diff --git a/s390x/Makefile b/s390x/Makefile index ddb4b48..baebf18 100644 --- a/s390x/Makefile +++ b/s390x/Makefile @@ -17,6 +17,7 @@ tests += $(TEST_DIR)/stsi.elf tests += $(TEST_DIR)/skrf.elf tests += $(TEST_DIR)/smp.elf tests += $(TEST_DIR)/sclp.elf +tests += $(TEST_DIR)/css.elf tests_binary = $(patsubst %.elf,%.bin,$(tests)) all: directories test_cases test_cases_binary @@ -51,6 +52,7 @@ cflatobjs += lib/s390x/sclp-console.o cflatobjs += lib/s390x/interrupt.o cflatobjs += lib/s390x/mmu.o cflatobjs += lib/s390x/smp.o +cflatobjs += lib/s390x/css_dump.o OBJDIRS += lib/s390x diff --git a/s390x/css.c b/s390x/css.c new file mode 100644 index 0000000..cc97e79 --- /dev/null +++ b/s390x/css.c @@ -0,0 +1,92 @@ +/* + * Channel Subsystem tests + * + * Copyright (c) 2020 IBM Corp + * + * Authors: + * Pierre Morel + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define SID_ONE 0x00010000 + +static struct schib schib; +static int test_device_sid; + +static void test_enumerate(void) +{ + struct pmcw *pmcw = &schib.pmcw; + int cc; + int scn; + int scn_found = 0; + int dev_found = 0; + + for (scn = 0; scn < 0xffff; scn++) { + cc = stsch(scn|SID_ONE, &schib); + switch (cc) { + case 0: /* 0 means SCHIB stored */ + break; + case 3: /* 3 means no more channels */ + goto out; + default: /* 1 or 2 should never happened for STSCH */ + report(0, "Unexpected cc=%d on subchannel number 0x%x", + cc, scn); + return; + } + /* We currently only support type 0, a.k.a. I/O channels */ + if (PMCW_CHANNEL_TYPE(pmcw) != 0) + continue; + /* We ignore I/O channels without valid devices */ + scn_found++; + if (!(pmcw->flags & PMCW_DNV)) + continue; + /* We keep track of the first device as our test device */ + if (!test_device_sid) + test_device_sid = scn|SID_ONE; + dev_found++; + } +out: + if (!dev_found) { + report(0, + "Tested subchannels: %d, I/O subchannels: %d, I/O devices: %d", + scn, scn_found, dev_found); + return; + } + report(1, + "Tested subchannels: %d, I/O subchannels: %d, I/O devices: %d", + scn, scn_found, dev_found); +} + +static struct { + const char *name; + void (*func)(void); +} tests[] = { + { "enumerate (stsch)", test_enumerate }, + { NULL, NULL } +}; + +int main(int argc, char *argv[]) +{ + int i; + + report_prefix_push("Channel Subsystem"); + for (i = 0; tests[i].name; i++) { + report_prefix_push(tests[i].name); + tests[i].func(); + report_prefix_pop(); + } + report_prefix_pop(); + + return report_summary(); +} diff --git a/s390x/unittests.cfg b/s390x/unittests.cfg index 07013b2..a436ec0 100644 --- a/s390x/unittests.cfg +++ b/s390x/unittests.cfg @@ -83,3 +83,7 @@ extra_params = -m 1G [sclp-3g] file = sclp.elf extra_params = -m 3G + +[css] +file = css.elf +extra_params =-device ccw-pong From patchwork Fri Apr 24 10:45:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507513 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CFB431575 for ; Fri, 24 Apr 2020 10:46:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C22FE2064C for ; Fri, 24 Apr 2020 10:46:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726992AbgDXKqE (ORCPT ); Fri, 24 Apr 2020 06:46:04 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:39070 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726885AbgDXKqD (ORCPT ); Fri, 24 Apr 2020 06:46:03 -0400 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03OAX7sI040223; Fri, 24 Apr 2020 06:46:02 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 30k7rd2dx5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); 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Fri, 24 Apr 2020 10:44:49 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1EF8CA4055; Fri, 24 Apr 2020 10:45:57 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C4904A404D; Fri, 24 Apr 2020 10:45:56 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:56 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 07/10] s390x: css: msch, enable test Date: Fri, 24 Apr 2020 12:45:49 +0200 Message-Id: <1587725152-25569-8-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 impostorscore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=1 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240078 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A second step when testing the channel subsystem is to prepare a channel for use. This includes: - Get the current SubCHannel Information Block (SCHIB) using STSCH - Update it in memory to set the ENABLE bit - Tell the CSS that the SCHIB has been modified using MSCH - Get the SCHIB from the CSS again to verify that the subchannel is enabled. This tests the MSCH instruction to enable a channel succesfuly. This is NOT a routine to really enable the channel, no retry is done, in case of error, a report is made. Signed-off-by: Pierre Morel --- s390x/css.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/s390x/css.c b/s390x/css.c index cc97e79..fa068bf 100644 --- a/s390x/css.c +++ b/s390x/css.c @@ -68,11 +68,59 @@ out: scn, scn_found, dev_found); } +static void test_enable(void) +{ + struct pmcw *pmcw = &schib.pmcw; + int cc; + + if (!test_device_sid) { + report_skip("No device"); + return; + } + /* Read the SCHIB for this subchannel */ + cc = stsch(test_device_sid, &schib); + if (cc) { + report(0, "stsch cc=%d", cc); + return; + } + + /* Update the SCHIB to enable the channel */ + pmcw->flags |= PMCW_ENABLE; + + /* Tell the CSS we want to modify the subchannel */ + cc = msch(test_device_sid, &schib); + if (cc) { + /* + * If the subchannel is status pending or + * if a function is in progress, + * we consider both cases as errors. + */ + report(0, "msch cc=%d", cc); + return; + } + + /* + * Read the SCHIB again to verify the enablement + */ + cc = stsch(test_device_sid, &schib); + if (cc) { + report(0, "stsch cc=%d", cc); + return; + } + + if (!(pmcw->flags & PMCW_ENABLE)) { + report(0, "Enable failed. pmcw: %x", pmcw->flags); + return; + } + report(1, "Tested"); +} + static struct { const char *name; void (*func)(void); } tests[] = { { "enumerate (stsch)", test_enumerate }, + { "enable (msch)", test_enable }, { NULL, NULL } }; From patchwork Fri Apr 24 10:45:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507523 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 560C415AB for ; Fri, 24 Apr 2020 10:46:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47E7620776 for ; Fri, 24 Apr 2020 10:46:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727029AbgDXKqL (ORCPT ); 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Fri, 24 Apr 2020 10:45:57 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:57 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 08/10] s390x: define wfi: wait for interrupt Date: Fri, 24 Apr 2020 12:45:50 +0200 Message-Id: <1587725152-25569-9-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=634 lowpriorityscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 suspectscore=1 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240078 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org wfi(irq_mask) allows the programm to wait for an interrupt. The interrupt handler is in charge to remove the WAIT bit when it finished handling interrupt. Signed-off-by: Pierre Morel --- lib/s390x/asm/arch_def.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index a0d2362..e04866c 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -13,6 +13,7 @@ #define PSW_MASK_EXT 0x0100000000000000UL #define PSW_MASK_DAT 0x0400000000000000UL #define PSW_MASK_SHORT_PSW 0x0008000000000000UL +#define PSW_MASK_WAIT 0x0002000000000000UL #define PSW_MASK_PSTATE 0x0001000000000000UL #define PSW_MASK_BA 0x0000000080000000UL #define PSW_MASK_EA 0x0000000100000000UL @@ -254,6 +255,16 @@ static inline void load_psw_mask(uint64_t mask) : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); } +static inline void wfi(uint64_t irq_mask) +{ + uint64_t psw_mask; + + psw_mask = extract_psw_mask(); + load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); + load_psw_mask(psw_mask); +} + + static inline void enter_pstate(void) { uint64_t mask; From patchwork Fri Apr 24 10:45:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507519 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6D6813B2 for ; Fri, 24 Apr 2020 10:46:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 935A62064C for ; Fri, 24 Apr 2020 10:46:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727020AbgDXKqI (ORCPT ); Fri, 24 Apr 2020 06:46:08 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:45880 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726909AbgDXKqE (ORCPT ); Fri, 24 Apr 2020 06:46:04 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03OAXemu032591; Fri, 24 Apr 2020 06:46:03 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 30jtk3px49-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 06:46:02 -0400 Received: from m0098396.ppops.net (m0098396.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 03OAZorx040488; Fri, 24 Apr 2020 06:46:02 -0400 Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 30jtk3px2v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 06:46:02 -0400 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 03OAjWjx009747; Fri, 24 Apr 2020 10:46:00 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma04ams.nl.ibm.com with ESMTP id 30fs658ygb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 10:46:00 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03OAjwH349545224 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 24 Apr 2020 10:45:58 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EEED3A4057; Fri, 24 Apr 2020 10:45:57 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9306FA4040; Fri, 24 Apr 2020 10:45:57 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:57 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 09/10] s390x: css: ssch/tsch with sense and interrupt Date: Fri, 24 Apr 2020 12:45:51 +0200 Message-Id: <1587725152-25569-10-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=1 impostorscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240082 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We add a new css_lib file to contain the I/O function we may share with different tests. First function is the subchannel_enable() function. When a channel is enabled we can start a SENSE_ID command using the SSCH instruction to recognize the control unit and device. This tests the success of SSCH, the I/O interruption and the TSCH instructions. The test expects a device with a control unit type of 0xC0CA as the first subchannel of the CSS. Signed-off-by: Pierre Morel --- lib/s390x/asm/arch_def.h | 1 + lib/s390x/css.h | 20 ++++++ lib/s390x/css_lib.c | 55 +++++++++++++++ s390x/Makefile | 1 + s390x/css.c | 149 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 226 insertions(+) create mode 100644 lib/s390x/css_lib.c diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index e04866c..7a63ab7 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -10,6 +10,7 @@ #ifndef _ASM_S390X_ARCH_DEF_H_ #define _ASM_S390X_ARCH_DEF_H_ +#define PSW_MASK_IO 0x0200000000000000UL #define PSW_MASK_EXT 0x0100000000000000UL #define PSW_MASK_DAT 0x0400000000000000UL #define PSW_MASK_SHORT_PSW 0x0008000000000000UL diff --git a/lib/s390x/css.h b/lib/s390x/css.h index 9417541..f278d0b 100644 --- a/lib/s390x/css.h +++ b/lib/s390x/css.h @@ -97,6 +97,19 @@ struct irb { uint32_t emw[8]; } __attribute__ ((aligned(4))); +#define CCW_CMD_SENSE_ID 0xe4 +#define PONG_CU 0xc0ca +struct senseid { + /* common part */ + uint8_t reserved; /* always 0x'FF' */ + uint16_t cu_type; /* control unit type */ + uint8_t cu_model; /* control unit model */ + uint16_t dev_type; /* device type */ + uint8_t dev_model; /* device model */ + uint8_t unused; /* padding byte */ + uint8_t padding[256 - 10]; /* Extra padding for CCW */ +} __attribute__ ((aligned(4))) __attribute__ ((packed)); + /* CSS low level access functions */ static inline int ssch(unsigned long schid, struct orb *addr) @@ -254,4 +267,11 @@ static inline struct ccw *dump_ccw(struct ccw *cp) return NULL; } #endif /* DEBUG_CSS */ + +#define SID_ONE 0x00010000 + +/* Library functions */ +int enable_subchannel(unsigned int sid); +int start_ccw1_chain(unsigned int sid, struct ccw1 *ccw); + #endif diff --git a/lib/s390x/css_lib.c b/lib/s390x/css_lib.c new file mode 100644 index 0000000..80b9359 --- /dev/null +++ b/lib/s390x/css_lib.c @@ -0,0 +1,55 @@ +/* + * Channel subsystem library functions + * + * Copyright (c) 2020 IBM Corp. + * + * Authors: + * Pierre Morel + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2. + */ +#include +#include +#include + +int enable_subchannel(unsigned int sid) +{ + struct schib schib; + struct pmcw *pmcw = &schib.pmcw; + int try_count = 5; + int cc; + + if (!(sid & SID_ONE)) + return -1; + + cc = stsch(sid, &schib); + if (cc) + return -cc; + + do { + pmcw->flags |= PMCW_ENABLE; + + cc = msch(sid, &schib); + if (cc) + return -cc; + + cc = stsch(sid, &schib); + if (cc) + return -cc; + + } while (!(pmcw->flags & PMCW_ENABLE) && --try_count); + + return try_count; +} + +int start_ccw1_chain(unsigned int sid, struct ccw1 *ccw) +{ + struct orb orb; + + orb.intparm = sid; + orb.ctrl = ORB_F_INIT_IRQ|ORB_F_FORMAT|ORB_F_LPM_DFLT; + orb.cpa = (unsigned int) (unsigned long)ccw; + + return ssch(sid, &orb); +} diff --git a/s390x/Makefile b/s390x/Makefile index baebf18..166cb5c 100644 --- a/s390x/Makefile +++ b/s390x/Makefile @@ -53,6 +53,7 @@ cflatobjs += lib/s390x/interrupt.o cflatobjs += lib/s390x/mmu.o cflatobjs += lib/s390x/smp.o cflatobjs += lib/s390x/css_dump.o +cflatobjs += lib/s390x/css_lib.o OBJDIRS += lib/s390x diff --git a/s390x/css.c b/s390x/css.c index fa068bf..b9dbf01 100644 --- a/s390x/css.c +++ b/s390x/css.c @@ -20,9 +20,26 @@ #include #define SID_ONE 0x00010000 +#define PSW_PRG_MASK (PSW_MASK_EA | PSW_MASK_BA) + +#define PONG_CU_TYPE 0xc0ca + +struct lowcore *lowcore = (void *)0x0; static struct schib schib; static int test_device_sid; +#define NUM_CCW 100 +static struct ccw1 ccw[NUM_CCW]; +static struct irb irb; +static struct senseid senseid; + +static void set_io_irq_subclass_mask(uint64_t const new_mask) +{ + asm volatile ( + "lctlg %%c6, %%c6, %[source]\n" + : /* No outputs */ + : [source] "R" (new_mask)); +} static void test_enumerate(void) { @@ -115,12 +132,143 @@ static void test_enable(void) report(1, "Tested"); } +static void enable_io_isc(void) +{ + /* Let's enable all ISCs for I/O interrupt */ + set_io_irq_subclass_mask(0x00000000ff000000); +} + +static void irq_io(void) +{ + int ret = 0; + char *flags; + int sid; + + report_prefix_push("Interrupt"); + /* Lowlevel set the SID as interrupt parameter. */ + if (lowcore->io_int_param != test_device_sid) { + report(0, + "Bad io_int_param: %x expected %x", + lowcore->io_int_param, test_device_sid); + goto pop; + } + report_prefix_pop(); + + report_prefix_push("tsch"); + sid = lowcore->subsys_id_word; + ret = tsch(sid, &irb); + switch (ret) { + case 1: + dump_irb(&irb); + flags = dump_scsw_flags(irb.scsw.ctrl); + report(0, + "I/O interrupt, but sch not status pending: %s", flags); + break; + case 2: + report(0, "TSCH returns unexpected CC 2"); + break; + case 3: + report(0, "Subchannel %08x not operational", sid); + break; + case 0: + /* Stay humble on success */ + break; + } +pop: + report_prefix_pop(); + lowcore->io_old_psw.mask &= ~PSW_MASK_WAIT; +} + +static int start_subchannel(int code, void *data, int count) +{ + int ret; + + report_prefix_push("start_senseid"); + /* Build the CCW chain with a single CCW */ + ccw[0].code = code; + ccw[0].flags = 0; /* No flags need to be set */ + ccw[0].count = count; + ccw[0].data_address = (int)(unsigned long)data; + + ret = start_ccw1_chain(test_device_sid, ccw); + if (ret) { + report(0, "start_ccw_chain failed ret=%d", ret); + report_prefix_pop(); + return 0; + } + report_prefix_pop(); + return 1; +} + +/* + * test_sense + * Pre-requisits: + * - We need the QEMU PONG device as the first recognized + * device by the enumeration. + * - ./s390x-run s390x/css.elf -device ccw-pong,cu_type=0xc0ca + */ +static void test_sense(void) +{ + int ret; + + if (!test_device_sid) { + report_skip("No device"); + return; + } + + ret = enable_subchannel(test_device_sid); + if (ret < 0) { + report(0, + "Could not enable the subchannel: %08x", + test_device_sid); + return; + } + + ret = register_io_int_func(irq_io); + if (ret) { + report(0, "Could not register IRQ handler"); + goto unreg_cb; + } + + lowcore->io_int_param = 0; + + ret = start_subchannel(CCW_CMD_SENSE_ID, &senseid, sizeof(senseid)); + if (!ret) { + report(0, "start_senseid failed"); + goto unreg_cb; + } + + wfi(PSW_MASK_IO); + + if (lowcore->io_int_param != test_device_sid) { + report(0, + "No interrupts. io_int_param: expect 0x%08x, got 0x%08x", + test_device_sid, lowcore->io_int_param); + goto unreg_cb; + } + + report_info("reserved %02x cu_type %04x cu_model %02x dev_type %04x dev_model %02x", + senseid.reserved, senseid.cu_type, senseid.cu_model, + senseid.dev_type, senseid.dev_model); + + if (senseid.cu_type == PONG_CU) + report(1, "cu_type: expect 0x%04x got 0x%04x", + PONG_CU_TYPE, senseid.cu_type); + else + report(0, "cu_type: expect 0x%04x got 0x%04x", + PONG_CU_TYPE, senseid.cu_type); + +unreg_cb: + unregister_io_int_func(irq_io); +} + static struct { const char *name; void (*func)(void); } tests[] = { { "enumerate (stsch)", test_enumerate }, { "enable (msch)", test_enable }, + { "sense (ssch/tsch)", test_sense }, { NULL, NULL } }; @@ -129,6 +277,7 @@ int main(int argc, char *argv[]) int i; report_prefix_push("Channel Subsystem"); + enable_io_isc(); for (i = 0; tests[i].name; i++) { report_prefix_push(tests[i].name); tests[i].func(); From patchwork Fri Apr 24 10:45:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507515 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4407513B2 for ; Fri, 24 Apr 2020 10:46:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 34FE620776 for ; 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Fri, 24 Apr 2020 10:45:58 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:57 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 10/10] s390x: css: ping pong Date: Fri, 24 Apr 2020 12:45:52 +0200 Message-Id: <1587725152-25569-11-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 suspectscore=1 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240078 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To test a write command with the SSCH instruction we need a QEMU device, with control unit type 0xC0CA. The PONG device is such a device. This type of device responds to PONG_WRITE requests by incrementing an integer, stored as a string at offset 0 of the CCW data. Signed-off-by: Pierre Morel --- s390x/css.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/s390x/css.c b/s390x/css.c index b9dbf01..7cd8731 100644 --- a/s390x/css.c +++ b/s390x/css.c @@ -23,6 +23,12 @@ #define PSW_PRG_MASK (PSW_MASK_EA | PSW_MASK_BA) #define PONG_CU_TYPE 0xc0ca +/* Channel Commands for PONG device */ +#define PONG_WRITE 0x21 /* Write */ +#define PONG_READ 0x22 /* Read buffer */ + +#define BUFSZ 9 +static char buffer[BUFSZ]; struct lowcore *lowcore = (void *)0x0; @@ -262,6 +268,53 @@ unreg_cb: unregister_io_int_func(irq_io); } +static void test_ping(void) +{ + int success, result; + int cnt = 0, max = 4; + + if (senseid.cu_type != PONG_CU) { + report_skip("No PONG, no ping-pong"); + return; + } + + result = register_io_int_func(irq_io); + if (result) { + report(0, "Could not register IRQ handler"); + return; + } + + while (cnt++ < max) { + snprintf(buffer, BUFSZ, "%08x\n", cnt); + success = start_subchannel(PONG_WRITE, buffer, BUFSZ); + if (!success) { + report(0, "start_subchannel failed"); + goto unreg_cb; + } + + wfi(PSW_MASK_IO); + + success = start_subchannel(PONG_READ, buffer, BUFSZ); + if (!success) { + report(0, "start_subchannel failed"); + goto unreg_cb; + } + + wfi(PSW_MASK_IO); + + result = atol(buffer); + if (result != (cnt + 1)) { + report(0, "Bad answer from pong: %08x - %08x", + cnt, result); + goto unreg_cb; + } + } + report(1, "ping-pong count 0x%08x", cnt); + +unreg_cb: + unregister_io_int_func(irq_io); +} + static struct { const char *name; void (*func)(void); @@ -269,6 +322,7 @@ static struct { { "enumerate (stsch)", test_enumerate }, { "enable (msch)", test_enable }, { "sense (ssch/tsch)", test_sense }, + { "ping-pong (ssch/tsch)", test_ping }, { NULL, NULL } };