From patchwork Sun Apr 26 11:47:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11510501 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BAD48912 for ; Sun, 26 Apr 2020 11:49:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 99C09206CD for ; Sun, 26 Apr 2020 11:49:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="FaZlDv7o" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726146AbgDZLtr (ORCPT ); Sun, 26 Apr 2020 07:49:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726141AbgDZLtr (ORCPT ); Sun, 26 Apr 2020 07:49:47 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07B55C061A0E; Sun, 26 Apr 2020 04:49:47 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id C8E7020CE1; Sun, 26 Apr 2020 11:49:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1587901786; bh=+LuT/3nibUCM17C8SmPQvIp+cZqdd+HnPCvu3yrweao=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FaZlDv7ogslBt+SfhBIGZQF6TmNg8cTLECx4nz4JMIWMAPggx1fyhgGhI9U5GFkhq hrIvAAYmq967Zyf4yFW2xXYN9qWH4h8smKa9o9ijgHoGZXof35m3wPPzCpbhbY/vjX g8klxKJiW5+F56WkCgjqnS6zfe0STDHy1jc5PDd0i3KY0l0Zv/1x0NfZNRwWSm+gBR 6CV5AYdOPfJwe181gZsbWcfYxaSVPUcJ3ZeVji/DBirZwuJKVFyzg2BdarBe7AToen DVKqvsWQMBOrI6rEhbgZEYH+d+lGhktqkRUMloHm+buPatroG7AE/s6BDK1VBDgQhs W+a1AhkWjx6dw== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Paul Burton , Serge Semin , Thomas Gleixner , Stephen Kitt , Nick Desaulniers , Andrew Morton , Anshuman Khandual , Geert Uytterhoeven , Vlastimil Babka , Daniel Silsby , Mike Rapoport , Paul Cercueil , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mark Tomlinson , Greg Kroah-Hartman , Allison Randal , Tiezhu Yang , Wei Xu , John Garry , linux-kernel@vger.kernel.org Subject: [PATCH 1/4] MIPS: Massage address spaces headers Date: Sun, 26 Apr 2020 19:47:34 +0800 Message-Id: <20200426114806.1176629-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> References: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org That would allow us modify kernel vm address spaces without step into the hell of includes. Also use some marcos for address spaces to make spaces.h more clear. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/addrspace.h | 4 +-- arch/mips/include/asm/mach-generic/spaces.h | 33 ++++++++++++++------- arch/mips/include/asm/page-def.h | 28 +++++++++++++++++ arch/mips/include/asm/page.h | 21 ------------- arch/mips/include/asm/pgtable-32.h | 2 -- arch/mips/include/asm/pgtable-64.h | 10 ++----- arch/mips/include/asm/sync.h | 2 ++ arch/mips/kernel/cps-vec.S | 3 +- arch/mips/lib/uncached.c | 6 ++-- 9 files changed, 60 insertions(+), 49 deletions(-) create mode 100644 arch/mips/include/asm/page-def.h diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 59a48c60a065..4fa8ee48ef02 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -10,7 +10,7 @@ #ifndef _ASM_ADDRSPACE_H #define _ASM_ADDRSPACE_H -#include +#include /* * Configure language @@ -67,7 +67,7 @@ #define XKSEG _CONST64_(0xc000000000000000) #define CKSEG0 _CONST64_(0xffffffff80000000) #define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG2 _CONST64_(0xffffffffc0000000) #define CKSEG3 _CONST64_(0xffffffffe0000000) #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index ee5ebe98f6cf..89162740951a 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -10,9 +10,9 @@ #ifndef _ASM_MACH_GENERIC_SPACES_H #define _ASM_MACH_GENERIC_SPACES_H -#include - +#include #include +#include /* * This gives the physical RAM offset. @@ -29,20 +29,20 @@ #ifdef CONFIG_KVM_GUEST #define CAC_BASE _AC(0x40000000, UL) #else -#define CAC_BASE _AC(0x80000000, UL) +#define CAC_BASE CKSEG0 #endif #ifndef IO_BASE -#define IO_BASE _AC(0xa0000000, UL) +#define IO_BASE CKSEG1 #endif #ifndef UNCAC_BASE -#define UNCAC_BASE _AC(0xa0000000, UL) +#define UNCAC_BASE CKSEG1 #endif #ifndef MAP_BASE #ifdef CONFIG_KVM_GUEST #define MAP_BASE _AC(0x60000000, UL) #else -#define MAP_BASE _AC(0xc0000000, UL) +#define MAP_BASE CKSEG2 #endif #endif @@ -58,19 +58,19 @@ #ifdef CONFIG_64BIT #ifndef CAC_BASE -#define CAC_BASE PHYS_TO_XKPHYS(read_c0_config() & CONF_CM_CMASK, 0) +#define CAC_BASE PHYS_TO_XKPHYS(read_c0_config() & CONF_CM_CMASK, 0) #endif #ifndef IO_BASE -#define IO_BASE _AC(0x9000000000000000, UL) +#define IO_BASE PHYS_TO_XKPHYS(K_CALG_UNCACHED, 0) #endif #ifndef UNCAC_BASE -#define UNCAC_BASE _AC(0x9000000000000000, UL) +#define UNCAC_BASE PHYS_TO_XKPHYS(K_CALG_UNCACHED, 0) #endif #ifndef MAP_BASE -#define MAP_BASE _AC(0xc000000000000000, UL) +#define MAP_BASE XKSEG #endif /* @@ -99,8 +99,19 @@ #ifdef CONFIG_KVM_GUEST #define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000) #else -#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) +#define FIXADDR_TOP (CKSEG3 + 0x1ffe0000) +#endif #endif + +#ifdef CONFIG_64BIT +/* + * TLB refill handlers also map the vmalloc area into xuseg. Avoid + * the first couple of pages so NULL pointer dereferences will still + * reliably trap. + */ +#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE)) +#else +#define VMALLOC_START MAP_BASE #endif #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/arch/mips/include/asm/page-def.h b/arch/mips/include/asm/page-def.h new file mode 100644 index 000000000000..a0110bcff7b3 --- /dev/null +++ b/arch/mips/include/asm/page-def.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_PAGE_DEF_H +#define __ASM_PAGE_DEF_H + +#include +/* + * PAGE_SHIFT determines the page size + */ +#ifdef CONFIG_PAGE_SIZE_4KB +#define PAGE_SHIFT 12 +#endif +#ifdef CONFIG_PAGE_SIZE_8KB +#define PAGE_SHIFT 13 +#endif +#ifdef CONFIG_PAGE_SIZE_16KB +#define PAGE_SHIFT 14 +#endif +#ifdef CONFIG_PAGE_SIZE_32KB +#define PAGE_SHIFT 15 +#endif +#ifdef CONFIG_PAGE_SIZE_64KB +#define PAGE_SHIFT 16 +#endif +#define PAGE_SIZE (_AC(1 ,UL) << PAGE_SHIFT) +#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) + +#endif /* __ASM_PAGE_DEF_H */ + diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index e2f503fc7a84..07f6a55eec5d 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -14,27 +14,6 @@ #include #include -/* - * PAGE_SHIFT determines the page size - */ -#ifdef CONFIG_PAGE_SIZE_4KB -#define PAGE_SHIFT 12 -#endif -#ifdef CONFIG_PAGE_SIZE_8KB -#define PAGE_SHIFT 13 -#endif -#ifdef CONFIG_PAGE_SIZE_16KB -#define PAGE_SHIFT 14 -#endif -#ifdef CONFIG_PAGE_SIZE_32KB -#define PAGE_SHIFT 15 -#endif -#ifdef CONFIG_PAGE_SIZE_64KB -#define PAGE_SHIFT 16 -#endif -#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) -#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) - /* * This is used for calculating the real page sizes * for FTLB or VTLB + FTLB configurations. diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 1945c8970141..40049fda596b 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -95,8 +95,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0UL -#define VMALLOC_START MAP_BASE - #define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1)) #define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP) diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index ee5dc0c145b9..037aec0a14de 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -139,21 +139,15 @@ #define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1) #define FIRST_USER_ADDRESS 0UL -/* - * TLB refill handlers also map the vmalloc area into xuseg. Avoid - * the first couple of pages so NULL pointer dereferences will still - * reliably trap. - */ -#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE)) #define VMALLOC_END \ (MAP_BASE + \ min(PTRS_PER_PGD * PTRS_PER_PUD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ (1UL << cpu_vmbits)) - (1UL << 32)) #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ - VMALLOC_START != CKSSEG + VMALLOC_START != CKSEG2 /* Load modules into 32bit-compatible segment. */ -#define MODULE_START CKSSEG +#define MODULE_START CKSEG2 #define MODULE_END (FIXADDR_START-2*PAGE_SIZE) #endif diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h index aabd097933fe..8b297255854b 100644 --- a/arch/mips/include/asm/sync.h +++ b/arch/mips/include/asm/sync.h @@ -2,6 +2,8 @@ #ifndef __MIPS_ASM_SYNC_H__ #define __MIPS_ASM_SYNC_H__ +#include + /* * sync types are defined by the MIPS64 Instruction Set documentation in Volume * II-A of the MIPS Architecture Reference Manual, which can be found here: diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 4db7ff055c9f..ba5e89825308 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -4,7 +4,8 @@ * Author: Paul Burton */ -#include +#include + #include #include #include diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c index 09d5deea747f..5736f3f4c24f 100644 --- a/arch/mips/lib/uncached.c +++ b/arch/mips/lib/uncached.c @@ -9,13 +9,11 @@ */ -#include +#include + #include #include -#ifndef CKSEG2 -#define CKSEG2 CKSSEG -#endif #ifndef TO_PHYS_MASK #define TO_PHYS_MASK -1 #endif From patchwork Sun Apr 26 11:47:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11510503 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F171714DD for ; Sun, 26 Apr 2020 11:50:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D437C2087E for ; Sun, 26 Apr 2020 11:50:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="VvF+PBBA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726144AbgDZLuQ (ORCPT ); Sun, 26 Apr 2020 07:50:16 -0400 Received: from vultr.net.flygoat.com ([149.28.68.211]:59850 "EHLO vultr.net.flygoat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726137AbgDZLuQ (ORCPT ); Sun, 26 Apr 2020 07:50:16 -0400 Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 1F2E920CE3; Sun, 26 Apr 2020 11:50:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1587901816; bh=NhkIJM5ytGNsFposU59z17fTPYd5dTJxh4b7v1FBF2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VvF+PBBAozDTyWbQJJpp2sjGudz/CPnv6IVZm4rr0qSVWvUZsYvMoS6Dgox9x74WE Jslqst6ME2TL1dib5VSnp6hkFLBuJU88jxacFgokkZfeQ3NLd67dp+IIBogJwkpjsM GIzq2qZxYUdjTpjkY9ldprhzFvnCTI5XQzjwLKyhYq88GnZ0Ds5mY4Y+N3OkH8Vf8E TQ24iRIRddVdB0zpJjDsuEq9GCWayx7uqdDM1Y5SQ5NsHZauDzQjY2RcVAfTjHo54a DvkUdc22rDnCuJl1LSMKHykO4bPc9mt+RvyUJ8zXhyXiIxkHgGsN9qycreCxL0hDL8 2o8leaCarSEHQ== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Paul Burton , Thomas Gleixner , Nathan Chancellor , Stephen Kitt , Serge Semin , Nick Desaulniers , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Anshuman Khandual , Geert Uytterhoeven , Paul Cercueil , Mike Rapoport , Daniel Silsby , Mark Tomlinson , Greg Kroah-Hartman , Allison Randal , Tiezhu Yang , John Garry , Wei Xu , linux-kernel@vger.kernel.org Subject: [PATCH 2/4] MIPS: Introduce PCI_IO_VMMAP Date: Sun, 26 Apr 2020 19:47:35 +0800 Message-Id: <20200426114806.1176629-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> References: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Define PCI_IOBASE for MIPS at the strat of kernel mapping segment. That would allow virt address of I/O ports to be dynamicly mapped. So we'll be able to combine multiple MMIO ranges into I/O ports and thus we can take advantage of logic_pio mechanism. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 3 ++ arch/mips/include/asm/io.h | 36 ++++++++++++++++----- arch/mips/include/asm/mach-generic/spaces.h | 13 ++++++-- arch/mips/kernel/setup.c | 2 ++ arch/mips/lib/iomap-pci.c | 2 +- 5 files changed, 45 insertions(+), 11 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0519ca9f00f9..4e5308178649 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3149,6 +3149,9 @@ config PCI_DRIVERS_LEGACY select NO_GENERIC_PCI_IOPORT_MAP select PCI_DOMAINS if PCI +config PCI_IO_VMMAP + def_bool n + # # ISA support is now enabled via select. Too many systems still have the one # or other ISA chip on the board that users don't know about so don't expect diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 346fffd9e972..f15ddcd27f35 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -51,17 +51,36 @@ /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ +/* + * On MIPS I/O ports are memory mapped, so we access them using normal + * load/store instructions. + */ +#ifdef CONFIG_PCI_IO_VMMAP +/* + * I/O port access primitives for dymatic I/O ports mapping. + * + * We'll create kmap for I/O ports in this space. + */ +#define arch_has_dev_port() (1) +#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) +#define PCI_IOBASE ((void __iomem *)PCI_IO_START) +#define IOPORT_RW_BASE PCI_IO_START + +#else + #define IO_SPACE_LIMIT 0xffff /* - * On MIPS I/O ports are memory mapped, so we access them using normal - * load/store instructions. mips_io_port_base is the virtual address to - * which all ports are being mapped. For sake of efficiency some code - * assumes that this is an address that can be loaded with a single lui - * instruction, so the lower 16 bits must be zero. Should be true on - * on any sane architecture; generic code does not use this assumption. + * I/O port access primitives for fixed I/O ports mapping. + * + * mips_io_port_base is the virtual address to which all ports are + * being mapped. For sake of efficiency some code assumes that this + * is an address that can be loaded with a single lui, instruction, so + * the lower 16 bits must be zero. Should be true on on any sane architecture; + * generic code does not use this assumption. */ extern unsigned long mips_io_port_base; +#define IOPORT_RW_BASE mips_io_port_base static inline void set_io_port_base(unsigned long base) { @@ -78,6 +97,7 @@ static inline void set_io_port_base(unsigned long base) #define PIO_OFFSET mips_io_port_base #define PIO_MASK IO_SPACE_LIMIT #define PIO_RESERVED 0x0UL +#endif /* * Enforce in-order execution of data I/O. In the MIPS architecture @@ -308,7 +328,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ else \ war_io_reorder_wmb(); \ \ - __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \ \ __val = pfx##ioswab##bwlq(__addr, val); \ \ @@ -323,7 +343,7 @@ static inline type pfx##in##bwlq##p(unsigned long port) \ volatile type *__addr; \ type __val; \ \ - __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \ \ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ \ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index 89162740951a..a39714c5fd7b 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -103,15 +103,24 @@ #endif #endif +#ifdef CONFIG_PCI_IO_VMMAP +#define PCI_IO_SIZE SZ_16M +#else +#define PCI_IO_SIZE 0 +#endif + #ifdef CONFIG_64BIT /* * TLB refill handlers also map the vmalloc area into xuseg. Avoid * the first couple of pages so NULL pointer dereferences will still * reliably trap. */ -#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE)) +#define PCI_IO_START (MAP_BASE + (2 * PAGE_SIZE)) #else -#define VMALLOC_START MAP_BASE +#define PCI_IO_START MAP_BASE #endif +#define PCI_IO_END (PCI_IO_START + PCI_IO_SIZE) +#define VMALLOC_START PCI_IO_END + #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 8db533cd816c..99225539de3c 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -73,12 +73,14 @@ static const char builtin_cmdline[] __initconst = CONFIG_CMDLINE; static const char builtin_cmdline[] __initconst = ""; #endif +#ifndef CONFIG_PCI_IO_VMMAP /* * mips_io_port_base is the begin of the address space to which x86 style * I/O ports are mapped. */ unsigned long mips_io_port_base = -1; EXPORT_SYMBOL(mips_io_port_base); +#endif static struct resource code_resource = { .name = "Kernel code", }; static struct resource data_resource = { .name = "Kernel data", }; diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c index 210f5a95ecb1..f28924aaac1d 100644 --- a/arch/mips/lib/iomap-pci.c +++ b/arch/mips/lib/iomap-pci.c @@ -27,7 +27,7 @@ void __iomem *__pci_ioport_map(struct pci_dev *dev, while (bus->parent) bus = bus->parent; - ctrl->io_map_base = base = mips_io_port_base; + ctrl->io_map_base = base = IOPORT_RW_BASE; sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number); printk(KERN_WARNING "io_map_base of root PCI bus %s unset. " From patchwork Sun Apr 26 11:47:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11510505 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B78A8912 for ; Sun, 26 Apr 2020 11:50:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A050F208FE for ; Sun, 26 Apr 2020 11:50:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="nq2CSnz9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726162AbgDZLup (ORCPT ); Sun, 26 Apr 2020 07:50:45 -0400 Received: from vultr.net.flygoat.com ([149.28.68.211]:59902 "EHLO vultr.net.flygoat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726131AbgDZLup (ORCPT ); Sun, 26 Apr 2020 07:50:45 -0400 Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 0925920CE5; Sun, 26 Apr 2020 11:50:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1587901844; bh=JH5fmaVAU3zVjpRZJe3S98l22Af+YjDXkuSE9/t9KHI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nq2CSnz9kzmXuDisFD3lv+o6xbKbvM5qsWLOTHxUqlSVbcVga3JA5BWa90lENTLX5 0NNMV0r4glJaZwe6HfhvoJmANWGj7mkMxYd/BVxNTTG5aRqgcJyW5/PnM65YZo8/AD girea5tWjHOO8+WrvZN8O6nxPlzubhy/LQy7zFrXBcOx4VBKegCfQnP1yY1U+lVy3d tmj4G6COah4gLB21nb0kNUBONrKXn3yJfhsh2vYnnMyikH+jgDHWtvzqqM1XUGkHyh BSWrtY0fkbYhtw53WuBPTZg6aynxb833bt+/t+LWWRNMMm8UuwZtk9HVh5lBY4zTO8 ftWbszQZBm4MQ== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Paul Burton , Thomas Gleixner , Stephen Kitt , Nick Desaulniers , Serge Semin , Anshuman Khandual , Geert Uytterhoeven , Andrew Morton , Daniel Silsby , Mike Rapoport , Paul Cercueil , Mark Tomlinson , Greg Kroah-Hartman , Allison Randal , Tiezhu Yang , John Garry , Wei Xu , linux-kernel@vger.kernel.org Subject: [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED Date: Sun, 26 Apr 2020 19:47:36 +0800 Message-Id: <20200426114806.1176629-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> References: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org That would allow platforms reserve some lower address in PIO MMIO range to deal with legacy drivers with hardcoded I/O ports that can't be managed by logic_pio. Signed-off-by: Jiaxun Yang --- lib/logic_pio.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/logic_pio.c b/lib/logic_pio.c index f511a99bb389..57fff1cb7063 100644 --- a/lib/logic_pio.c +++ b/lib/logic_pio.c @@ -20,6 +20,10 @@ static LIST_HEAD(io_range_list); static DEFINE_MUTEX(io_range_mutex); +#ifndef MMIO_LOWER_RESERVED +#define MMIO_LOWER_RESERVED 0 +#endif + /* Consider a kernel general helper for this */ #define in_range(b, first, len) ((b) >= (first) && (b) < (first) + (len)) @@ -36,7 +40,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range) struct logic_pio_hwaddr *range; resource_size_t start; resource_size_t end; - resource_size_t mmio_end = 0; + resource_size_t mmio_end = MMIO_LOWER_RESERVED; resource_size_t iio_sz = MMIO_UPPER_LIMIT; int ret = 0; From patchwork Sun Apr 26 11:47:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11510507 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E38114DD for ; Sun, 26 Apr 2020 11:51:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 366672084D for ; Sun, 26 Apr 2020 11:51:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="QpyOxyFt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726154AbgDZLvQ (ORCPT ); Sun, 26 Apr 2020 07:51:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726135AbgDZLvP (ORCPT ); Sun, 26 Apr 2020 07:51:15 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C71BC061A0E; Sun, 26 Apr 2020 04:51:15 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 18F8420CE7; Sun, 26 Apr 2020 11:51:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1587901875; bh=FIpkVgCcZIOSR5LDhY/QsB4UvPKGRBmMbi5Ln6/hcIA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QpyOxyFtVI9AhdwU/EaFyuJLre0YiMrOJR0N9E5ACBf3t3cAamMrKv1Numq1ZYnSg UNd1r3qGxmz1+UjGqIPmYlXNHhxNniEg/7Q1Tngn+hkS9UYJC3JOBdcsi12mBBQZoy HYY1RvPxMU9zuPuA3RL1RHBacPUF3aTZQkUxyW6t1g9NnYz/ZySf/oTuflKjsrzVgL HYYKp2NFhYIQU1bMCapxhBZKH4eYLvClvEEpMMUPGHrNIhXQBa3U8J8mJISSWsdmhE n94sJoMn2WP+OYWD/0pF7C80f0HHwAawkSyuq8GT4doBiZGRd5fLbpAK7k58zmCekV cLW7rxDJBp5Ew== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Paul Burton , Stephen Kitt , Andrew Morton , Nick Desaulniers , Serge Semin , Geert Uytterhoeven , Anshuman Khandual , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Mike Rapoport , Daniel Silsby , Paul Cercueil , Mark Tomlinson , Greg Kroah-Hartman , Allison Randal , Thomas Gleixner , Tiezhu Yang , Wei Xu , John Garry , linux-kernel@vger.kernel.org Subject: [PATCH 4/4] MIPS: Loongson64: Enable PCI_IO_VMMAP Date: Sun, 26 Apr 2020 19:47:37 +0800 Message-Id: <20200426114806.1176629-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> References: <20200426114806.1176629-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Finally we are able to elegantly add I/O ports for PCI host bridge via devicetree with logic_pio. To deal with legacy drivers that have fixed I/O ports range we reserved 0x10000 in PCI_IOBASE, should be enough for i8259 i8042 stuff. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 1 + arch/mips/include/asm/io.h | 4 ++++ arch/mips/loongson64/init.c | 12 ++++++++---- arch/mips/loongson64/pci.c | 2 +- 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4e5308178649..1669735dacd8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -479,6 +479,7 @@ config MACH_LOONGSON64 select I8259 select IRQ_MIPS_CPU select NR_CPUS_DEFAULT_64 + select PCI_IO_VMMAP select USE_GENERIC_EARLY_PRINTK_8250 select SYS_HAS_CPU_LOONGSON64 select SYS_HAS_EARLY_PRINTK diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index f15ddcd27f35..7f9716c95aa0 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -66,6 +66,10 @@ #define PCI_IOBASE ((void __iomem *)PCI_IO_START) #define IOPORT_RW_BASE PCI_IO_START +#ifdef CONFIG_MACH_LOONGSON64 +#define MMIO_LOWER_RESERVED 0x10000 +#endif + #else #define IO_SPACE_LIMIT 0xffff diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index da38944471f4..3117edbbea46 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -29,10 +29,6 @@ void __init prom_init(void) fw_init_cmdline(); prom_init_env(); - /* init base address of io space */ - set_io_port_base((unsigned long) - ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); - prom_init_numa_memory(); /* Hardcode to CPU UART 0 */ @@ -48,5 +44,13 @@ void __init prom_free_prom_memory(void) void __init arch_init_irq(void) { + /* + * i8259 would access I/O space, so mapping must be done here. + * Please remove it when all drivers can be managed by logic_pio. + */ + ioremap_page_range(PCI_IO_START, PCI_IO_START + MMIO_LOWER_RESERVED, + LOONGSON_PCIIO_BASE, + pgprot_device(PAGE_KERNEL)); + irqchip_init(); } diff --git a/arch/mips/loongson64/pci.c b/arch/mips/loongson64/pci.c index a440a2725a20..7aecb88dd377 100644 --- a/arch/mips/loongson64/pci.c +++ b/arch/mips/loongson64/pci.c @@ -37,7 +37,7 @@ extern int sbx00_acpi_init(void); static int __init pcibios_init(void) { - loongson_pci_controller.io_map_base = mips_io_port_base; + loongson_pci_controller.io_map_base = IOPORT_RW_BASE; loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr; loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;