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envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index bc80aa87cf..ed64190386 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -456,7 +456,7 @@ restart: hwaddr vbase; /* Do the second stage translation on the base PTE address. */ - get_physical_address(env, &vbase, &vbase_prot, base, access_type, + get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD, mmu_idx, false, true); pte_addr = vbase + idx * ptesize; From patchwork Sun Apr 26 16:19:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510713 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22F8C92A for ; Sun, 26 Apr 2020 16:28:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ECF9E206DD for ; Sun, 26 Apr 2020 16:28:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="DNrXkdz6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ECF9E206DD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; 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27 Apr 2020 00:27:27 +0800 IronPort-SDR: 9FyCwXhaLW6G8MGHEz7oRwmapjp8NBD3tQj/zNG9mz/cIxADrrIls95NQJFPxKZen/ch6sTb/G xmVxCbb13S4LOUNNTGS1f9sAmrtnjRaH8= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:17:37 -0700 IronPort-SDR: LstrtwSbw/bLUwrSBVx8Bz9cGT1zB2IRGhvmuvouBicWkjKBo1XzL4Y2SBxAT/Fdv8uuPazBGw AKikpW51UrQw== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip02.wdc.com with ESMTP; 26 Apr 2020 09:27:27 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs Date: Sun, 26 Apr 2020 09:19:16 -0700 Message-Id: <416aa978887e9f86307616189207a5b015f8e82e.1587917657.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ed64190386..0d4a7b752d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -456,8 +456,13 @@ restart: hwaddr vbase; /* Do the second stage translation on the base PTE address. */ - get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD, - mmu_idx, false, true); + int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, + base, MMU_DATA_LOAD, + mmu_idx, false, true); + + if (vbase_ret != TRANSLATE_SUCCESS) { + return vbase_ret; + } pte_addr = vbase + idx * ptesize; } else { From patchwork Sun Apr 26 16:19:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510715 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8986014DD for ; Sun, 26 Apr 2020 16:28:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5FA66206DD for ; Sun, 26 Apr 2020 16:28:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="Ub76s5jv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5FA66206DD Authentication-Results: mail.kernel.org; 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27 Apr 2020 00:27:30 +0800 IronPort-SDR: kkH9iceGJRVrSHjesfGdz8zgA85Hxg8BFT2C+4cnF0mswAOL3t1CobTbWibX7IBqN9X5W3d8Rs e+6Jez56/aLIOrO7ZOKEB8pmSIhBk4FJE= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:17:40 -0700 IronPort-SDR: /P67STBwE2Xrd7m1swM+tD4yMzlhOckSp9DE6oAjcBp41xvurO0A6+zF7AUOlbK8NnJCzi1RCi GyG7DaYCjhdg== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip02.wdc.com with ESMTP; 26 Apr 2020 09:27:30 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 03/15] target/riscv: Move the hfence instructions to the rvh decode Date: Sun, 26 Apr 2020 09:19:19 -0700 Message-Id: <59e67210a356f9ccc3e62bf56ba8b4a819f05f45.1587917657.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 +- .../riscv/insn_trans/trans_privileged.inc.c | 40 ------------- target/riscv/insn_trans/trans_rvh.inc.c | 57 +++++++++++++++++++ target/riscv/translate.c | 1 + 4 files changed, 62 insertions(+), 42 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b883672e63..05266f5a36 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -77,8 +77,6 @@ uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 -hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma -hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm @@ -207,3 +205,7 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm + +# *** RV32H Base Instruction Set *** +hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma +hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c index 76c2fad71c..c187ead774 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -103,43 +103,3 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) #endif return false; } - -static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) -{ -#ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv == PRV_M || - * (env->priv == PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } -#endif - return false; -} - -static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) -{ -#ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv == PRV_M || - * (env->priv == PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } -#endif - return false; -} diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c new file mode 100644 index 0000000000..2e91d6ae57 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -0,0 +1,57 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2020 Western Digital + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv == PRV_M || + * (env->priv == PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} + +static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv == PRV_M || + * (env->priv == PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 43bf7e39a6..ce71ca7a92 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -711,6 +711,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" #include "insn_trans/trans_rvd.inc.c" +#include "insn_trans/trans_rvh.inc.c" #include "insn_trans/trans_privileged.inc.c" /* Include the auto-generated decoder for 16 bit insn */ From patchwork Sun Apr 26 16:19:23 2020 Content-Type: text/plain; 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26 Apr 2020 09:27:33 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 04/15] target/riscv: Implement checks for hfence Date: Sun, 26 Apr 2020 09:19:23 -0700 Message-Id: <00639bbec729905cd9ac785447b78b8e2e05b275.1587917657.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:33 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Signed-off-by: Alistair Francis --- target/riscv/helper.h | 5 ++++ target/riscv/insn_trans/trans_rvh.inc.c | 32 +++++-------------------- target/riscv/op_helper.c | 13 ++++++++++ 3 files changed, 24 insertions(+), 26 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index debb22a480..b36be978d5 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -76,3 +76,8 @@ DEF_HELPER_2(mret, tl, env, tl) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif + +/* Hypervisor functions */ +#ifndef CONFIG_USER_ONLY +DEF_HELPER_1(hyp_tlb_flush, void, env) +#endif diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c index 2e91d6ae57..60978f2fa5 100644 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -18,40 +18,20 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { + REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv == PRV_M || - * (env->priv == PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } + gen_helper_hyp_tlb_flush(cpu_env); + return true; #endif return false; } static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) { + REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv == PRV_M || - * (env->priv == PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } + gen_helper_hyp_tlb_flush(cpu_env); + return true; #endif return false; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c6412f680c..53dca7128d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -201,4 +201,17 @@ void helper_tlb_flush(CPURISCVState *env) } } +void helper_hyp_tlb_flush(CPURISCVState *env) +{ + CPUState *cs = env_cpu(env); + + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) { + tlb_flush(cs); + return; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); +} + #endif /* !CONFIG_USER_ONLY */ From patchwork Sun Apr 26 16:19:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8FE5413B2 for ; Sun, 26 Apr 2020 16:30:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6575620700 for ; Sun, 26 Apr 2020 16:30:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="KwgK+91W" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6575620700 Authentication-Results: mail.kernel.org; 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27 Apr 2020 00:27:37 +0800 IronPort-SDR: D6GXHfKLaAGKe68MTHqU8wGILDqrRCuuiCr8rI1e98LAR1xoOWEGAiThQDXivKaRE3aj3JRJtb vJZ9gGgRUTTCa/YDbkfDipmt8/DmYyRj8= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:18:19 -0700 IronPort-SDR: OS9xMFmjjTKnWZ2rO50f8f+DXqMsu88rHKweqKfW/xjy5uC9tkXzx2tPTKvA45iXHHaU1rPM53 vQoPawoCLe8w== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip02.wdc.com with ESMTP; 26 Apr 2020 09:27:36 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status Date: Sun, 26 Apr 2020 09:19:26 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:33 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e7f5b9c5..e44a7a91e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -302,6 +302,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(CPURISCVState *env); +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7f64ee1174..f52711ac32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -452,6 +452,7 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 +#define HS_TWO_STAGE 4 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0d4a7b752d..075675c59c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); } +bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, HS_TWO_STAGE); +} + +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt = set_field(env->virt, HS_TWO_STAGE, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env; From patchwork Sun Apr 26 16:19:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D467E912 for ; Sun, 26 Apr 2020 16:31:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9874D20700 for ; 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d="scan'208";a="137626676" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 27 Apr 2020 00:27:40 +0800 IronPort-SDR: 0veoq64zi42SVQfGZ63jarSur4sWZT7ZTYbwOqq90NIoChmkXZBJcMtpfUDfN3O6jSHD9V8I30 Q0hoehzBcqPAQqJ7g2A6mkOPDL9IKrsU0= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:18:22 -0700 IronPort-SDR: w5S5hsnsrRSabRAdnVYDet+HJild6jKTPgebqqsvkYL7F7N/EYGYZMUJJjmlny1oxcxz5P5NH5 ldXoTcom+jdQ== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip02.wdc.com with ESMTP; 26 Apr 2020 09:27:39 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 06/15] target/riscv: Allow generating hlv/hlvx/hsv instructions Date: Sun, 26 Apr 2020 09:19:29 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:33 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32-64.decode | 5 + target/riscv/insn32.decode | 11 + target/riscv/insn_trans/trans_rvh.inc.c | 340 ++++++++++++++++++++++++ target/riscv/op_helper.c | 114 ++++++++ 6 files changed, 474 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f52711ac32..bb4ee3fc35 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -428,6 +428,7 @@ #define HSTATUS_SP2V 0x00000200 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HU 0x00000200 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b36be978d5..d020d1459c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -80,4 +80,7 @@ DEF_HELPER_1(tlb_flush, void, env) /* Hypervisor functions */ #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) +DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) +DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) +DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 380bf791bc..24feef4e0f 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -70,3 +70,8 @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 + +# *** RV32H Base Instruction Set *** +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 05266f5a36..d87c6ba122 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -62,6 +62,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd +@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -207,5 +208,15 @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm # *** RV32H Base Instruction Set *** +hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 +hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 +hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 +hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 +hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 +hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 +hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 +hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s +hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s +hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c index 60978f2fa5..a2bf4b6c50 100644 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -16,6 +16,346 @@ * this program. If not, see . */ +static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_UB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +#ifdef TARGET_RISCV64 +static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} +#endif + +static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 53dca7128d..d7f26b22f3 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -214,4 +214,118 @@ void helper_hyp_tlb_flush(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } +target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + pte = cpu_ldsb_data(env, address); + break; + case MO_UB: + pte = cpu_ldub_data(env, address); + break; + case MO_TESW: + pte = cpu_ldsw_data(env, address); + break; + case MO_TEUW: + pte = cpu_lduw_data(env, address); + break; + case MO_TESL: + pte = cpu_ldl_data(env, address); + break; + case MO_TEUL: + pte = cpu_ldl_data(env, address); + break; + case MO_TEQ: + pte = cpu_ldq_data(env, address); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + +void helper_hyp_store(CPURISCVState *env, target_ulong address, + target_ulong val, target_ulong attrs, target_ulong memop) +{ + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + case MO_UB: + cpu_stb_data(env, address, val); + break; + case MO_TESW: + case MO_TEUW: + cpu_stw_data(env, address, val); + break; + case MO_TESL: + case MO_TEUL: + cpu_stl_data(env, address, val); + break; + case MO_TEQ: + cpu_stq_data(env, address, val); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); +} + +target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_TEUL: + pte = cpu_ldub_data(env, address); + break; + case MO_TEUW: + pte = cpu_lduw_data(env, address); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + #endif /* !CONFIG_USER_ONLY */ From patchwork Sun Apr 26 16:19:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510733 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3BBD1912 for ; Sun, 26 Apr 2020 16:36:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 103622080C for ; Sun, 26 Apr 2020 16:36:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="iXiRGLOU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 103622080C Authentication-Results: mail.kernel.org; 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27 Apr 2020 00:27:42 +0800 IronPort-SDR: h0ln9wSw3OvTdPsgM3d4FXT2n3w6rJi1XyRGi23AJxHgxyuCSQwwolWjuiPwcBEWd21J8oNsou jNXoyHBfrq8brH3CwEVXQ5OHCEb8HmNLk= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:18:25 -0700 IronPort-SDR: 5gFv1QW0g9vV6pmVOgE2xBzPSx7ESy3gcvOaBROlG20RaxiPNoqT2jpCDdSHijiTpi5/gW8BCf Cn3pKhqj8NAg== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip02.wdc.com with ESMTP; 26 Apr 2020 09:27:42 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions Date: Sun, 26 Apr 2020 09:19:31 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:33 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 54 +++++++++++++++------------------------ 1 file changed, 21 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 075675c59c..2ac599505f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ + if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) { + use_background = true; + } + if (mode == PRV_M && access_type != MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); - - if (riscv_has_ext(env, RVH) && - MSTATUS_MPV_ISSET(env)) { - use_background = true; - } - } - } - - if (mode == PRV_S && access_type != MMU_INST_FETCH && - riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { - if (get_field(env->hstatus, HSTATUS_SPRV)) { - mode = get_field(env->mstatus, SSTATUS_SPP); - use_background = true; } } @@ -727,8 +718,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, hwaddr pa = 0; int prot, prot2; bool pmp_violation = false; - bool m_mode_two_stage = false; - bool hs_mode_two_stage = false; bool first_stage_error = true; int ret = TRANSLATE_FAIL; int mode = mmu_idx; @@ -738,30 +727,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); - /* - * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is - * set and we want to access a virtulisation address. - */ - if (riscv_has_ext(env, RVH)) { - m_mode_two_stage = env->priv == PRV_M && - access_type != MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env); - - hs_mode_two_stage = env->priv == PRV_S && - !riscv_cpu_virt_enabled(env) && - access_type != MMU_INST_FETCH && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV); - } - if (mode == PRV_M && access_type != MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); } } - if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { + if (riscv_has_ext(env, RVH) && env->priv == PRV_M && + access_type != MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, true); + } + + if (riscv_cpu_virt_enabled(env) || + (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) { /* Two stage lookup */ ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, true, true); @@ -813,6 +793,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, __func__, address, ret, pa, prot); } + /* We did the two stage lookup based on MPRV, unset the lookup */ + if (riscv_has_ext(env, RVH) && env->priv == PRV_M && + access_type != MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, false); + } + if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { From patchwork Sun Apr 26 16:19:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4E39912 for ; Sun, 26 Apr 2020 16:38:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A3C220700 for ; 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envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:33 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/csr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 11d184cd16..88cf0ff600 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -940,7 +940,6 @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) { - env->htinst = val; return 0; } From patchwork Sun Apr 26 16:19:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510731 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BBD3E912 for ; Sun, 26 Apr 2020 16:34:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91A7C20700 for ; Sun, 26 Apr 2020 16:34:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="bqTLlKhD" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 91A7C20700 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; 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27 Apr 2020 00:27:48 +0800 IronPort-SDR: +n2fw6xHpRGgUOxUj5STLGzGMUpOG9kH+d6usis2y5CBgyerL4ZTUN43OZ9ZMJc7ET6L1N2C2u m1SZsoFODy8FcLEu20z1VMUYcS1G6KWO4= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:18:30 -0700 IronPort-SDR: 6SCtEmM9IE2MY2rMGSFPmvfhONyhBvmubHC+2dLm1rqturdaOz0A63TDjVLJ9dygxibZtc2yZp 3wWYMu7r6CZA== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip02.wdc.com with ESMTP; 26 Apr 2020 09:27:47 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 09/15] target/riscv: Convert MSTATUS MTL to GVA Date: Sun, 26 Apr 2020 09:19:37 -0700 Message-Id: <94c8a014597c988cd58a01abab5803004beb7e83.1587917657.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:33 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 5 +++-- target/riscv/cpu_helper.c | 20 ++++++++++++++++---- target/riscv/csr.c | 6 +++--- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bb4ee3fc35..028e268faa 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -364,10 +364,10 @@ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ #if defined(TARGET_RISCV64) -#define MSTATUS_MTL 0x4000000000ULL +#define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL #elif defined(TARGET_RISCV32) -#define MSTATUS_MTL 0x00000040 +#define MSTATUS_GVA 0x00000040 #define MSTATUS_MPV 0x00000080 #endif @@ -429,6 +429,7 @@ #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 +#define HSTATUS_GVA 0x00000040 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2ac599505f..93df7a896d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -914,6 +914,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { target_ulong hdeleg = async ? env->hideleg : env->hedeleg; + if (riscv_cpu_virt_enabled(env) && tval) { + /* + * If we are writing a guest virtual address to stval, set + * this to 1. If we are trapping to VS we will set this to 0 + * later. + */ + env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1); + } + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { /* @@ -924,6 +933,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause == IRQ_VS_EXT) cause = cause - 1; /* Trap to VS mode */ + env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); @@ -973,13 +983,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) #ifdef TARGET_RISCV32 env->mstatush = set_field(env->mstatush, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); - env->mstatush = set_field(env->mstatush, MSTATUS_MTL, - riscv_cpu_force_hs_excep_enabled(env)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1); + } #else env->mstatus = set_field(env->mstatus, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); - env->mstatus = set_field(env->mstatus, MSTATUS_MTL, - riscv_cpu_force_hs_excep_enabled(env)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); + } #endif mtval2 = env->guest_phys_fault_addr; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 88cf0ff600..6b6080592a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -380,10 +380,10 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) MSTATUS_TW; #if defined(TARGET_RISCV64) /* - * RV32: MPV and MTL are not in mstatus. The current plan is to + * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |= MSTATUS_MTL | MSTATUS_MPV; + mask |= MSTATUS_MPV | MSTATUS_GVA; #endif } @@ -410,7 +410,7 @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) tlb_flush(env_cpu(env)); } - val &= MSTATUS_MPV | MSTATUS_MTL; + val &= MSTATUS_MPV | MSTATUS_GVA; env->mstatush = val; From patchwork Sun Apr 26 16:19:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510729 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69EA192A for ; Sun, 26 Apr 2020 16:33:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F8C520700 for ; Sun, 26 Apr 2020 16:33:58 +0000 (UTC) Authentication-Results: mail.kernel.org; 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d="scan'208";a="136193251" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 27 Apr 2020 00:27:50 +0800 IronPort-SDR: H/cTgOQmL6JUxgaTupXXuZ4RSkmLdclbpgydzA6GvdDWOITGYkFSiaKo4HVnaA/5CpOV4lg0sI WMQYmDs4kHP+fB96I4pdZE+QERIssRBqU= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:18:00 -0700 IronPort-SDR: XcfAmeVNywNSdqqv6cjX04wsNOKlz91syYphokrPg4qEAEuHZ2Ws1t7WuuYWa4fc6zBmXeryn+ suXkyOSRvbrw== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip01.wdc.com with ESMTP; 26 Apr 2020 09:27:50 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 10/15] target/riscv: Fix the interrupt cause code Date: Sun, 26 Apr 2020 09:19:39 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 93df7a896d..f7ada23861 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -925,14 +925,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt * no if hypervisor has delegated one of hs mode's interrupt */ if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || - cause == IRQ_VS_EXT) + cause == IRQ_VS_EXT) { cause = cause - 1; - /* Trap to VS mode */ + } env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ From patchwork Sun Apr 26 16:19:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510739 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D9AD92A for ; Sun, 26 Apr 2020 16:39:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E23F820700 for ; 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envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 8 +------- target/riscv/op_helper.c | 8 ++------ target/riscv/translate.c | 10 ---------- 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 028e268faa..6b97c27711 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -430,6 +430,7 @@ #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 #define HSTATUS_GVA 0x00000040 +#define HSTATUS_SPVP 0x00000100 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f7ada23861..84a5b20f56 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -938,9 +938,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); - env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_SPV)); - env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, + env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, get_field(env->mstatus, SSTATUS_SPP)); env->hstatus = set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); @@ -951,10 +949,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_SPV)); - env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, - get_field(env->mstatus, SSTATUS_SPP)); env->hstatus = set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index d7f26b22f3..c94aba78b3 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -98,12 +98,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) prev_priv = get_field(mstatus, MSTATUS_SPP); prev_virt = get_field(hstatus, HSTATUS_SPV); - hstatus = set_field(hstatus, HSTATUS_SPV, - get_field(hstatus, HSTATUS_SP2V)); - mstatus = set_field(mstatus, MSTATUS_SPP, - get_field(hstatus, HSTATUS_SP2P)); - hstatus = set_field(hstatus, HSTATUS_SP2V, 0); - hstatus = set_field(hstatus, HSTATUS_SP2P, 0); + hstatus = set_field(hstatus, HSTATUS_SPV, 0); + mstatus = set_field(mstatus, MSTATUS_SPP, 0); mstatus = set_field(mstatus, SSTATUS_SIE, get_field(mstatus, SSTATUS_SPIE)); mstatus = set_field(mstatus, SSTATUS_SPIE, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ce71ca7a92..1d973b62e9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -754,16 +754,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { ctx->virt_enabled = riscv_cpu_virt_enabled(env); - if (env->priv_ver == PRV_M && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { - ctx->virt_enabled = true; - } else if (env->priv == PRV_S && - !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV)) { - ctx->virt_enabled = true; - } } else { ctx->virt_enabled = false; } From patchwork Sun Apr 26 16:19:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510717 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 73D8014DD for ; Sun, 26 Apr 2020 16:29:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 491A3206DD for ; Sun, 26 Apr 2020 16:29:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="kUYR4SLc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 491A3206DD Authentication-Results: mail.kernel.org; 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27 Apr 2020 00:27:55 +0800 IronPort-SDR: TEfzyvoS1pGT1Gkfd9K6JMXUKCVDdg+cWivK+ysMNYlJCUVAdwXFO8ZBpWX8jgtU2dElp61JY0 ldD1OlGhgO18E3Vux6p01okT5de1cvTCE= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:18:05 -0700 IronPort-SDR: vYfbP9q0nEV6GUU84tc2QuOTnvBbiUASAVZX88RmAbZk3vb3iWB5umraWjTwUQPdCsEFmrVDhg /lQyl9OvfeNg== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip01.wdc.com with ESMTP; 26 Apr 2020 09:27:55 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 12/15] target/riscv: Update the CSRs to the v0.6 Hyp extension Date: Sun, 26 Apr 2020 09:19:45 -0700 Message-Id: <87318882f7b08e93dae29f26d62b1eb823a136d7.1587917657.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6b97c27711..8a145e0a32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -422,15 +422,17 @@ #endif /* hstatus CSR bits */ -#define HSTATUS_SPRV 0x00000001 +#define HSTATUS_VSBE 0x00000020 +#define HSTATUS_GVA 0x00000040 #define HSTATUS_SPV 0x00000080 -#define HSTATUS_SP2P 0x00000100 -#define HSTATUS_SP2V 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_VGEIN 0x0003F000 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_SPVP 0x00000100 +#if defined(TARGET_RISCV64) +#define HSTATUS_VSXL 0x300000000 +#endif #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL From patchwork Sun Apr 26 16:19:48 2020 Content-Type: text/plain; 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26 Apr 2020 09:27:59 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 13/15] target/riscv: Only support a single VSXL length Date: Sun, 26 Apr 2020 09:19:48 -0700 Message-Id: <23c98b0c5a3394ce5a98331069383cdb0a4d095f.1587917657.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/csr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b6080592a..438d0a61ee 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -854,12 +854,21 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->hstatus; +#ifdef TARGET_RISCV64 + /* We only support 64-bit VSXL */ + *val = set_field(*val, HSTATUS_VSXL, 2); +#endif return 0; } static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus = val; +#ifdef TARGET_RISCV64 + if (get_field(val, HSTATUS_VSXL) != 2) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); + } +#endif return 0; } From patchwork Sun Apr 26 16:19:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 11510725 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DA689912 for ; Sun, 26 Apr 2020 16:32:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B04E020700 for ; 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d="scan'208";a="136193262" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 27 Apr 2020 00:28:01 +0800 IronPort-SDR: iKWuPKqilS8S5b+fBXI5lwnzshntvthh2J7I1lwqbj2xxA5PCdj4zWX0t7whdSXxy7R/A1idXP S3PmBIg1tAe3QE1iY4oNDwrrLkohhTWxM= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2020 09:18:11 -0700 IronPort-SDR: MOuZamxbp/QOib8VHHUwrksXZrtQlMy2mZvwsPDAXu5qk3mwvQjpHDt+DnSBfZhDewryVIkP6U Ue4iojcz5d+w== WDCIronportException: Internal Received: from wdthnc17-0189.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.50]) by uls-op-cesaip02.wdc.com with ESMTP; 26 Apr 2020 09:28:01 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 14/15] target/riscv: Only support little endian guests Date: Sun, 26 Apr 2020 09:19:51 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 438d0a61ee..04f3471f2e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -858,6 +858,8 @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) /* We only support 64-bit VSXL */ *val = set_field(*val, HSTATUS_VSXL, 2); #endif + /* We only support little endian */ + *val = set_field(*val, HSTATUS_VSBE, 0); return 0; } @@ -869,6 +871,9 @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); } #endif + if (get_field(val, HSTATUS_VSBE) != 0) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); + } return 0; }