From patchwork Wed Apr 29 14:29:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1576A19A2 for ; Wed, 29 Apr 2020 14:30:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E930221D82 for ; Wed, 29 Apr 2020 14:30:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ue8ZjUE7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726539AbgD2OaQ (ORCPT ); Wed, 29 Apr 2020 10:30:16 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:44280 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726526AbgD2OaQ (ORCPT ); Wed, 29 Apr 2020 10:30:16 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU8BB053731; Wed, 29 Apr 2020 09:30:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170608; bh=ey//PmdKfeyz5b819jnip6em7a8suXsJVF1VwUhpTKM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ue8ZjUE74/gAShwFGtVblhBDMOjT9/ljMDbrjHiTVo5Saf5hSydzMZE7MRMOj5Dbc ZKKb8sCOoJmSF11gOXWa3KaQ0bnCS3qGOLx9evdJ82ZPmthu0KmljGo6FixgKX6jJB BwWZWVQOqSopR4Mwpchh65ULpnm6mUSw99uvghP0= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03TEU9MK054681 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 Apr 2020 09:30:09 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:08 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:08 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54l010784; Wed, 29 Apr 2020 09:30:07 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 1/8] ARM: dts: omap4: fix node names for the l4_cm clkctrl nodes Date: Wed, 29 Apr 2020 17:29:55 +0300 Message-ID: <20200429143002.5050-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The node name for these should be clk instead of clock. Otherwise the clock driver won't be able to map the parent/child relationships properly, and large number of clocks end up in orphaned state. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 532868591107..b82b1ca0e557 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -1279,13 +1279,13 @@ #size-cells = <1>; ranges = <0 0x1400 0x200>; - l4_per_clkctrl: clock@20 { + l4_per_clkctrl: clk@20 { compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; reg = <0x20 0x144>; #clock-cells = <2>; }; - l4_secure_clkctrl: clock@1a0 { + l4_secure_clkctrl: clk@1a0 { compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; From patchwork Wed Apr 29 14:29:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22DDE1893 for ; Wed, 29 Apr 2020 14:30:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 018C121D93 for ; Wed, 29 Apr 2020 14:30:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hFFJ0mkf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726773AbgD2Oa3 (ORCPT ); Wed, 29 Apr 2020 10:30:29 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:53956 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726741AbgD2Oa3 (ORCPT ); Wed, 29 Apr 2020 10:30:29 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUPJW098764; Wed, 29 Apr 2020 09:30:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170625; bh=Rr3yRU7e+WZwUMxKj3OhbM3FhcVrnhefKHLL5Wt8jQQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hFFJ0mkfIwiXeKCKyJHSOfghox4x95BF+ivhTL2/d47rnKZBjxJMvvCxcKFscvO+3 mzqUDGfVDIZRIa/g+kyPlNaCPTd2xxtscaoPSXP8K0s2nAPE9jceM1d7nV+zTHz1hG 5HwmrjOyHDVcOXk1xuz3JL7cLgj5yAvQGJ+OhuSc= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03TEUPeB062979 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 Apr 2020 09:30:25 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:10 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:10 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54m010784; Wed, 29 Apr 2020 09:30:09 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 2/8] ARM: dts: omap5: fix node names for the l4_cm clkctrl nodes Date: Wed, 29 Apr 2020 17:29:56 +0300 Message-ID: <20200429143002.5050-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The node name for these should be clk instead of clock. Otherwise the clock driver won't be able to map the parent/child relationships properly, and large number of clocks end up in orphaned state. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 42f2c447727d..746048813a12 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -1125,13 +1125,13 @@ #size-cells = <1>; ranges = <0 0x1000 0x200>; - l4per_clkctrl: clock@20 { + l4per_clkctrl: clk@20 { compatible = "ti,clkctrl-l4per", "ti,clkctrl"; reg = <0x20 0x15c>; #clock-cells = <2>; }; - l4sec_clkctrl: clock@1a0 { + l4sec_clkctrl: clk@1a0 { compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; From patchwork Wed Apr 29 14:29:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA38315AB for ; Wed, 29 Apr 2020 14:30:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A95022074A for ; Wed, 29 Apr 2020 14:30:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RtGgy1LX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726739AbgD2OaZ (ORCPT ); Wed, 29 Apr 2020 10:30:25 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:45994 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726503AbgD2OaZ (ORCPT ); Wed, 29 Apr 2020 10:30:25 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUBet030618; Wed, 29 Apr 2020 09:30:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170611; bh=fWC+Rp0M0z5eox70tIMoGNLsRSAUN8+UUzp2rgayua0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RtGgy1LX2n1oiYMNve1Jiziud30huYw4QQP+49rGVxLVsQzSpup35VZiMZS9UTDLC ZB+pKCUgZUXTpij0x1vuUS9yHhb+yAuzMm86P6zXOsJ1BMBXOWvJgIvp7tvHrB5pO3 OA9EvXRuMmAWNmWcYmGFiy5E4zIg2D+QRP/ED3Mk= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03TEUBBe062590 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 Apr 2020 09:30:11 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:11 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:11 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54n010784; Wed, 29 Apr 2020 09:30:10 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 3/8] ARM: dts: omap5: add aes1 entry Date: Wed, 29 Apr 2020 17:29:57 +0300 Message-ID: <20200429143002.5050-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org OMAP5 has AES hardware cryptographic accelerator, add AES1 instance for it. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2ac7f021c284..30391dbc7f8f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -247,6 +247,35 @@ hw-caps-temp-alert; }; + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc From patchwork Wed Apr 29 14:29:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC5C915AB for ; Wed, 29 Apr 2020 14:30:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BC04221EA for ; Wed, 29 Apr 2020 14:30:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="q+N8sSxB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726562AbgD2OaR (ORCPT ); Wed, 29 Apr 2020 10:30:17 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:53904 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726526AbgD2OaQ (ORCPT ); Wed, 29 Apr 2020 10:30:16 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUDOv098691; Wed, 29 Apr 2020 09:30:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170613; bh=uBQouG9rgdP00V2nkV/meGcDAffMSdZKGT/7rmPLZMI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=q+N8sSxBCBs3kx3OXKz0tyyaUEtGjCLFt6Gn0LWTnNd5CsQ+NqAICRgcS2ELGuERk /OPB7RoE5/Dc5OTZHQKBPRGbBjsYw6yG7wOE4jEypECQn/FznQxy7+9o3kJtjeOKXB bNEcpmWagN5v3V4qp+m3ILt8pOnDZnAO99SVjw2I= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUD4p122041; Wed, 29 Apr 2020 09:30:13 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:12 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:12 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54o010784; Wed, 29 Apr 2020 09:30:11 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 4/8] ARM: dts: omap5: add aes2 entry Date: Wed, 29 Apr 2020 17:29:58 +0300 Message-ID: <20200429143002.5050-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org OMAP5 has AES hardware cryptographic accelerator, add AES2 instance for it. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 30391dbc7f8f..007911685cd9 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -276,6 +276,35 @@ }; }; + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc From patchwork Wed Apr 29 14:29:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50F8815AB for ; Wed, 29 Apr 2020 14:30:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F6882074A for ; Wed, 29 Apr 2020 14:30:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="sgElPn0f" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726423AbgD2OaV (ORCPT ); Wed, 29 Apr 2020 10:30:21 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:44286 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726503AbgD2OaV (ORCPT ); Wed, 29 Apr 2020 10:30:21 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUEL7053747; Wed, 29 Apr 2020 09:30:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170614; bh=wVT5Fy4WxIeGBWpm63lGslI6NL0UocyEOMuJsuDJe2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sgElPn0f01EXT9OXVq2RB+s2cgfwEWfROAKK6i60I5jl+LwAK5gdw+dUDAJ//LFAx 9gHaVSyiyYH2Rpfk2AajDAo6hxXF3cFwwLucA3LJB2TmCT++QsPGDlFTWAnabW3VYR oups19K0HVcsqjt+vu2uChwAy7IAj8NThoNkwxPk= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03TEUEca125774 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 Apr 2020 09:30:14 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:13 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:13 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54p010784; Wed, 29 Apr 2020 09:30:13 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 5/8] ARM: dts: omap5: add SHA crypto accelerator node Date: Wed, 29 Apr 2020 17:29:59 +0300 Message-ID: <20200429143002.5050-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add the single available SHA crypto accelerator device for OMAP5 SoC. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 007911685cd9..5e74f441c7e5 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -305,6 +305,34 @@ }; }; + sham_target: target-module@4b100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x4b100100 0x4>, + <0x4b100110 0x4>, + <0x4b100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc From patchwork Wed Apr 29 14:30:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517625 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 414C01893 for ; Wed, 29 Apr 2020 14:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A630221EB for ; Wed, 29 Apr 2020 14:30:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="XhxV/9it" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726654AbgD2OaZ (ORCPT ); Wed, 29 Apr 2020 10:30:25 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38826 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726691AbgD2OaZ (ORCPT ); Wed, 29 Apr 2020 10:30:25 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUFwb103729; Wed, 29 Apr 2020 09:30:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170615; bh=dp/ptzdtBpE57xdN7wrAd5gHoAOPnNuOJOS+skT7pWs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XhxV/9itdLtQCw3a0qk+yc1ZrIB+J1eXnT95yAPfg4Lz2VfJzc89N3V0f6axCsrKg 04UukYjztpJzfNixbuTUJrV26P8L1JHhcuh8Nhw6j2xqQm6Fme9uGMMUW4BheCKwx7 7N2MR6yL+TDhsrqQQWb0rgFZlk34JX94aR9xkHpM= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUF96122220; Wed, 29 Apr 2020 09:30:15 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:15 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:15 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54q010784; Wed, 29 Apr 2020 09:30:14 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 6/8] ARM: dts: omap5: add DES crypto accelerator node Date: Wed, 29 Apr 2020 17:30:00 +0300 Message-ID: <20200429143002.5050-7-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org OMAP5 contains a single DES crypto accelerator instance. Add node for this in DT to enable it. We keep the node disabled for now, as it appears OMAP5 platform is running out of available DMA channels, and DES is the least interesting crypto accelerator available on the device. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5-l4.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index f68740abb8aa..55999655a3bc 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -1003,6 +1003,7 @@ <0x00090000 0x00090000 0x002000>, /* ap 55 */ <0x00092000 0x00092000 0x001000>, /* ap 56 */ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a5000 0x000a5000 0x001000>, <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ @@ -1908,6 +1909,36 @@ <0x00001000 0x000a5000 0x00001000>; }; + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + status = "disabled"; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + }; + target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ compatible = "ti,sysc"; status = "disabled"; From patchwork Wed Apr 29 14:30:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5B3AC1893 for ; Wed, 29 Apr 2020 14:30:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A4792074A for ; Wed, 29 Apr 2020 14:30:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QmTfaj5a" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726691AbgD2Oa0 (ORCPT ); Wed, 29 Apr 2020 10:30:26 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:53948 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726741AbgD2Oa0 (ORCPT ); Wed, 29 Apr 2020 10:30:26 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUGjf098716; Wed, 29 Apr 2020 09:30:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170616; bh=i4nxys67IrBGJmeZqHzLnjDvYm4CubsYfNKisa2LT9g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QmTfaj5aVGqy8JbeAXA0XcCX6iqqBL1PRqfnuwJKARW4PFyoELBC0iQLS8zOIzz6+ Tk5auPe6q3/9ZFeZUiwRLuoiLRNEO5+vlR1D5xq8pzySzCjh3SPnDPJOw5TC+Qx7D5 5omZZXY4JxNlF1oBX20BqG0V9VG3yq4ta5fH6T/A= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUGww122297; Wed, 29 Apr 2020 09:30:16 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:16 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54r010784; Wed, 29 Apr 2020 09:30:15 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 7/8] ARM: OMAP4: Make L4SEC clock domain SWSUP only Date: Wed, 29 Apr 2020 17:30:01 +0300 Message-ID: <20200429143002.5050-8-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only') made DRA7 SoC L4SEC clock domain SWSUP only because of power state transition issues detected with HWSUP mode. Based on experimentation similar issue exists on OMAP4, so do the same change for OMAP4 also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 6005c4ed3bc6..8285be7c1eab 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -214,7 +214,7 @@ static struct clockdomain l4_secure_44xx_clkdm = { .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT, .wkdep_srcs = l4_secure_wkup_sleep_deps, .sleepdep_srcs = l4_secure_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l4_per_44xx_clkdm = { From patchwork Wed Apr 29 14:30:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11517627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7DE914B4 for ; Wed, 29 Apr 2020 14:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C773821D82 for ; Wed, 29 Apr 2020 14:30:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vTh3nJn3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726661AbgD2Oa0 (ORCPT ); Wed, 29 Apr 2020 10:30:26 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:53946 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726691AbgD2Oa0 (ORCPT ); Wed, 29 Apr 2020 10:30:26 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03TEUKOx098722; Wed, 29 Apr 2020 09:30:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588170620; bh=nVCV7GPPDR3vDlWCebMxkjIcsvNpW4Hi/TEQD5iWzEE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vTh3nJn3+idbSELh56lIzPb4ZkJ9OQzOV3q89DeCiRTS/SCnmtO9tvj5LfGQpDRoU Xntk5cHnAUJ+oP3XlbT1N/eJP/bAxYIU6quZ8wrbN7R2OpgXG04s+ZAFnBTAkS6QGT gVFoI9cfBpM56F8FIFOGBR9kFLhEs7+QmkT29Wn4= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03TEUHqX055015 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 Apr 2020 09:30:17 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Apr 2020 09:30:17 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Apr 2020 09:30:17 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03TEU54s010784; Wed, 29 Apr 2020 09:30:16 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 8/8] ARM: OMAP5: Make L4SEC clock domain SWSUP only Date: Wed, 29 Apr 2020 17:30:02 +0300 Message-ID: <20200429143002.5050-9-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429143002.5050-1-t-kristo@ti.com> References: <20200429143002.5050-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only') made DRA7 SoC L4SEC clock domain SWSUP only because of power state transition issues detected with HWSUP mode. Based on experimentation similar issue exists on OMAP5, so do the same change for OMAP5 also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clockdomains54xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c index 3ab41fc89dd3..5611e08018a2 100644 --- a/arch/arm/mach-omap2/clockdomains54xx_data.c +++ b/arch/arm/mach-omap2/clockdomains54xx_data.c @@ -170,7 +170,7 @@ static struct clockdomain l4sec_54xx_clkdm = { .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT, .wkdep_srcs = l4sec_wkup_sleep_deps, .sleepdep_srcs = l4sec_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain iva_54xx_clkdm = {