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Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- drivers/clocksource/exynos_mct.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 7a244b681876..43b335ff4a96 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -581,11 +581,7 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) * timer irqs are specified after the four global timer * irqs are specified. */ -#ifdef CONFIG_OF nr_irqs = of_irq_count(np); -#else - nr_irqs = 0; -#endif for (i = MCT_L0_IRQ; i < nr_irqs; i++) mct_irqs[i] = irq_of_parse_and_map(np, i); From patchwork Mon Oct 8 12:50:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 10630655 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5273216B1 for ; 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This patch adds a mode of cooperation with arch_timer driver, so kernel can use CP15 based timer interface via arch_timer driver, which is mandatory on ARM64. In such mode driver only configures MCT registers and starts the timer but don't register any clocksource or events in the system. Those are left to be handled by arch_timer driver. Signed-off-by: Marek Szyprowski --- drivers/clocksource/exynos_mct.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 43b335ff4a96..05b201ed8ef5 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -57,6 +57,7 @@ #define TICK_BASE_CNT 1 enum { + MCT_INT_NONE = 0, MCT_INT_SPI, MCT_INT_PPI }; @@ -238,6 +239,9 @@ static int __init exynos4_clocksource_init(void) { exynos4_mct_frc_start(); + if (!mct_int_type) + return 0; + #if defined(CONFIG_ARM) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; exynos4_delay_timer.freq = clk_rate; @@ -343,6 +347,9 @@ static struct irqaction mct_comp_event_irq = { static int exynos4_clockevent_init(void) { + if (!mct_int_type) + return 0; + mct_comp_device.cpumask = cpumask_of(0); clockevents_config_and_register(&mct_comp_device, clk_rate, 0xf, 0xffffffff); @@ -476,12 +483,12 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) irq_force_affinity(evt->irq, cpumask_of(cpu)); enable_irq(evt->irq); - } else { + } else if (mct_int_type == MCT_INT_PPI) { enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); } - clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), - 0xf, 0x7fffffff); - + if (mct_int_type) + clockevents_config_and_register(evt, + clk_rate / (TICK_BASE_CNT + 1), 0xf, 0x7fffffff); return 0; } @@ -496,7 +503,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) if (evt->irq != -1) disable_irq_nosync(evt->irq); exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); - } else { + } else if (mct_int_type == MCT_INT_PPI) { disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); } return 0; @@ -529,7 +536,7 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem * &percpu_mct_tick); WARN(err, "MCT: can't request IRQ %d (%d)\n", mct_irqs[MCT_L0_IRQ], err); - } else { + } else if (mct_int_type == MCT_INT_SPI) { for_each_possible_cpu(cpu) { int mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; struct mct_clock_event_device *pcpu_mevt = @@ -573,6 +580,15 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) mct_int_type = int_type; + if (IS_ENABLED(CONFIG_ARM64) && IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) { + struct device_node *np = of_find_compatible_node(NULL, NULL, + "arm,armv8-timer"); + if (np) { + mct_int_type = MCT_INT_NONE; + of_node_put(np); + } + } + /* This driver uses only one global timer interrupt */ mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); From patchwork Mon Oct 8 12:50:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 10630659 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5707D17E3 for ; Mon, 8 Oct 2018 12:51:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4987028F52 for ; Mon, 8 Oct 2018 12:51:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 473FC28F82; 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Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- include/linux/cpuhotplug.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index caf40ad0bbc6..5d9e4a6ea299 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -115,10 +115,10 @@ enum cpuhp_state { CPUHP_AP_PERF_ARM_ACPI_STARTING, CPUHP_AP_PERF_ARM_STARTING, CPUHP_AP_ARM_L2X0_STARTING, + CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_ARCH_TIMER_STARTING, CPUHP_AP_ARM_GLOBAL_TIMER_STARTING, CPUHP_AP_JCORE_TIMER_STARTING, - CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, From patchwork Mon Oct 8 12:50:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 10630653 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE1A416B1 for ; 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Mon, 8 Oct 2018 13:50:49 +0100 (BST) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20181008125048eucas1p229a94c202596ddd0a65009c15d9e3001~box5elyRs1879418794eucas1p2r; Mon, 8 Oct 2018 12:50:48 +0000 (GMT) X-AuditID: cbfec7f5-367ff700000012c6-85-5bbb52a8a3c7 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id C4.39.04128.8A25BBB5; Mon, 8 Oct 2018 13:50:48 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PGA006EA6BYW230@eusync1.samsung.com>; Mon, 08 Oct 2018 13:50:48 +0100 (BST) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski , Will Deacon , Catalin Marinas , Marc Zyngier , Thomas Gleixner , Daniel Lezcano , Krzysztof Kozlowski , Chanwoo Choi , Bartlomiej Zolnierkiewicz , Inki Dae Subject: [PATCH 4/7] clocksource: arch_timer: Add support for not-fw-configured timer on ARM64 Date: Mon, 08 Oct 2018 14:50:06 +0200 Message-id: <20181008125009.3721-5-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20181008125009.3721-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAIsWRmVeSWpSXmKPExsWy7djP87org3ZHG7yYwGSxccZ6Vov3y3oY La5/ec5qMe+zrMWk+xNYLM6f38BusenxNVaLy7vmsFnMOL+PyWLtkbvsFn/v/GOz2LxpKrPF y48nWBx4PdbMW8PosWlVJ5vHnWt72DzenTvH7rF5Sb1H35ZVjB6fN8kFsEdx2aSk5mSWpRbp 2yVwZUxZdoSx4LJ4xcnDAg2M74S7GDk5JARMJB5tnMbSxcjFISSwglFi8uz9rBDOZ0aJ859+ MsJU7f18CapqGaPEhatfoKoamCR+NW1jAqliEzCU6HrbxQZiiwhkS3Q+fgDWzSywiFniwDGw fcICCRKvN81jBrFZBFQlfu9pBrN5BWwkti7tg9omL7F6wwGwOKeArcSTrlVgmyUE9rBJtK7a ywpR5CKx/9A/ZghbWOLV8S3sELaMxOXJ3VANzYwS7TNmsUM4PYwSW+fsYIOospY4fPwiK8R5 fBKTtk0HmsQBFOeV6GgTgijxkHi2bhk7xJsTGCU2X2phncAouYCRYRWjeGppcW56arFxXmq5 XnFibnFpXrpecn7uJkZgPJ/+d/zrDsZ9f5IOMQpwMCrx8Ab47YoWYk0sK67MPcQowcGsJMIr uh0oxJuSWFmVWpQfX1Sak1p8iFGag0VJnHfZvI3RQgLpiSWp2ampBalFMFkmDk6pBsYgATn/ qtgFvbr2jv0pHnZTV7SU3o6yfaVU9sakRP6Jp8cyjdXfmpSiXs+dIcL08K8p95FfWpkmC1SX e96JmvN+/VKt9R5egX1G63+bFD7IVXyVdG4v6zvbw+f/+E7M3aa0qjXwz/dnKvsC1C43XW9V k1A5vHllpLlVjPW6gw7lt17P8F9htliJpTgj0VCLuag4EQA2zswz4wIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDLMWRmVeSWpSXmKPExsVy+t/xy7orgnZHG0zrkLHYOGM9q8X7ZT2M Fte/PGe1mPdZ1mLS/QksFufPb2C32PT4GqvF5V1z2CxmnN/HZLH2yF12i793/rFZbN40ldni 5ccTLA68HmvmrWH02LSqk83jzrU9bB7vzp1j99i8pN6jb8sqRo/Pm+QC2KO4bFJSczLLUov0 7RK4MqYsO8JYcFm84uRhgQbGd8JdjJwcEgImEns/X2LpYuTiEBJYwiix4+0cRginiUli6fKX 7CBVbAKGEl1vu9hAbBGBbIn5e7vB4swCS5glbt53ALGFBRIk7lyeygRiswioSvze08wMYvMK 2EhsXdrHCLFNXmL1hgNgcU4BW4knXatYQGwhoJre6RdZJzDyLGBkWMUoklpanJueW2ykV5yY W1yal66XnJ+7iREYhtuO/dyyg7HrXfAhRgEORiUe3hUBu6KFWBPLiitzDzFKcDArifCKbgcK 8aYkVlalFuXHF5XmpBYfYpTmYFES5z1vUBklJJCeWJKanZpakFoEk2Xi4JRqYOw4xb9Lcfrj gKS5K7582/f9142or1pbLJStRa4eFt9yxF0x4Pts6U9TEttKn3641Zcq19/+6o6Aqpr/gxVT dvR6Hz3Gt/3yHj7hxLehFgdleiY88zAr/3ttTnBkhZnKgZTzT/oOiMxZkn5ZeNayZ1wGX/fc Oliucahy8uy9J+oktt6SfXt/yeXnSizFGYmGWsxFxYkA/YrTkz8CAAA= X-CMS-MailID: 20181008125048eucas1p229a94c202596ddd0a65009c15d9e3001 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181008125048eucas1p229a94c202596ddd0a65009c15d9e3001 References: <20181008125009.3721-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use common infrastructure for ARM Architected Timers erratum to enable support for systems with broken CPU firmware (timer registers not properly configured). This mode has been already availabled on ARM (32bits) architecture. This enables to run Linux kernel on ARM64 boards using physical architected timers instead of the virtual ones. Examples of such system with broken firmware are Samsung Exynos5433 SoC based TM2(e) boards, which is already deployed for years and updating firmware is not possible. Signed-off-by: Marek Szyprowski --- drivers/clocksource/Kconfig | 11 +++++++++++ drivers/clocksource/arm_arch_timer.c | 15 ++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a11f4ba98b05..a30752579b03 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -364,6 +364,17 @@ config ARM64_ERRATUM_858921 The workaround will be dynamically enabled when an affected core is detected. +config ARCH_TIMER_REGISTERS_NOT_FW_CONFIGURED + bool "Workaround for arch timer registers not configured by firmware" + default y + select ARM_ARCH_TIMER_OOL_WORKAROUND + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a workaround for boards, on which arch timer + registers are not properly configured by the board firmware. + The workaround will be dynamically enabled when an affected + board is detected. + config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select TIMER_OF if OF diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9a7d4dc00b6e..b6f109654daf 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -423,6 +423,14 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .read_cntvct_el0 = arm64_1188873_read_cntvct_el0, }, #endif +#ifdef CONFIG_ARCH_TIMER_REGISTERS_NOT_FW_CONFIGURED + { + .match_type = ate_match_dt, + .id = "arm,cpu-registers-not-fw-configured", + .desc = "broken CPU firmware (timer registers not configured)", + .read_cntvct_el0 = arch_counter_get_cntpct, + }, +#endif }; typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, @@ -1234,9 +1242,10 @@ static int __init arch_timer_of_init(struct device_node *np) * If we cannot rely on firmware initializing the timer registers then * we should use the physical timers instead. */ - if (IS_ENABLED(CONFIG_ARM) && - of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) - arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; + if (of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) + arch_timer_uses_ppi = IS_ENABLED(CONFIG_ARM64) ? + ARCH_TIMER_PHYS_NONSECURE_PPI : + ARCH_TIMER_PHYS_SECURE_PPI; else arch_timer_uses_ppi = arch_timer_select_ppi(); From patchwork Mon Oct 8 12:50:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 10630647 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D9B616B1 for ; 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Signed-off-by: Marek Szyprowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 23 +++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 77297d66642c..eee3d1d1b52f 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -290,6 +290,18 @@ interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x5c000>; @@ -1811,17 +1823,6 @@ }; }; - timer: timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; }; #include "exynos5433-bus.dtsi" From patchwork Mon Oct 8 12:50:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 10630651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B32EC17E3 for ; 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This enables respective workarounds in the timer driver. Signed-off-by: Marek Szyprowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 2606c2ab6456..ded0fb6c5936 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -1265,6 +1265,7 @@ }; &timer { + arm,cpu-registers-not-fw-configured; clock-frequency = <24000000>; }; From patchwork Mon Oct 8 12:50:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 10630649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF8D717E3 for ; Mon, 8 Oct 2018 12:50:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E079A28DD4 for ; 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Signed-off-by: Marek Szyprowski --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 51bc479334a4..7cc687580fad 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -62,6 +62,7 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG + select CLKSRC_EXYNOS_MCT select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select HAVE_S3C2410_WATCHDOG if WATCHDOG