From patchwork Thu Apr 30 08:36:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11519465 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D738715AB for ; Thu, 30 Apr 2020 08:36:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B79112192A for ; Thu, 30 Apr 2020 08:36:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="g+X8qqiV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726611AbgD3Igt (ORCPT ); Thu, 30 Apr 2020 04:36:49 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35372 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726420AbgD3Igt (ORCPT ); Thu, 30 Apr 2020 04:36:49 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03U8akMN101696; Thu, 30 Apr 2020 03:36:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588235806; bh=uRDS3CZggzBOWMlm4jhNck7COB5RbecQq9XdSfwObDE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g+X8qqiVEFM9TYemJMPbG2QipdGCnFfgmsuLExb5BwibmeFN5xRaPpMbNpBSEZIDy NwGxch6sNH/RdA0+/lqdLXmQSRsR+xTqhl9GQgHs3zu8jJFsTkVhBk1PjMayqRxI4B grbeIM4I2RQwGBp3yzvh7m4MugcoA8KcEp6AD+Yo= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03U8aknq063223 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 30 Apr 2020 03:36:46 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 30 Apr 2020 03:36:45 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 30 Apr 2020 03:36:46 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03U8agEm073623; Thu, 30 Apr 2020 03:36:44 -0500 From: Tero Kristo To: , , CC: , Subject: [PATCH 1/3] clk: ti: dra7xx: fix gpu clkctrl parent Date: Thu, 30 Apr 2020 11:36:38 +0300 Message-ID: <20200430083640.8621-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430083640.8621-1-t-kristo@ti.com> References: <20200430083640.8621-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org gpu_cm:* parent clock name is wrong, replace this with correct gpu-clkctrl:* clock. Otherwise the clock ends up in the orphaned list. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 14b645093107..366cb75378cb 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -328,7 +328,7 @@ static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = }; static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = { - { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24", }, + { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", }, { 0 }, }; From patchwork Thu Apr 30 08:36:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11519469 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD57915AB for ; Thu, 30 Apr 2020 08:36:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9AB0D214D8 for ; Thu, 30 Apr 2020 08:36:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nBpBH7DS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726621AbgD3Igv (ORCPT ); Thu, 30 Apr 2020 04:36:51 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:48798 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726420AbgD3Igu (ORCPT ); Thu, 30 Apr 2020 04:36:50 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03U8alhm094443; Thu, 30 Apr 2020 03:36:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588235807; bh=idc5gdhNc8qmOLkXqV/R5/KEalHYKuJ427pVS2ZvQzY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nBpBH7DSpmIcODZHRjqdjSSPZ9KCZUy6QrDM1EAuWqqS47OCn/dOazYXymYUfgeSn lV5QVUGmj4mBMs787+erbDdSBNu0yMphDTr6MOL2+2VRANcT2eF53h8PwPfLxd225+ 5cIrbanUgcwkqOzxyQ6H8WZSiBbIEh3eBGToPF3E= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03U8alXW063243 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 30 Apr 2020 03:36:47 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 30 Apr 2020 03:36:47 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 30 Apr 2020 03:36:47 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03U8agEn073623; Thu, 30 Apr 2020 03:36:46 -0500 From: Tero Kristo To: , , CC: , Subject: [PATCH 2/3] clk: ti: dra7xx: mark MCAN clock as DRA76x only Date: Thu, 30 Apr 2020 11:36:39 +0300 Message-ID: <20200430083640.8621-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430083640.8621-1-t-kristo@ti.com> References: <20200430083640.8621-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org This clock entry does not exist on any other devices except DRA76, so mark it as specific to that SoC only. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 366cb75378cb..146d1d67c732 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -815,7 +815,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" }, { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" }, - { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" }, + { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" }, { 0 }, }; From patchwork Thu Apr 30 08:36:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11519473 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 940F615AB for ; Thu, 30 Apr 2020 08:36:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72A312173E for ; Thu, 30 Apr 2020 08:36:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="aXTJZnUc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726683AbgD3Igx (ORCPT ); Thu, 30 Apr 2020 04:36:53 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:48808 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726420AbgD3Igw (ORCPT ); Thu, 30 Apr 2020 04:36:52 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03U8anKh094449; Thu, 30 Apr 2020 03:36:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588235809; bh=VYueZm5CvboGryMIxPqzyx8mLmX3qjIlZueWkp9+pss=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aXTJZnUcOWKiJHI+oQ3XlMBQOlJQe1QqtAa0zQgrppcUHYPzPQVZSBWeK7qP2GpHR svnD4zerDYjBbnoGsYkshxfV6bkaHzLaCwnqMXuob9k1G9pbL9m6COGlfq3Lr1ZM+j 039jrH6F1hlQeFGKSimHKRTuLNb2lVAi3FFMApwU= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03U8anYr076754; Thu, 30 Apr 2020 03:36:49 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 30 Apr 2020 03:36:49 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 30 Apr 2020 03:36:49 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03U8agEo073623; Thu, 30 Apr 2020 03:36:47 -0500 From: Tero Kristo To: , , CC: , Subject: [PATCH 3/3] clk: ti: dra7xx: fix RNG clock parent Date: Thu, 30 Apr 2020 11:36:40 +0300 Message-ID: <20200430083640.8621-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430083640.8621-1-t-kristo@ti.com> References: <20200430083640.8621-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org RNG is sourced from L4 clock. Add info for this for proper parenting of the clock. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 146d1d67c732..bf8fced40e42 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -644,7 +644,7 @@ static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" }, { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, { 0 }, };