From patchwork Thu Apr 30 11:56:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11519979 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 56216912 for ; Thu, 30 Apr 2020 11:57:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DFA32078D for ; Thu, 30 Apr 2020 11:57:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="ptSca4hV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726884AbgD3L5l (ORCPT ); Thu, 30 Apr 2020 07:57:41 -0400 Received: from plaes.org ([188.166.43.21]:37072 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726481AbgD3L5l (ORCPT ); Thu, 30 Apr 2020 07:57:41 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 13D554036D; Thu, 30 Apr 2020 11:57:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588247829; bh=bh7o9ZhtcwUOEzy3WygVte7TJMzYuXaXlcYI721k4f8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ptSca4hVYlVlD+EeQS36HhT/dPaEy5pyiigz/Kfbl3GOJ5Bo8KfOzvXrIQg8VPoDM Fy66ScCGvpCkDjyVF7rM4ZeaugaTacGRw/4GkvtaW1BVIBvsEjU65L3VKl/wPP/VR5 oZFUBNSMdNsFEaFK9deqPJztaNHnS4X5yrYD6J2OprwfG/3GF+oScP+TI0uyLARkDH OUqgKKPngJlu71n6BqlE/UvnR+NKfdlb/nTR2IFBFOTAoIU02LI49ZndUolk5ENMII GAu/vY4jxfDLRiUBPUQC7Is3FUR141vs9/XhICwZ0uulGWwApMclmREtUICFh7PAAF w67FZ6Gbh76jw== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v3 1/6] clk: sunxi-ng: a20: Register regmap for sun7i CCU Date: Thu, 30 Apr 2020 14:56:57 +0300 Message-Id: <20200430115702.5768-2-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200430115702.5768-1-plaes@plaes.org> References: <20200430115702.5768-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On sun7i, the gmac clock is handled by the dwmac-sunxi driver, but its configuration register is located in the CCU register range, requiring proper regmap setup. In order to do that, we use CLK_OF_DECLARE_DRIVER to initialize sun7i ccu, which clears the OF_POPULATED flag, allowing the platform device to probe the same resource with proper device node. Signed-off-by: Priit Laes --- drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 62 +++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c index f32366d9336e..fa147b8ce705 100644 --- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include "ccu_common.h" #include "ccu_reset.h" @@ -1478,5 +1480,61 @@ static void __init sun7i_a20_ccu_setup(struct device_node *node) { sun4i_ccu_init(node, &sun7i_a20_ccu_desc); } -CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu", - sun7i_a20_ccu_setup); +CLK_OF_DECLARE_DRIVER(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu", + sun7i_a20_ccu_setup); + +/* + * Regmap for the GMAC driver (dwmac-sunxi) to allow access to + * GMAC configuration register. + */ +#define SUN7I_A20_GMAC_CFG_REG 0x164 +static bool sun7i_a20_ccu_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUN7I_A20_GMAC_CFG_REG) + return true; + return false; +} + +static struct regmap_config sun7i_a20_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x1f4, /* clk_out_b */ + + .readable_reg = sun7i_a20_ccu_regmap_accessible_reg, + .writeable_reg = sun7i_a20_ccu_regmap_accessible_reg, +}; + +static int sun7i_a20_ccu_probe_regmap(struct platform_device *pdev) +{ + void __iomem *reg; + struct resource *res; + struct regmap *regmap; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun7i_a20_ccu_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return 0; +} + +static const struct of_device_id sun7i_a20_ccu_ids[] = { + { .compatible = "allwinner,sun7i-a20-ccu"}, + { } +}; + +static struct platform_driver sun7i_a20_ccu_driver = { + .probe = sun7i_a20_ccu_probe_regmap, + .driver = { + .name = "sun7i-a20-ccu", + .of_match_table = sun7i_a20_ccu_ids, + }, +}; +builtin_platform_driver(sun7i_a20_ccu_driver); From patchwork Thu Apr 30 11:56:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11519971 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11DD6913 for ; Thu, 30 Apr 2020 11:57:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF35920870 for ; Thu, 30 Apr 2020 11:57:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="BpLAHAYx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726809AbgD3L5N (ORCPT ); Thu, 30 Apr 2020 07:57:13 -0400 Received: from plaes.org ([188.166.43.21]:37020 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726481AbgD3L5N (ORCPT ); Thu, 30 Apr 2020 07:57:13 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id A676D4066A; Thu, 30 Apr 2020 11:57:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588247830; bh=KtrNDTyIYly28OFcUiv1CrKTihke56ToqkXK8VtrLnE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BpLAHAYxOT56SoKWq8eNcb1vPxjkJV2WJVmtWEl+zOHPQi6PR78R4bLys2kodvc5r h3c0u6sizZblpY0lCm0OZHyk7+Qstv6FLC8CrD1oYXEdqeLVH19v2YR4xQGevjxry4 eYKGBnFgbIrxMrTweE/WW3snMGPm2WgkNwCvCo98cuRsUqrW6HpIuJd0BhR2KNz0nD 8mHbvuaS0j1mw56hXN8P6aSLn2GN2is99R4XxSEqLEMl9EM7Pwqr1rE97RGgWnQYyY WqeSx6Ak+uXtdj1Hk29Ti+TbFNf7tsMVawh2N7R4VGLWYJIjbJ4QebZjYjUmc0HjMd 48yIjieRaNlEw== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v3 2/6] clk: sunxi-ng: a31: Register regmap for sun6i CCU Date: Thu, 30 Apr 2020 14:56:58 +0300 Message-Id: <20200430115702.5768-3-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200430115702.5768-1-plaes@plaes.org> References: <20200430115702.5768-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On sun6i, the gmac clock is handled by the dwmac-sunxi driver, but its configuration register is located in the CCU register range, requiring proper regmap setup. In order to do that, we use CLK_OF_DECLARE_DRIVER to initialize sun7i ccu, which clears the OF_POPULATED flag, allowing the platform device to probe the same resource with device node. Signed-off-by: Priit Laes --- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 62 +++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index 9b40d53266a3..3f6f9824b2ca 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include "ccu_common.h" #include "ccu_reset.h" @@ -1262,5 +1264,61 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node) ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, &sun6i_a31_cpu_nb); } -CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu", - sun6i_a31_ccu_setup); +CLK_OF_DECLARE_DRIVER(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu", + sun6i_a31_ccu_setup); + +/* + * Regmap for the GMAC driver (dwmac-sunxi) to allow access to + * GMAC configuration register. + */ +#define SUN6I_A31_GMAC_CFG_REG 0xD0 +static bool sun6i_a31_ccu_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUN6I_A31_GMAC_CFG_REG) + return true; + return false; +} + +static struct regmap_config sun6i_a31_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x308, /* clk_out_b */ + + .readable_reg = sun6i_a31_ccu_regmap_accessible_reg, + .writeable_reg = sun6i_a31_ccu_regmap_accessible_reg, +}; + +static int sun6i_a31_ccu_probe_regmap(struct platform_device *pdev) +{ + void __iomem *reg; + struct resource *res; + struct regmap *regmap; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun6i_a31_ccu_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return 0; +} + +static const struct of_device_id sun6i_a31_ccu_ids[] = { + { .compatible = "allwinner,sun6i-a31-ccu"}, + { } +}; + +static struct platform_driver sun6i_a31_ccu_driver = { + .probe = sun6i_a31_ccu_probe_regmap, + .driver = { + .name = "sun6i-a31-ccu", + .of_match_table = sun6i_a31_ccu_ids, + }, +}; +builtin_platform_driver(sun6i_a31_ccu_driver); From patchwork Thu Apr 30 11:56:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11519987 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C2FF61805 for ; Thu, 30 Apr 2020 11:57:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A64D120757 for ; Thu, 30 Apr 2020 11:57:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="Pzng54RT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726809AbgD3L5p (ORCPT ); Thu, 30 Apr 2020 07:57:45 -0400 Received: from plaes.org ([188.166.43.21]:37078 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726481AbgD3L5p (ORCPT ); Thu, 30 Apr 2020 07:57:45 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 318D840774; Thu, 30 Apr 2020 11:57:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588247832; bh=vozgkxdGukZkw97VZxaA46SLq3vMd9Wmn6ITkjlRwzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pzng54RTQjI9fC292U4VQj3hoLs4JvLd08JqmAYuJFI68IoP3RsYXyQQyKs5XoE1s KXyFZS80zUmUhih+dFToXFlTYSTr/ssTL3EYBzRDM1DyNXm544MdIg2ge3xf5/Srqc M99cDk1y0oKds9ZeOq+JWo4aYzzTZcIQkolNStBKeisSMPjveyNheJr4sEORZ9/i0l Zs+8jGZ89oO+U1i+LmLCSho8B3mHf0GYTDzTax/f6eI3DeyDP8roAkW8zibaR7FLbf vZgoh4doBfYAXJ0QVP+KtToeM4XK3AM0tqgPII/YRrsWds5S2Ev0A8xZpcudckDVv3 wmgy5+DsF7I5Q== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v3 3/6] net: stmmac: dwmac-sunxi: Implement syscon-based clock handling Date: Thu, 30 Apr 2020 14:56:59 +0300 Message-Id: <20200430115702.5768-4-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200430115702.5768-1-plaes@plaes.org> References: <20200430115702.5768-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert the sun7i-gmac driver to use a regmap-based driver, instead of relying on the custom clock implementation. This allows to get rid of the last custom clock in the sun7i device tree making the sun7i fully CCU-compatible. Compatibility with existing devicetrees is retained. Signed-off-by: Priit Laes --- .../net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 130 ++++++++++++++++-- 1 file changed, 122 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c index 0e1ca2cba3c7..206398f7a2af 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c @@ -12,8 +12,11 @@ #include #include #include +#include #include #include +#include +#include #include "stmmac_platform.h" @@ -22,11 +25,23 @@ struct sunxi_priv_data { int clk_enabled; struct clk *tx_clk; struct regulator *regulator; + struct regmap_field *regmap_field; +}; + +/* EMAC clock register @ 0x164 in the CCU address range */ +static const struct reg_field ccu_reg_field = { + .reg = 0x164, + .lsb = 0, + .msb = 31, }; #define SUN7I_GMAC_GMII_RGMII_RATE 125000000 #define SUN7I_GMAC_MII_RATE 25000000 +#define SUN7I_A20_CLK_MASK GENMASK(2, 0) +#define SUN7I_A20_RGMII_CLK (BIT(2) | BIT(1)) +#define SUN7I_A20_MII_CLK 0 + static int sun7i_gmac_init(struct platform_device *pdev, void *priv) { struct sunxi_priv_data *gmac = priv; @@ -38,7 +53,20 @@ static int sun7i_gmac_init(struct platform_device *pdev, void *priv) return ret; } - /* Set GMAC interface port mode + if (gmac->regmap_field) { + if (phy_interface_mode_is_rgmii(gmac->interface)) { + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_RGMII_CLK); + return clk_prepare_enable(gmac->tx_clk); + } + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_MII_CLK); + return clk_enable(gmac->tx_clk); + } + + /* Legacy devicetree clock (allwinner,sun7i-a20-gmac-clk) support: * * The GMAC TX clock lines are configured by setting the clock * rate, which then uses the auto-reparenting feature of the @@ -62,9 +90,16 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) { struct sunxi_priv_data *gmac = priv; - if (gmac->clk_enabled) { + if (gmac->regmap_field) { + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, 0); clk_disable(gmac->tx_clk); - gmac->clk_enabled = 0; + } else { + /* Handle legacy devicetree clock (sun7i-a20-gmac-clk) */ + if (gmac->clk_enabled) { + clk_disable(gmac->tx_clk); + gmac->clk_enabled = 0; + } } clk_unprepare(gmac->tx_clk); @@ -72,10 +107,55 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) regulator_disable(gmac->regulator); } +static struct regmap *sun7i_gmac_get_syscon_from_dev(struct device_node *node) +{ + struct device_node *syscon_node; + struct platform_device *syscon_pdev; + struct regmap *regmap = NULL; + + syscon_node = of_parse_phandle(node, "syscon", 0); + if (!syscon_node) + return ERR_PTR(-ENODEV); + + syscon_pdev = of_find_device_by_node(syscon_node); + if (!syscon_pdev) { + /* platform device might not be probed yet */ + regmap = ERR_PTR(-EPROBE_DEFER); + goto out_put_node; + } + + /* If no regmap is found then the other device driver is at fault */ + regmap = dev_get_regmap(&syscon_pdev->dev, NULL); + if (!regmap) + regmap = ERR_PTR(-EINVAL); + + platform_device_put(syscon_pdev); +out_put_node: + of_node_put(syscon_node); + return regmap; +} + static void sun7i_fix_speed(void *priv, unsigned int speed) { struct sunxi_priv_data *gmac = priv; + if (gmac->regmap_field) { + clk_disable(gmac->tx_clk); + clk_unprepare(gmac->tx_clk); + if (speed == 1000) + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_RGMII_CLK); + else + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_MII_CLK); + clk_prepare_enable(gmac->tx_clk); + return; + } + + /* Handle legacy devicetree clock (sun7i-a20-gmac-clk) */ + /* only GMII mode requires us to reconfigure the clock lines */ if (gmac->interface != PHY_INTERFACE_MODE_GMII) return; @@ -102,6 +182,8 @@ static int sun7i_gmac_probe(struct platform_device *pdev) struct stmmac_resources stmmac_res; struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; + struct device_node *syscon_node; + struct regmap *regmap = NULL; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -124,11 +206,43 @@ static int sun7i_gmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } - gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); - if (IS_ERR(gmac->tx_clk)) { - dev_err(dev, "could not get tx clock\n"); - ret = PTR_ERR(gmac->tx_clk); - goto err_remove_config_dt; + /* Attempt to fetch syscon node... */ + syscon_node = of_parse_phandle(dev->of_node, "syscon", 0); + if (syscon_node) { + gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "Could not get TX clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + + regmap = sun7i_gmac_get_syscon_from_dev(pdev->dev.of_node); + if (IS_ERR(regmap)) + regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); + goto err_remove_config_dt; + } + + gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, + ccu_reg_field); + + if (IS_ERR(gmac->regmap_field)) { + ret = PTR_ERR(gmac->regmap_field); + dev_err(dev, "Unable to map syscon register: %d\n", ret); + goto err_remove_config_dt; + } + /* ...or fall back to legacy clock setup */ + } else { + gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "could not get tx clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + dev_info(dev, "allwinner_gmac_tx support is deprecated!\n"); } /* Optional regulator for PHY */ From patchwork Thu Apr 30 11:57:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11519985 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80C71912 for ; Thu, 30 Apr 2020 11:57:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6029B20838 for ; Thu, 30 Apr 2020 11:57:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="QkPepq9j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726950AbgD3L5s (ORCPT ); Thu, 30 Apr 2020 07:57:48 -0400 Received: from plaes.org ([188.166.43.21]:37082 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726907AbgD3L5q (ORCPT ); Thu, 30 Apr 2020 07:57:46 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id D017B4092D; Thu, 30 Apr 2020 11:57:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588247834; bh=vMo2TanI9GatNd59nOo9RI6zU3bToC+1dQv+F9Smax0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QkPepq9jRIHzXYSDHzmANJ+RqWrN2Do7/VE3yhAEqeTTI/ddCGQF3C5E55wE/Wpk6 ETVZ7nf+ZlG6jVnqeNNpbWJwCHZpcjzVkNXa9YEK6Aeirv272bl10ne4TgEan1X9tU 6UZnTnma0bOmJP7Ls8Vb3PcNVMfP1uoPkHI9GROJnbK7St8rcR+sqPwSUShjQTxLeC eFpwtNQGmlpsoQtfbI+6x9rhEZ1k3+24xq9FxVr0rU18bdHgSlYQ32YaS13OhL1qmx 5e8Zuz6RWT9bMmIPwXynHtWIu4Ip167IeoVqKE2Dy34d4Ff+Gjv+pK5IupeH0i5raY XSkvGP8QXQ4jw== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v3 4/6] dt-bindings: net: sun7i-gmac: Add syscon support Date: Thu, 30 Apr 2020 14:57:00 +0300 Message-Id: <20200430115702.5768-5-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200430115702.5768-1-plaes@plaes.org> References: <20200430115702.5768-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Now that driver supports syscon-based regmap access, document also the devicetree binding. Signed-off-by: Priit Laes --- .../bindings/net/allwinner,sun7i-a20-gmac.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml index 703d0d886884..c41d7c598c19 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml @@ -29,17 +29,26 @@ properties: clocks: items: - description: GMAC main clock + + # Deprecated - description: TX clock clock-names: items: - const: stmmaceth + + # Deprecated - const: allwinner_gmac_tx phy-supply: description: PHY regulator + syscon: + $ref: /schemas/types.yaml#definitions/phandle + description: + Phandle to the device containing the GMAC clock register + required: - compatible - reg @@ -48,6 +57,7 @@ required: - clocks - clock-names - phy-mode + - syscon unevaluatedProperties: false @@ -55,11 +65,12 @@ examples: - | gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&syscon>; reg = <0x01c50000 0x10000>; interrupts = <0 85 1>; interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ahb_gates 49>; + clock-names = "stmmaceth"; phy-mode = "mii"; }; From patchwork Thu Apr 30 11:57:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11519975 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D096912 for ; Thu, 30 Apr 2020 11:57:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 05AEA2078D for ; Thu, 30 Apr 2020 11:57:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="GIzah/ig" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbgD3L5S (ORCPT ); Thu, 30 Apr 2020 07:57:18 -0400 Received: from plaes.org ([188.166.43.21]:37054 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726481AbgD3L5R (ORCPT ); Thu, 30 Apr 2020 07:57:17 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 607F840020; Thu, 30 Apr 2020 11:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588247835; bh=4Nyq2+q+6gFl8xdUXrX7ogdDuJtGtGSha4s+xAB0G6E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GIzah/igz/6ft4ru3lV5D5c3bsMXMumCwGjWVJaI52sdUTMGYdE8+nW3NvTcUXTBB 9gHwzsr6ftIAG7Q4HcwQ8UHdsKsnzCqqV0vc4SlkYprADklbnLZ/6afQfW2DFxxdg2 NXCaKOA87yuer1mL2E3sQSBXw88I2rWvjNaAYJMkn7/81ADG33H0F2tUPUkotOmWs0 d8kPVN/4VcD3181OtT2fj4JEW/oMV0iKkycnAoxdmQxgmr9PaSOXLgdR3pCNArXni+ LKBy/4Bij51sIQEDhKHo+jUBS1ERZYYLM4JXkubmax7eXXagYwcCDlDgOuXEWI4qJp 41rfFL+pHDHBw== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v3 5/6] ARM: dts: sun7i: Use syscon-based implementation for gmac Date: Thu, 30 Apr 2020 14:57:01 +0300 Message-Id: <20200430115702.5768-6-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200430115702.5768-1-plaes@plaes.org> References: <20200430115702.5768-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use syscon-based approach to access gmac clock configuration register, instead of relying on a custom clock driver. As a bonus, we can now drop the custom clock implementation and dummy clocks making sun7i fully CCU-compatible. Signed-off-by: Priit Laes --- arch/arm/boot/dts/sun7i-a20.dtsi | 36 +++----------------------------- 1 file changed, 3 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index ffe1d10a1a84..750962a94fad 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -219,37 +219,6 @@ osc32k: clk-32k { clock-frequency = <32768>; clock-output-names = "osc32k"; }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; }; @@ -1511,11 +1480,12 @@ mali: gpu@1c40000 { gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&ccu>; reg = <0x01c50000 0x10000>; interrupts = ; interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ccu CLK_AHB_GMAC>; + clock-names = "stmmaceth"; snps,pbl = <2>; snps,fixed-burst; snps,force_sf_dma_mode; From patchwork Thu Apr 30 11:57:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11519981 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D7C7017EF for ; Thu, 30 Apr 2020 11:57:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C001D20838 for ; Thu, 30 Apr 2020 11:57:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="D8wXvgqC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726907AbgD3L5v (ORCPT ); Thu, 30 Apr 2020 07:57:51 -0400 Received: from plaes.org ([188.166.43.21]:37090 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726481AbgD3L5t (ORCPT ); Thu, 30 Apr 2020 07:57:49 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id E15CF40AA3; Thu, 30 Apr 2020 11:57:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588247837; bh=hD8MO8nZG7cWOQMyvrg2gESOCiX1BXG9t5neHczu/iA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D8wXvgqCTX6Uko1bPgFR6lOJoYSEj7v07e1Ho0LMBR+CpTcs9mNXJrPttT8rs4AmC 9YBf7DM47wwisU+aOpA1BbM3Ur6xrfHN7l02pIJStOY2D1ElzXHCu4uO89DkqoiD7D lGGTD80vRcDJ/TwyKor/2zhN6fvvyyNxgnnJqWexLQT/0d3W/79WQ78KaqMQPJDyMg xZ4owK6MhS0sp3nfR3omdOm6U4gS67s/i2CVwi7wc6atxbgtudq1ZHLB25laEWqRE4 mtjnbxUa24O9j4aVALrO7FzvanTGF54gvT9I0O3KrruPb+JK+SsKdV9H+WwTbOAwdv Ue4bkpYbSq3Pg== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v3 6/6] ARM: dts: sun6i: Use syscon-based implementation for gmac Date: Thu, 30 Apr 2020 14:57:02 +0300 Message-Id: <20200430115702.5768-7-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200430115702.5768-1-plaes@plaes.org> References: <20200430115702.5768-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use syscon-based approach to access gmac clock configuration register instead of relying on a custom clock driver. As a bonus, we can now drop the custom clock implementation and the dummy clocks. Signed-off-by: Priit Laes --- arch/arm/boot/dts/sun6i-a31.dtsi | 35 +++----------------------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index f3425a66fc0a..fcf8a242741f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -228,36 +228,6 @@ osc32k: clk-32k { clock-output-names = "ext_osc32k"; }; - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c200d0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c200d0 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; }; de: display-engine { @@ -943,11 +913,12 @@ i2c3: i2c@1c2b800 { gmac: ethernet@1c30000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&ccu>; reg = <0x01c30000 0x1054>; interrupts = ; interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ccu CLK_AHB1_EMAC>; + clock-names = "stmmaceth"; resets = <&ccu RST_AHB1_EMAC>; reset-names = "stmmaceth"; snps,pbl = <2>;