From patchwork Sun May 3 10:33:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 11524405 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0030B912 for ; Sun, 3 May 2020 10:35:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D08D320757 for ; Sun, 3 May 2020 10:35:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="YcfU/Paa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727916AbgECKfr (ORCPT ); Sun, 3 May 2020 06:35:47 -0400 Received: from [115.28.160.31] ([115.28.160.31]:57426 "EHLO mailbox.box.xen0n.name" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1727125AbgECKfr (ORCPT ); Sun, 3 May 2020 06:35:47 -0400 Received: from localhost.localdomain (unknown [116.236.177.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id DB61C600B4; Sun, 3 May 2020 18:35:43 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1588502144; bh=/Cdf57xJ/xIdBp8bMbuMoFQL6Kr5I+HS2hPKeglyOw8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YcfU/Paa+jz0AW8Lo2fNeQbPZaCEUg25eunZgFA5vfi0dn/SfrkkI3reMbeUa3a3N KZzAobhWAUZ/d6SbTQaMCnjqU9RRi64mX/5x5t3zJkgBba8TdxYrTNs13LvoeD3Bo2 0KE8TYFNgrGtgEN0ucA3XkHKxGxPLaeImfHdbUGI= From: WANG Xuerui To: linux-mips@vger.kernel.org Cc: WANG Xuerui , Huacai Chen , Jiaxun Yang Subject: [PATCH v2 1/4] MIPS: Loongson64: fix typos in loongson_regs.h Date: Sun, 3 May 2020 18:33:02 +0800 Message-Id: <20200503103304.40678-2-git@xen0n.name> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200502133846.40590-1-git@xen0n.name> References: <20200502133846.40590-1-git@xen0n.name> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Fix some symbol names to align with Loongson's User Manual wording. Also correct the comment in csr_readq() suggesting the wrong instruction in use. Fixes: 6a6f9b7dafd50efc ("MIPS: Loongson: Add CFUCFG&CSR support") Signed-off-by: WANG Xuerui Cc: Huacai Chen Cc: Jiaxun Yang --- arch/mips/include/asm/mach-loongson64/loongson_regs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h index 363a47a5d26e..07aab3c5b22c 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h @@ -77,12 +77,12 @@ static inline u32 read_cpucfg(u32 reg) #define LOONGSON_CFG2_LBT3 BIT(6) #define LOONGSON_CFG2_LBTMMU BIT(7) #define LOONGSON_CFG2_LPMP BIT(8) -#define LOONGSON_CFG2_LPMPREV GENMASK(11, 9) +#define LOONGSON_CFG2_LPMREV GENMASK(11, 9) #define LOONGSON_CFG2_LAMO BIT(12) #define LOONGSON_CFG2_LPIXU BIT(13) -#define LOONGSON_CFG2_LPIXUN BIT(14) -#define LOONGSON_CFG2_LZVP BIT(15) -#define LOONGSON_CFG2_LZVREV GENMASK(18, 16) +#define LOONGSON_CFG2_LPIXNU BIT(14) +#define LOONGSON_CFG2_LVZP BIT(15) +#define LOONGSON_CFG2_LVZREV GENMASK(18, 16) #define LOONGSON_CFG2_LGFTP BIT(19) #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20) #define LOONGSON_CFG2_LLFTP BIT(23) @@ -139,7 +139,7 @@ static inline u64 csr_readq(u32 reg) { u64 __res; - /* DWRCSR reg, val */ + /* DRDCSR reg, val */ __asm__ __volatile__( "parse_r __res,%0\n\t" "parse_r reg,%1\n\t" From patchwork Sat May 2 13:38:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 11523905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13EF392A for ; Sat, 2 May 2020 13:46:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD80A2071E for ; Sat, 2 May 2020 13:46:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="LwCFPJa1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728052AbgEBNqf (ORCPT ); Sat, 2 May 2020 09:46:35 -0400 Received: from [115.28.160.31] ([115.28.160.31]:46292 "EHLO mailbox.box.xen0n.name" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728034AbgEBNqf (ORCPT ); Sat, 2 May 2020 09:46:35 -0400 Received: from localhost.localdomain (unknown [116.236.177.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id F145860161; Sat, 2 May 2020 21:39:44 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1588426785; bh=Yn5Z+8DuiLQa/cJoX6ZPjTfvrkeW8daV39JuqCOjncU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LwCFPJa1IQlHNPrUJoiwMwVjqjsrAGXI4Hmf5pPaunBrgQ3YQgqLOROyMZzEkt1zg idYNXm3u1jnrRquGh59TYqbBSJhtEoIW+ALTHIC3MBV7N13eQ1JoNLSTdR1SrB9sWe OaQVPErj+VfZy97kh1eB4fm1ZG3EgBdHgy9rDuw4= From: WANG Xuerui To: linux-mips@vger.kernel.org Cc: WANG Xuerui , Huacai Chen , Jiaxun Yang Subject: [PATCH 2/4] MIPS: Loongson64: define offsets and known revisions for some CPUCFG features Date: Sat, 2 May 2020 21:38:44 +0800 Message-Id: <20200502133846.40590-3-git@xen0n.name> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200502133846.40590-1-git@xen0n.name> References: <20200502133846.40590-1-git@xen0n.name> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add the constants for easier and maintainable composition of CPUCFG values. Signed-off-by: WANG Xuerui Cc: Huacai Chen Cc: Jiaxun Yang --- .../asm/mach-loongson64/loongson_regs.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h index 3fa94c6ec3b9..8508afffdfd1 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h @@ -67,6 +67,8 @@ static inline u32 read_cpucfg(u32 reg) #define LOONGSON_CFG1_SFBP BIT(29) #define LOONGSON_CFG1_CDMAP BIT(30) +#define LOONGSON_CFG1_FPREV_OFFSET 1 + #define LOONGSON_CFG2 0x2 #define LOONGSON_CFG2_LEXT1 BIT(0) #define LOONGSON_CFG2_LEXT2 BIT(1) @@ -90,6 +92,13 @@ static inline u32 read_cpucfg(u32 reg) #define LOONGSON_CFG2_LCSRP BIT(27) #define LOONGSON_CFG2_LDISBLIKELY BIT(28) +#define LOONGSON_CFG2_LPMREV_OFFSET 9 +#define LOONGSON_CFG2_LPM_REV1 (1 << LOONGSON_CFG2_LPMREV_OFFSET) +#define LOONGSON_CFG2_LPM_REV2 (2 << LOONGSON_CFG2_LPMREV_OFFSET) +#define LOONGSON_CFG2_LVZREV_OFFSET 16 +#define LOONGSON_CFG2_LVZ_REV1 (1 << LOONGSON_CFG2_LVZREV_OFFSET) +#define LOONGSON_CFG2_LVZ_REV2 (2 << LOONGSON_CFG2_LVZREV_OFFSET) + #define LOONGSON_CFG3 0x3 #define LOONGSON_CFG3_LCAMP BIT(0) #define LOONGSON_CFG3_LCAMREV GENMASK(3, 1) @@ -97,6 +106,16 @@ static inline u32 read_cpucfg(u32 reg) #define LOONGSON_CFG3_LCAMKW GENMASK(19, 12) #define LOONGSON_CFG3_LCAMVW GENMASK(27, 20) +#define LOONGSON_CFG3_LCAMREV_OFFSET 1 +#define LOONGSON_CFG3_LCAM_REV1 (1 << LOONGSON_CFG3_LCAMREV_OFFSET) +#define LOONGSON_CFG3_LCAM_REV2 (2 << LOONGSON_CFG3_LCAMREV_OFFSET) +#define LOONGSON_CFG3_LCAMNUM_OFFSET 4 +#define LOONGSON_CFG3_LCAMNUM_REV1 (0x3f << LOONGSON_CFG3_LCAMNUM_OFFSET) +#define LOONGSON_CFG3_LCAMKW_OFFSET 12 +#define LOONGSON_CFG3_LCAMKW_REV1 (0x27 << LOONGSON_CFG3_LCAMKW_OFFSET) +#define LOONGSON_CFG3_LCAMVW_OFFSET 20 +#define LOONGSON_CFG3_LCAMVW_REV1 (0x3f << LOONGSON_CFG3_LCAMVW_OFFSET) + #define LOONGSON_CFG4 0x4 #define LOONGSON_CFG4_CCFREQ GENMASK(31, 0) From patchwork Sat May 2 13:38:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 11523909 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5359213B2 for ; Sat, 2 May 2020 13:46:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3196E21974 for ; Sat, 2 May 2020 13:46:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="r7DQWLtJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728035AbgEBNqg (ORCPT ); Sat, 2 May 2020 09:46:36 -0400 Received: from [115.28.160.31] ([115.28.160.31]:46296 "EHLO mailbox.box.xen0n.name" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728038AbgEBNqg (ORCPT ); Sat, 2 May 2020 09:46:36 -0400 Received: from localhost.localdomain (unknown [116.236.177.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 4547060162; Sat, 2 May 2020 21:39:49 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1588426789; bh=ONRtGOA4myqnZrJLa5c+bfIHlPkdzZQWJl5rHs3mfJA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r7DQWLtJ/OJM2slr13qfVQjX7i5oC4ujHJBiCrEMKOVaYmwaJMyDFTlUMo8PBSnsH uC+bBFeJuV/QY9DGm2Gr9Hr5fyIH2S11O0EG7UZBtKAjPZf7CCF4jjO+cZbnK060DT OK5ceSxCOa/dGgPXeZVLSeipAvsDG6bniPg1+6NI= From: WANG Xuerui To: linux-mips@vger.kernel.org Cc: WANG Xuerui , Huacai Chen , Jiaxun Yang Subject: [PATCH 3/4] MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bits Date: Sat, 2 May 2020 21:38:45 +0800 Message-Id: <20200502133846.40590-4-git@xen0n.name> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200502133846.40590-1-git@xen0n.name> References: <20200502133846.40590-1-git@xen0n.name> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org These are exposed to userland alternatively via the new CPUCFG instruction on Loongson-3A R4 and above. Add definitions for readback on older cores. Signed-off-by: WANG Xuerui Cc: Huacai Chen Cc: Jiaxun Yang --- arch/mips/include/asm/mipsregs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 796fe47cfd17..90f843c72774 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -681,6 +681,10 @@ #define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22) /* FTLB probability bits */ #define MIPS_CONF6_FTLBP_SHIFT (16) +/* Loongson-3 feature bits */ +#define MIPS_CONF6_LOONGSON_SCRAND (_ULCAST_(1) << 17) +#define MIPS_CONF6_LOONGSON_LLEXC (_ULCAST_(1) << 16) +#define MIPS_CONF6_LOONGSON_STFILL (_ULCAST_(1) << 8) #define MIPS_CONF7_WII (_ULCAST_(1) << 31) @@ -997,6 +1001,8 @@ #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2) /* Flush DTLB */ #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3) +/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */ +#define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8) /* Flush VTLB */ #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12) /* Flush FTLB */ From patchwork Sat May 2 13:38:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 11523913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E845D13B2 for ; Sat, 2 May 2020 13:46:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C758E24954 for ; Sat, 2 May 2020 13:46:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="C6z2V7Lq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727921AbgEBNqm (ORCPT ); Sat, 2 May 2020 09:46:42 -0400 Received: from [115.28.160.31] ([115.28.160.31]:46290 "EHLO mailbox.box.xen0n.name" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728040AbgEBNqm (ORCPT ); Sat, 2 May 2020 09:46:42 -0400 Received: from localhost.localdomain (unknown [116.236.177.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 3BB6E60163; Sat, 2 May 2020 21:39:54 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1588426794; bh=oxVNjtRq8JUgM/LjjKYrKIclzJt1khEVINObcmvL1N4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C6z2V7LqW7OBEzr14b/D4JN1mKEksbT7Z+wp5utkkfoMDVi8tCYlG1jydIMlyVkEV CDsBoPtz8aE1Ot7BbrUA7eLw7xOasop1e6+Zk/LGHAaXoyeNzPL408EsZBhKsEV01E eU8ClIBEqRmekKgyeEds/45CNnUg7q7CCl+hKV+U= From: WANG Xuerui To: linux-mips@vger.kernel.org Cc: WANG Xuerui , Huacai Chen , Jiaxun Yang , Tiezhu Yang Subject: [PATCH 4/4] MIPS: emulate CPUCFG instruction on older Loongson64 cores Date: Sat, 2 May 2020 21:38:46 +0800 Message-Id: <20200502133846.40590-5-git@xen0n.name> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200502133846.40590-1-git@xen0n.name> References: <20200502133846.40590-1-git@xen0n.name> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org CPUCFG is the instruction for querying processor characteristics on newer Loongson processors, much like CPUID of x86. Since the instruction is supposedly designed to provide a unified way to do feature detection (without having to, for example, parse /proc/cpuinfo which is too heavyweight), it is important to provide compatibility for older cores without native support. Fortunately, most of the fields can be synthesized without changes to semantics. Performance is not really big a concern, because feature detection logic is not expected to be invoked very often in typical userland applications. The instruction can't be emulated on LOONGSON_2EF cores, according to FlyGoat's experiments. Because the LWC2 opcode is assigned to other valid instructions on 2E and 2F, no RI exception is raised for us to intercept. So compatibility is only extended back furthest to Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix of various blocks from the 3A/3B models from a kernel perspective. This is lightly based on Loongson's work on their Linux 3.10 fork, for being the authority on the right feature flags to fill in, where things aren't otherwise discoverable. Signed-off-by: WANG Xuerui Cc: Huacai Chen Cc: Jiaxun Yang Cc: Tiezhu Yang Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang # Loongson-2K, 3B1500 --- arch/mips/Kconfig | 11 ++ arch/mips/include/asm/cpu-info.h | 9 ++ .../include/asm/mach-loongson64/cpucfg-emul.h | 67 +++++++++ arch/mips/kernel/cpu-probe.c | 129 ++++++++++++++++++ arch/mips/kernel/traps.c | 57 ++++++++ arch/mips/loongson64/Makefile | 1 + arch/mips/loongson64/cpucfg-emul.c | 80 +++++++++++ 7 files changed, 354 insertions(+) create mode 100644 arch/mips/include/asm/mach-loongson64/cpucfg-emul.h create mode 100644 arch/mips/loongson64/cpucfg-emul.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9f15539a6342..2ab189001917 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1508,6 +1508,17 @@ config CPU_LOONGSON3_WORKAROUNDS If unsure, please say Y. +config CPU_LOONGSON3_CPUCFG_EMULATION + bool "Emulate the CPUCFG instruction on older cores" + default y + depends on CPU_LOONGSON64 + help + Loongson-3A R4 and newer have the CPUCFG instruction available for + userland to query CPU capabilities, much like CPUID on x86. This + option provides emulation of the instruction on older cores. + + If unsure, please say Y. + config CPU_LOONGSON2E bool "Loongson 2E" depends on SYS_HAS_CPU_LOONGSON2E diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index ed7ffe4e63a3..43c238567a80 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -105,6 +105,15 @@ struct cpuinfo_mips { unsigned int gtoffset_mask; unsigned int guestid_mask; unsigned int guestid_cache; + +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + /* CPUCFG data for this CPU, synthesized at probe time. + * + * CPUCFG select 0 is PRId, others are unimplemented for now. So the + * only stored values are for CPUCFG selects 1-3 inclusive. + */ + u32 loongson3_cpucfg_data[3]; +#endif } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; diff --git a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h new file mode 100644 index 000000000000..b9f6b2aa98f9 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ +#define _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ + +#include + +#include + +#define LOONGSON_FPREV_MASK 0x7 + +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + +/* Finalize synthesis of CPUCFG data by patching the partially filled data + * with dynamically detected CPU characteristics. This keeps the amount of + * hard-coded logic at a minimum. + */ +void loongson3_cpucfg_finish_synthesis(struct cpuinfo_mips *c); + +static inline u32 loongson3_cpucfg_read_synthesized( + struct cpuinfo_mips *c, + __u64 sel) +{ + switch (sel) { + case LOONGSON_CFG0: + return c->processor_id; + case LOONGSON_CFG1: + case LOONGSON_CFG2: + case LOONGSON_CFG3: + return c->loongson3_cpucfg_data[sel - 1]; + case LOONGSON_CFG4: + case LOONGSON_CFG5: + /* CPUCFG selects 4 and 5 are related to the processor clock. + * Unimplemented for now. + */ + return 0; + case LOONGSON_CFG6: + /* CPUCFG select 6 is for the undocumented Safe Extension. */ + return 0; + case LOONGSON_CFG7: + /* CPUCFG select 7 is for the virtualization extension. + * We don't know if the two currently known features are + * supported on older cores according to the public + * documentation, so leave this at zero. + */ + return 0; + } + + /* + * Return 0 for unrecognized CPUCFG selects, which is real hardware + * behavior observed on Loongson 3A R4. + */ + return 0; +} +#else +static void loongson3_cpucfg_finish_synthesis(struct cpuinfo_mips *c) +{ +} + +static inline u32 loongson3_cpucfg_read_synthesized( + struct cpuinfo_mips *c, + __u64 sel) +{ + return 0; +} +#endif + +#endif /* _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ca2e6f1af4fe..907e31ff562f 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -28,6 +28,8 @@ #include #include +#include + /* Hardware capabilities */ unsigned int elf_hwcap __read_mostly; EXPORT_SYMBOL_GPL(elf_hwcap); @@ -1580,6 +1582,24 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) set_isa(c, MIPS_CPU_ISA_M64R1); c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT); +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + /* Add CPUCFG features non-discoverable otherwise. */ + c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 | + LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA | + LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC); + c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 | + LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1); + c->loongson3_cpucfg_data[2] |= ( + LOONGSON_CFG3_LCAM_REV1 | + LOONGSON_CFG3_LCAMNUM_REV1 | + LOONGSON_CFG3_LCAMKW_REV1 | + LOONGSON_CFG3_LCAMVW_REV1); + + /* This feature is set by firmware, but all known + * Loongson-3A Legacy systems are configured this way. + */ + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP; +#endif break; case PRID_REV_LOONGSON3B_R1: case PRID_REV_LOONGSON3B_R2: @@ -1589,6 +1609,24 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) set_isa(c, MIPS_CPU_ISA_M64R1); c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT); +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + /* Add CPUCFG features non-discoverable otherwise. */ + c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 | + LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA | + LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC); + c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 | + LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1); + c->loongson3_cpucfg_data[2] |= ( + LOONGSON_CFG3_LCAM_REV1 | + LOONGSON_CFG3_LCAMNUM_REV1 | + LOONGSON_CFG3_LCAMKW_REV1 | + LOONGSON_CFG3_LCAMVW_REV1); + + /* This feature is set by firmware, but all known + * Loongson-3B Legacy systems are configured this way. + */ + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP; +#endif break; } @@ -1957,9 +1995,57 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c) c->ases |= MIPS_ASE_LOONGSON_CAM; } +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION +static inline int cpu_has_uca(void) +{ + u32 diag = read_c0_diag(); + u32 new_diag; + + if (diag & LOONGSON_DIAG_UCAC) + /* UCA is already enabled. */ + return 1; + + /* See if UCAC bit can be flipped on. This should be safe. */ + new_diag = diag | LOONGSON_DIAG_UCAC; + write_c0_diag(new_diag); + new_diag = read_c0_diag(); + write_c0_diag(diag); + + return (new_diag & LOONGSON_DIAG_UCAC) != 0; +} + +static inline void probe_uca(struct cpuinfo_mips *c) +{ + if (cpu_has_uca()) + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LSUCA; +} + +static inline void decode_loongson_config6(struct cpuinfo_mips *c) +{ + u32 config6 = read_c0_config6(); + + if (config6 & MIPS_CONF6_LOONGSON_STFILL) + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP; + if (config6 & MIPS_CONF6_LOONGSON_LLEXC) + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC; + if (config6 & MIPS_CONF6_LOONGSON_SCRAND) + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND; +} +#else +static inline void probe_uca(struct cpuinfo_mips *c) +{ +} + +static inline void decode_loongson_config6(struct cpuinfo_mips *c) +{ +} +#endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */ + static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); + decode_loongson_config6(c); + probe_uca(c); switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ @@ -1977,6 +2063,21 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) c->writecombine = _CACHE_UNCACHED_ACCELERATED; c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + /* Add CPUCFG features non-discoverable otherwise. */ + c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 | + LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC | + LOONGSON_CFG1_TGTSYNC); + c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 | + LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP | + LOONGSON_CFG2_LPM_REV2); + c->loongson3_cpucfg_data[2] = 0; + + /* This feature is set by firmware, but all known Loongson-2K + * systems are configured this way. + */ + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP; +#endif break; case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */ switch (c->processor_id & PRID_REV_MASK) { @@ -2007,6 +2108,26 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) c->writecombine = _CACHE_UNCACHED_ACCELERATED; c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + /* Add CPUCFG features non-discoverable otherwise. */ + c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_CNT64 | + LOONGSON_CFG1_LSLDR0 | LOONGSON_CFG1_LSPREF | + LOONGSON_CFG1_LSPREFX | LOONGSON_CFG1_LSSYNCI | + LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC); + c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 | + LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LBTMMU | + LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1 | + LOONGSON_CFG2_LVZ_REV1); + c->loongson3_cpucfg_data[2] |= (LOONGSON_CFG3_LCAM_REV1 | + LOONGSON_CFG3_LCAMNUM_REV1 | + LOONGSON_CFG3_LCAMKW_REV1 | + LOONGSON_CFG3_LCAMVW_REV1); + + /* This feature is set by firmware, but all known Loongson-3 + * systems are configured this way. + */ + c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP; +#endif break; case PRID_IMP_LOONGSON_64G: c->cputype = CPU_LOONGSON64; @@ -2200,6 +2321,12 @@ void cpu_probe(void) c->fpu_csr31 = FPU_CSR_RN; c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + c->loongson3_cpucfg_data[0] = 0; + c->loongson3_cpucfg_data[1] = 0; + c->loongson3_cpucfg_data[2] = 0; +#endif + c->processor_id = read_c0_prid(); switch (c->processor_id & PRID_COMP_MASK) { case PRID_COMP_LEGACY: @@ -2333,6 +2460,8 @@ void cpu_probe(void) if (cpu_has_vz) cpu_probe_vz(c); + loongson3_cpucfg_finish_synthesis(c); + cpu_probe_vmbits(c); #ifdef CONFIG_64BIT diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 31968cbd6464..0c77ca2f091b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -71,6 +71,8 @@ #include #include +#include + extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); extern asmlinkage void handle_int(void); @@ -693,6 +695,56 @@ static int simulate_sync(struct pt_regs *regs, unsigned int opcode) return -1; /* Must be something else ... */ } +/* + * Loongson-3 CSR instructions emulation + */ + +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + +#define LWC2 0xc8000000 +#define RS BASE +#define CSR_OPCODE2 0x00000118 +#define CSR_OPCODE2_MASK 0x000007ff +#define CSR_FUNC_MASK RT +#define CSR_FUNC_CPUCFG 0x8 + +static int simulate_loongson3_csr_cpucfg(struct pt_regs *regs, + unsigned int opcode) +{ + int rd = (opcode & RD) >> 11; + int rs = (opcode & RS) >> 21; + __u64 sel = regs->regs[rs]; + + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); + + regs->regs[rd] = loongson3_cpucfg_read_synthesized(¤t_cpu_data, + sel); + + return 0; +} + +static int simulate_loongson3_csr(struct pt_regs *regs, unsigned int opcode) +{ + int op = opcode & OPCODE; + int op2 = opcode & CSR_OPCODE2_MASK; + + if (op == LWC2 && op2 == CSR_OPCODE2) { + int csr_func = (opcode & CSR_FUNC_MASK) >> 16; + + switch (csr_func) { + case CSR_FUNC_CPUCFG: + return simulate_loongson3_csr_cpucfg(regs, opcode); + } + + /* Unrecognized Loongson-3 CSR instruction. */ + return -1; + } + + /* Not ours. */ + return -1; +} +#endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */ + asmlinkage void do_ov(struct pt_regs *regs) { enum ctx_state prev_state; @@ -1166,6 +1218,11 @@ asmlinkage void do_ri(struct pt_regs *regs) if (status < 0) status = simulate_fp(regs, opcode, old_epc, old31); + +#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION + if (status < 0) + status = simulate_loongson3_csr(regs, opcode); +#endif } else if (cpu_has_mmips) { unsigned short mmop[2] = { 0 }; diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile index 6f3c2b47f66f..61f6add20530 100644 --- a/arch/mips/loongson64/Makefile +++ b/arch/mips/loongson64/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_NUMA) += numa.o obj-$(CONFIG_RS780_HPET) += hpet.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_SUSPEND) += pm.o +obj-$(CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION) += cpucfg-emul.o diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c new file mode 100644 index 000000000000..a30f82b55c9e --- /dev/null +++ b/arch/mips/loongson64/cpucfg-emul.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include + +#include +#include + +static u32 get_loongson_fprev(struct cpuinfo_mips *c) +{ + return (c->fpu_id & LOONGSON_FPREV_MASK) << LOONGSON_CFG1_FPREV_OFFSET; +} + +static void patch_cpucfg_sel1(struct cpuinfo_mips *c) +{ + u64 ases = c->ases; + u64 options = c->options; + u32 data = c->loongson3_cpucfg_data[0]; + + if (options & MIPS_CPU_FPU) { + data |= LOONGSON_CFG1_FP; + data |= get_loongson_fprev(c); + } + if (ases & MIPS_ASE_LOONGSON_MMI) + data |= LOONGSON_CFG1_MMI; + if (ases & MIPS_ASE_MSA) + data |= LOONGSON_CFG1_MSA1; + + c->loongson3_cpucfg_data[0] = data; +} + +static void patch_cpucfg_sel2(struct cpuinfo_mips *c) +{ + u64 ases = c->ases; + u64 options = c->options; + u32 data = c->loongson3_cpucfg_data[1]; + + if (ases & MIPS_ASE_LOONGSON_EXT) + data |= LOONGSON_CFG2_LEXT1; + if (ases & MIPS_ASE_LOONGSON_EXT2) + data |= LOONGSON_CFG2_LEXT2; + if (options & MIPS_CPU_LDPTE) + data |= LOONGSON_CFG2_LSPW; + + if (ases & MIPS_ASE_VZ) + data |= LOONGSON_CFG2_LVZP; + else + data &= ~LOONGSON_CFG2_LVZREV; + + c->loongson3_cpucfg_data[1] = data; +} + +static void patch_cpucfg_sel3(struct cpuinfo_mips *c) +{ + u64 ases = c->ases; + u32 data = c->loongson3_cpucfg_data[2]; + + if (ases & MIPS_ASE_LOONGSON_CAM) { + data |= LOONGSON_CFG3_LCAMP; + } else { + data &= ~LOONGSON_CFG3_LCAMREV; + data &= ~LOONGSON_CFG3_LCAMNUM; + data &= ~LOONGSON_CFG3_LCAMKW; + data &= ~LOONGSON_CFG3_LCAMVW; + } + + c->loongson3_cpucfg_data[2] = data; +} + +void loongson3_cpucfg_finish_synthesis(struct cpuinfo_mips *c) +{ + /* CPUs with CPUCFG support don't need to synthesize anything. */ + if (cpu_has_cfg()) + return; + + patch_cpucfg_sel1(c); + patch_cpucfg_sel2(c); + patch_cpucfg_sel3(c); +}