From patchwork Sun May 3 20:18:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11524741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45AC6139A for ; Sun, 3 May 2020 20:18:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2592B206F1 for ; Sun, 3 May 2020 20:18:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="OmPEUSR/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729108AbgECUSp (ORCPT ); Sun, 3 May 2020 16:18:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729026AbgECUSp (ORCPT ); Sun, 3 May 2020 16:18:45 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F821C061A0E for ; Sun, 3 May 2020 13:18:43 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id d15so18482097wrx.3 for ; Sun, 03 May 2020 13:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pZbT+0Oo6gju/el56kGkKejtrVoHm+BJeWgEyTMdD/U=; b=OmPEUSR/qkLCaf/PW5Tun+H76mbrD5211OIGssp0z4pgPntDvsAVWr6anhTZAoN0mt 4LaxsMrDcXnHzRLhPn1nPcqE9NvQauxbqPuVOQoYEDpes8+8OdAcWrxT48EiZ86rwBw5 ZYzxXrx3QaZ/L1XK/D4FbBpxRe6GtDYKOrA6zGzh1OxUWxlkH3XVvXz99r52OmYiH9Za N5bUidfH9TyzlASs2jdol6ohIbRlbqO3ycwg6oj/jQvMij/eSHe7Pkg8UOnQhU48FwTj agia9P7LTmw7dLnv85kdJS6HPPdxpJJ03YmROV/eq8Cag05IG+wurCFAnboDRLY1ly8w rTgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pZbT+0Oo6gju/el56kGkKejtrVoHm+BJeWgEyTMdD/U=; b=gIh7q/zujWaSiOUfY6HbfBj2zqlcCbYbXjw4qIayX1+y/6YnccsUWXqSBwm8P2FFj9 u4v8tnQdL33KbTkEc8dUByuinu27EEPQdNf9D9MK2CYvRylixa7WUyIICuFwp7kI6ye0 BnkTTa9xMQrUDdsAbkHU+Gi76AXZi1B9VULp26uePsL1vdgNkpPTRnV3Ne79HeFhrhjc TNb5TxjRCpFVmHcckGOb9BKDS51SJ0mKljcL/ni0k9bi/7fRjdH05sKxPc7ugnNBxwo+ qELqi3coDPwl1XnhtXxRy4QWLtaBFZ+158A+TuzqasWM5NlGUgplUSoYZhn3Fu2DVXUa sqSw== X-Gm-Message-State: AGi0PuYEtQwgVC5djShPNbDxuODq3jufw1RBlEqNIVxy7CU9sIEEy5hO t4kCq6SPHLWCgpIggHP19UKr4Q== X-Google-Smtp-Source: APiQypK+XbE1NSpxwnTrxbNWg9DeBQFObrkw4sunojynARheacuhqjpF9C30xcMuD9/gd4t0L7tViA== X-Received: by 2002:adf:ec07:: with SMTP id x7mr9958050wrn.416.1588537122008; Sun, 03 May 2020 13:18:42 -0700 (PDT) Received: from localhost.localdomain ([2a0e:b107:830:0:47e5:c676:4796:5818]) by smtp.googlemail.com with ESMTPSA id 19sm9891624wmo.3.2020.05.03.13.18.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 May 2020 13:18:41 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, vkoul@kernel.org Cc: Robert Marko , John Crispin , Luka Perkov Subject: [PATCH v7 1/3] phy: add driver for Qualcomm IPQ40xx USB PHY Date: Sun, 3 May 2020 22:18:22 +0200 Message-Id: <20200503201823.531757-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: John Crispin Signed-off-by: Robert Marko Cc: Luka Perkov --- Changes from v6 to v7: * Use of_device_get_match_data() instead of of_match_device() and then passing that to devm_phy_create() Changes from v2 to v3: * Remove magic writes as they are not needed * Correct commit message drivers/phy/qualcomm/Kconfig | 7 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 148 ++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 98674ed094d9..b86f9556df85 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -18,6 +18,13 @@ config PHY_QCOM_APQ8064_SATA depends on OF select GENERIC_PHY +config PHY_QCOM_IPQ4019_USB + tristate "Qualcomm IPQ4019 USB PHY driver" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. + config PHY_QCOM_IPQ806X_SATA tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" depends on ARCH_QCOM diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 1f14aeacbd70..41746781de73 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o +obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c new file mode 100644 index 000000000000..b8ef331e1545 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 John Crispin + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ipq4019_usb_phy { + struct device *dev; + struct phy *phy; + void __iomem *base; + struct reset_control *por_rst; + struct reset_control *srif_rst; +}; + +static int ipq4019_ss_phy_power_off(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + reset_control_assert(phy->por_rst); + msleep(10); + + return 0; +} + +static int ipq4019_ss_phy_power_on(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + ipq4019_ss_phy_power_off(_phy); + + reset_control_deassert(phy->por_rst); + + return 0; +} + +static struct phy_ops ipq4019_usb_ss_phy_ops = { + .power_on = ipq4019_ss_phy_power_on, + .power_off = ipq4019_ss_phy_power_off, +}; + +static int ipq4019_hs_phy_power_off(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + reset_control_assert(phy->por_rst); + msleep(10); + + reset_control_assert(phy->srif_rst); + msleep(10); + + return 0; +} + +static int ipq4019_hs_phy_power_on(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + ipq4019_hs_phy_power_off(_phy); + + reset_control_deassert(phy->srif_rst); + msleep(10); + + reset_control_deassert(phy->por_rst); + + return 0; +} + +static struct phy_ops ipq4019_usb_hs_phy_ops = { + .power_on = ipq4019_hs_phy_power_on, + .power_off = ipq4019_hs_phy_power_off, +}; + +static const struct of_device_id ipq4019_usb_phy_of_match[] = { + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops}, + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops}, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match); + +static int ipq4019_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct phy_provider *phy_provider; + struct ipq4019_usb_phy *phy; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->dev = &pdev->dev; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + phy->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(phy->base)) { + dev_err(dev, "failed to remap register memory\n"); + return PTR_ERR(phy->base); + } + + phy->por_rst = devm_reset_control_get(phy->dev, "por_rst"); + if (IS_ERR(phy->por_rst)) { + if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER) + dev_err(dev, "POR reset is missing\n"); + return PTR_ERR(phy->por_rst); + } + + phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst"); + if (IS_ERR(phy->srif_rst)) + return PTR_ERR(phy->srif_rst); + + phy->phy = devm_phy_create(dev, NULL, of_device_get_match_data(dev)); + if (IS_ERR(phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(phy->phy); + } + phy_set_drvdata(phy->phy, phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver ipq4019_usb_phy_driver = { + .probe = ipq4019_usb_phy_probe, + .driver = { + .of_match_table = ipq4019_usb_phy_of_match, + .name = "ipq4019-usb-phy", + } +}; +module_platform_driver(ipq4019_usb_phy_driver); + +MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); +MODULE_AUTHOR("John Crispin "); +MODULE_LICENSE("GPL v2"); From patchwork Sun May 3 20:18:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11524745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FA95912 for ; Sun, 3 May 2020 20:18:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 259B720746 for ; Sun, 3 May 2020 20:18:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="vZXEB2ep" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729119AbgECUSs (ORCPT ); Sun, 3 May 2020 16:18:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729118AbgECUSr (ORCPT ); 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Sun, 03 May 2020 13:18:44 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, vkoul@kernel.org Cc: Robert Marko , John Crispin , Rob Herring , Luka Perkov Subject: [PATCH v7 2/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document Date: Sun, 3 May 2020 22:18:23 +0200 Message-Id: <20200503201823.531757-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200503201823.531757-1-robert.marko@sartura.hr> References: <20200503201823.531757-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the binding documentation for the HS/SS USB PHY found inside Qualcom Dakota SoCs. Signed-off-by: John Crispin Signed-off-by: Robert Marko Reviewed-by: Rob Herring Cc: Luka Perkov --- Changes from v5 to v6: * Add missing include for reset defines in example * Fix warning for missing # in #phy-cells Changes from v4 to v5: * Replace tabs with whitespaces * Add maintainer property .../bindings/phy/qcom-usb-ipq4019-phy.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml new file mode 100644 index 000000000000..1118fe69b611 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcom IPQ40xx Dakota HS/SS USB PHY + +maintainers: + - Robert Marko + +properties: + compatible: + enum: + - qcom,usb-ss-ipq4019-phy + - qcom,usb-hs-ipq4019-phy + + reg: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: por_rst + - const: srif_rst + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - resets + - reset-names + - "#phy-cells" + +examples: + - | + #include + + hsphy@a8000 { + #phy-cells = <0>; + compatible = "qcom,usb-hs-ipq4019-phy"; + reg = <0xa8000 0x40>; + resets = <&gcc USB2_HSPHY_POR_ARES>, + <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + }; From patchwork Sun May 3 20:18:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11524743 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DBAEC139A for ; Sun, 3 May 2020 20:18:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C439920752 for ; Sun, 3 May 2020 20:18:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="qK4+PH8g" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729134AbgECUSv (ORCPT ); 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Sun, 03 May 2020 13:18:46 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, vkoul@kernel.org Cc: John Crispin , Robert Marko , Luka Perkov Subject: [PATCH v7 3/3] ARM: dts: qcom: ipq4019: add USB devicetree nodes Date: Sun, 3 May 2020 22:18:24 +0200 Message-Id: <20200503201823.531757-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200503201823.531757-1-robert.marko@sartura.hr> References: <20200503201823.531757-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: John Crispin Since we now have driver for the USB PHY, lets add the necessary nodes to DTSI. Signed-off-by: John Crispin Signed-off-by: Robert Marko Cc: Luka Perkov Reviewed-by: Vinod Koul --- Changes from v6 to v7: * Remove changes to qcom-ipq4019-ap.dk01.1.dtsi It has slipped in unwanted, we only want to add nodes to the DTSI. arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bfa9ce4c6e69..ee45253361cb 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -604,5 +604,79 @@ reg = <4>; }; }; + + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; + reg = <0x9a000 0x800>; + reg-names = "phy_base"; + resets = <&gcc USB3_UNIPHY_PHY_ARES>; + reset-names = "por_rst"; + status = "disabled"; + }; + + usb3_hs_phy: hsphy@a6000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa6000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb3@8af8800 { + compatible = "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB3_MASTER_CLK>, + <&gcc GCC_USB3_SLEEP_CLK>, + <&gcc GCC_USB3_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xf8000>; + interrupts = ; + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + }; + }; + + usb2_hs_phy: hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa8000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb2@60f8800 { + compatible = "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB2_MASTER_CLK>, + <&gcc GCC_USB2_SLEEP_CLK>, + <&gcc GCC_USB2_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@6000000 { + compatible = "snps,dwc3"; + reg = <0x6000000 0xf8000>; + interrupts = ; + phys = <&usb2_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + }; + }; }; };