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Wed, 06 May 2020 10:49:12 -0700 (PDT) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] iommu/arm-smmu-v3: Don't reserve implementation defined register space Date: Wed, 6 May 2020 19:46:30 +0200 Message-Id: <20200506174629.1504153-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200506_104914_924743_A77F21A0 X-CRM114-Status: GOOD ( 14.70 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:441 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jean-Philippe Brucker , lorenzo.pieralisi@arm.com, will@kernel.org, joro@8bytes.org, tuanphan@amperemail.onmicrosoft.com, robin.murphy@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Some SMMUv3 implementation embed the Perf Monitor Group Registers (PMCG) inside the first 64kB region of the SMMU. Since PMCG are managed by a separate driver, this layout causes resource reservation conflicts during boot. To avoid this conflict, only reserve the MMIO region we actually use: the first 0xe0 bytes of page 0 and the first 0xd0 bytes of page 1. Although devm_ioremap() still works on full pages under the hood, this way we benefit from resource conflict checks. Signed-off-by: Jean-Philippe Brucker --- A nicer (and hopefully working) solution to the problem dicussed here: https://lore.kernel.org/linux-iommu/20200421155745.19815-1-jean-philippe@linaro.org/ --- drivers/iommu/arm-smmu-v3.c | 50 +++++++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 82508730feb7a1..fc85cdd5b62cca 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -171,6 +171,9 @@ #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc +#define ARM_SMMU_PAGE0_REG_SZ 0xe0 +#define ARM_SMMU_PAGE1_REG_SZ 0xd0 + /* Common MSI config fields */ #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) #define MSI_CFG2_SH GENMASK(5, 4) @@ -628,6 +631,7 @@ struct arm_smmu_strtab_cfg { struct arm_smmu_device { struct device *dev; void __iomem *base; + void __iomem *page1; #define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) #define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) @@ -733,11 +737,14 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset, struct arm_smmu_device *smmu) { - if ((offset > SZ_64K) && - (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY)) - offset -= SZ_64K; + void __iomem *base = smmu->base; - return smmu->base + offset; + if (offset > SZ_64K) { + offset -= SZ_64K; + if (smmu->page1) + base = smmu->page1; + } + return base + offset; } static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) @@ -4021,6 +4028,28 @@ err_reset_pci_ops: __maybe_unused; return err; } +static void __iomem *arm_smmu_ioremap(struct device *dev, + resource_size_t start, + resource_size_t size) +{ + void __iomem *dest_ptr; + struct resource *res; + + res = devm_request_mem_region(dev, start, size, dev_name(dev)); + if (!res) { + dev_err(dev, "can't request SMMU region %pa\n", &start); + return IOMEM_ERR_PTR(-EINVAL); + } + + dest_ptr = devm_ioremap(dev, start, size); + if (!dest_ptr) { + dev_err(dev, "ioremap failed for SMMU region %pR\n", res); + devm_release_mem_region(dev, start, size); + dest_ptr = IOMEM_ERR_PTR(-ENOMEM); + } + return dest_ptr; +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -4056,10 +4085,21 @@ static int arm_smmu_device_probe(struct platform_device *pdev) } ioaddr = res->start; - smmu->base = devm_ioremap_resource(dev, res); + /* + * Only map what we need, because the IMPLEMENTATION DEFINED registers + * may be used for the PMCGs, which are reserved by the PMU driver. + */ + smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_PAGE0_REG_SZ); if (IS_ERR(smmu->base)) return PTR_ERR(smmu->base); + if (arm_smmu_resource_size(smmu) > SZ_64K) { + smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, + ARM_SMMU_PAGE1_REG_SZ); + if (IS_ERR(smmu->page1)) + return PTR_ERR(smmu->page1); + } + /* Interrupt lines */ irq = platform_get_irq_byname_optional(pdev, "combined");