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Mon, 8 Oct 2018 09:33:27 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/exynos: fimd: Make plane alpha configurable Date: Mon, 8 Oct 2018 11:33:01 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538991182-12961-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJKsWRmVeSWpSXmKPExsWy7djPc7qZKrujDe42s1jcWneO1aL33Ekm i40z1rNaHN+9lNHiytf3bBaT7k9gsXhx7yKLRf/j18wW589vYLc42/SG3WLT42usFpd3zWGz mHF+H5PF2iN32S1mTH7J5sDvsWlVJ5vH9m8PWD3udx9n8ti8pN6jb8sqRo/Pm+QC2KK4bFJS czLLUov07RK4MjZM2sNacFej4tvh66wNjEcVuxg5OSQETCQezOtl6mLk4hASWMEosWjlNWYI 5wujxKkbHawgVUICnxklfp9hg+loOneWFaJoOaPEusc9bHAdz5+/BKtiEzCVuH33E5gtIqAs 8XfiKkaQImaBrSwSe0/eYAJJCAu4SPyYu5kFxGYRUJW4un43E8QKOYmb5zqZQWxOAU+Jg3tW sIA0SwhsYpe49uAhWIJXoEzi4mGIZgmgQRNXrYVqFpZ4dXwLO4QtI3F6cg9UczOjxK0v11gh nAmMEgdXd0F1W0tsuvEKqJsD6D5NifW79CHCjhJHpvWxgIQlBPgkbrwVBAkzA5mTtk1nhgjz SnS0CUFUq0m83rKFDWbti89fGSFsD4nVvw+yQ0Kok0ni8pZL7BMY5WchLFvAyLiKUTy1tDg3 PbXYKC+1XK84Mbe4NC9dLzk/dxMjMAGd/nf8yw7GXX+SDjEKcDAq8fCuCNgVLcSaWFZcmXuI UYKDWUmEV3Q7UIg3JbGyKrUoP76oNCe1+BCjNAeLkjjvsnkbo4UE0hNLUrNTUwtSi2CyTByc Ug2M8zhfTas3a7dj6shLLNBOXdh4d3WnYfT+Q2pJXXZXdoV0bAk/dehvO8Pv0/lx35ofPOlY sPX2TemXKTPF8v7vq6y23i95OcxO0+nOPLbW31nmc4MCzmnrfY1xaLBgnHo8cEFW+a7qic25 V/dvVJ7yy2zRjIZCmZTJdyzF/+d8lv31NXzPk9Y8JZbijERDLeai4kQA9xbudzwDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e/4Pd0Mld3RBle3sFncWneO1aL33Ekm i40z1rNaHN+9lNHiytf3bBaT7k9gsXhx7yKLRf/j18wW589vYLc42/SG3WLT42usFpd3zWGz mHF+H5PF2iN32S1mTH7J5sDvsWlVJ5vH9m8PWD3udx9n8ti8pN6jb8sqRo/Pm+QC2KL0bIry S0tSFTLyi0tslaINLYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLLUov07RL0MjZM2sNacFej 4tvh66wNjEcVuxg5OSQETCSazp1l7WLk4hASWMooce5iNwtEQkZi3tk+NghbWOLPtS42iKJP jBK/H7czgyTYBEwlbt/9BFYkIqAs8XfiKkaQImaBgywSLRvPMIIkhAVcJH7M3Qw2lUVAVeLq +t1MIDavgIfEyeUHmCA2yEncPNcJNpRTwFPi4J4VLBDbtjJKzNnbyDqBkW8BI8MqRpHU0uLc 9NxiI73ixNzi0rx0veT83E2MwIjYduznlh2MXe+CDzEKcDAq8fCuCNgVLcSaWFZcmXuIUYKD WUmEV3Q7UIg3JbGyKrUoP76oNCe1+BCjKdBVE5mlRJPzgdGaVxJvaGpobmFpaG5sbmxmoSTO e96gMkpIID2xJDU7NbUgtQimj4mDU6qBkV1/+zLWg3xtP5QLHHMn3K7YlPlnanAgd+cVJc87 TS2WKyz09GWz3lw4ZVo/6b8G2/Rl762mODQ1/WnbLflELft2atq9lRbSb4KnPWvs80t4VPOh WJWZa9/frij2A3f9+jj2Nx/nOnHLQT+61DQ78c7dBuN7J05Na7m7yX933h0hD59dCpL3lViK MxINtZiLihMB01pxdJ4CAAA= Message-Id: <20181008093328eucas1p2c00d65c7f8451f7628f630934c992185~bmFmklSgF0357503575eucas1p25@eucas1p2.samsung.com> X-CMS-MailID: 20181008093328eucas1p2c00d65c7f8451f7628f630934c992185 X-Msg-Generator: CA X-RootMTR: 20181008093328eucas1p2c00d65c7f8451f7628f630934c992185 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181008093328eucas1p2c00d65c7f8451f7628f630934c992185 References: <20181003094053eucas1p107c7a8a60c48dd68625fdaa223ef1996~aD9p3GwpI1866618666eucas1p1B@eucas1p1.samsung.com> <1538991182-12961-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Tue, 09 Oct 2018 07:34:35 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The fimd hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TRATS2 with Exynos 4412 CPU, on top of exynos-drm-next. Signed-off-by: Christoph Manszewski --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 69 +++++++++++++++++++++++--------- include/video/samsung_fimd.h | 1 + 2 files changed, 51 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index b7f56935a46b..06d5d2422246 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -229,6 +229,21 @@ static const uint32_t fimd_formats[] = { DRM_FORMAT_ARGB8888, }; +static const unsigned int capabilities[WINDOWS_NR] = { + 0, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, +}; + +static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, + u32 val) +{ + val = (val & mask) | (readl(ctx->regs + reg) & ~mask); + writel(val, ctx->regs + reg); +} + static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) { struct fimd_context *ctx = crtc->ctx; @@ -552,10 +567,38 @@ static void fimd_commit(struct exynos_drm_crtc *crtc) writel(val, ctx->regs + VIDCON0); } +static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, + struct drm_framebuffer *fb) +{ + struct exynos_drm_plane plane = ctx->planes[win]; + struct exynos_drm_plane_state *state = + to_exynos_plane_state(plane.base.state); + unsigned int alpha = state->base.alpha; + u32 win_alpha = alpha >> 8; + u32 val = 0; + + /* OSD alpha */ + val = VIDISD14C_ALPHA0_R(alpha >> 4) | + VIDISD14C_ALPHA0_G(win_alpha >> 4) | + VIDISD14C_ALPHA0_B(win_alpha >> 4) | + VIDISD14C_ALPHA1_R(win_alpha >> 4) | + VIDISD14C_ALPHA1_G(win_alpha >> 4) | + VIDISD14C_ALPHA1_B(win_alpha >> 4); + + writel(val, ctx->regs + VIDOSD_C(win)); + + val = VIDW_ALPHA_R(win_alpha & 0xf) | VIDW_ALPHA_G(win_alpha & 0xf) | + VIDW_ALPHA_G(win_alpha & 0xf); + writel(val, ctx->regs + VIDWnALPHA0(win)); + writel(val, ctx->regs + VIDWnALPHA1(win)); + fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, + BLENDCON_NEW_8BIT_ALPHA_VALUE); +} static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, - uint32_t pixel_format, int width) + struct drm_framebuffer *fb, int width) { + uint32_t pixel_format = fb->format->format; unsigned long val; val = WINCONx_ENWIN; @@ -596,6 +639,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; val |= WINCONx_WSWP; val |= WINCONx_BURSTLEN_16WORD; + val |= WINCON1_ALPHA_MUL; break; } @@ -607,7 +651,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, * still better to change dma-burst than displaying garbage. */ - if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { + if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { val &= ~WINCONx_BURSTLEN_MASK; val |= WINCONx_BURSTLEN_4WORD; } @@ -615,22 +659,8 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, writel(val, ctx->regs + WINCON(win)); /* hardware window 0 doesn't support alpha channel. */ - if (win != 0) { - /* OSD alpha */ - val = VIDISD14C_ALPHA0_R(0xf) | - VIDISD14C_ALPHA0_G(0xf) | - VIDISD14C_ALPHA0_B(0xf) | - VIDISD14C_ALPHA1_R(0xf) | - VIDISD14C_ALPHA1_G(0xf) | - VIDISD14C_ALPHA1_B(0xf); - - writel(val, ctx->regs + VIDOSD_C(win)); - - val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | - VIDW_ALPHA_G(0xf); - writel(val, ctx->regs + VIDWnALPHA0(win)); - writel(val, ctx->regs + VIDWnALPHA1(win)); - } + if (win != 0) + fimd_win_set_bldmod(ctx, win, fb); } static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) @@ -786,7 +816,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); } - fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w); + fimd_win_set_pixfmt(ctx, win, fb, state->src.w); /* hardware window 0 doesn't support color key. */ if (win != 0) @@ -988,6 +1018,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); ctx->configs[i].zpos = i; ctx->configs[i].type = fimd_win_types[i]; + ctx->configs[i].capabilities = capabilities[i]; ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, &ctx->configs[i]); if (ret) diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index d8fc96ed11e9..f070b7c0d2cf 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -211,6 +211,7 @@ #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) #define WINCON1_LOCALSEL_CAMIF (1 << 23) +#define WINCON1_ALPHA_MUL (1 << 7) #define WINCON1_BLD_PIX (1 << 6) #define WINCON1_BPPMODE_MASK (0xf << 2) #define WINCON1_BPPMODE_SHIFT 2 From patchwork Mon Oct 8 09:33:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Manszewski X-Patchwork-Id: 10632049 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6574714BD for ; Tue, 9 Oct 2018 07:34:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5344228AFD for ; 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Mon, 8 Oct 2018 09:33:30 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20181008093330eusmtrp13abe33998e17c0c36f03b41c63fd88f3~bmFoP9r6Y0079300793eusmtrp19; Mon, 8 Oct 2018 09:33:30 +0000 (GMT) X-AuditID: cbfec7f2-5e3ff70000001159-e9-5bbb246bbc83 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 3C.7B.04128.A642BBB5; Mon, 8 Oct 2018 10:33:30 +0100 (BST) Received: from AMDC2034.DIGITAL.local (unknown [106.120.51.41]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20181008093329eusmtip2fa7e2f887bf4a4694ec15f0c681c1c34~bmFnmYi5F0447404474eusmtip2S; Mon, 8 Oct 2018 09:33:29 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/exynos: fimd: Make pixel blend mode configurable Date: Mon, 8 Oct 2018 11:33:02 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538991182-12961-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSfSyUcRzv97y7dXoc8Zsa7UpLrcOm7TFSVrOnf25abVpadeXxEnfsHpS2 Rkw4RNjC9CKpc0KOyFshkZHXZpebl02a19lwlvWy7jzUf5/XfT/77UehEi3uSIWrYji1ShEp JURYfdfGwNGIA81B7oNlBDNW1Y8zWf09CFNTUI0z3c1lgPliWiaY3MkcjJmdGMKY7OkFlBkY eE0yn5MWSUY/PYozI03FBFMw8A5hKjvHSaYgb444uYvV69IJtmF9CmcnM7oRtvZ5Anu/TgfY Vb1TAHFR5BPMRYbHcWo336uisNTlJhA97XircnAdTwS19hpgRUHaE/5sTMI1QERJaC2AKXkT iEDWAKxa+EgIZBXAJzm9YLuS+W0EFYyXAK4bh9B/FW3+h80UQR+DxvEVwoLt6P3w9wMdsIRQ +g0GW3sMiMWwpc/AVm2R2aAojHaBd9tDhAtO8Gt/OmrBVuZIe4sWs3QhXUXCtaxG0mKI6Tio aVlChcJp+KNgBRGwLZzvriMFvBf25mVulZMBHFsbxQWSA2B7hQYTUt5Qb5hHLCtQ2hVWN7kJ sh+cKZzbHAdpa2hYsrHIqBnm1j9EBVkM0+5JhPRBuFBXR2yfnV01bb0WC0sqNjZnSuh0BFam KXKAc9H/W08B0AEHLpZXhnK8h4q7KeMVSj5WFSq7HqXUA/P/6f3TvfIWmIavdQCaAtKd4vKA piAJrojj45UdAFKo1E68u8EsiYMV8bc5ddQVdWwkx3eAPRQmdRC/eFwTJKFDFTFcBMdFc+pt F6GsHBPBZX8/TfHiq86zaaMJ5UOlHfJf5U4uvkGPzhn7LoT0fffaWO4afuYRaMouRG44e905 9UkeP20YgSltZPCUW+64zv+Etx83n+qS36vcly+XlXiy7g4zgRntrPP7wB3JBjE5cqTNRopP yPhL8kP9pfZhLkZ312Ufa4+x88niqcfHpRgfpvA4jKp5xV90khT3OwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkkeLIzCtJLcpLzFFi42I5/e/4Pd0sld3RBnOPclrcWneO1aL33Ekm i40z1rNaHN+9lNHiytf3bBaT7k9gsXhx7yKLRf/j18wW589vYLc42/SG3WLT42usFpd3zWGz mHF+H5PF2iN32S1mTH7J5sDvsWlVJ5vH9m8PWD3udx9n8ti8pN6jb8sqRo/Pm+QC2KL0bIry S0tSFTLyi0tslaINLYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLLUov07RL0Mtrf72IseCxV sfbCN9YGxs1iXYycHBICJhI9Ty4zg9hCAksZJXoPVUDEZSTmne1jg7CFJf5c6wKyuYBqPjFK rD49HSzBJmAqcfvuJzBbREBZ4u/EVYwgRcwCB1kkWjaeYQRJCAt4SuxdMQvI5uBgEVCVaDyY BhLmFfCQ+PlyEyPEAjmJm+c6wY7gBCo/uGcFC8SyrYwSc/Y2sk5g5FvAyLCKUSS1tDg3PbfY SK84Mbe4NC9dLzk/dxMjMBq2Hfu5ZQdj17vgQ4wCHIxKPLwrAnZFC7EmlhVX5h5ilOBgVhLh Fd0OFOJNSaysSi3Kjy8qzUktPsRoCnTURGYp0eR8YKTmlcQbmhqaW1gamhubG5tZKInznjeo jBISSE8sSc1OTS1ILYLpY+LglGpgZN++NuJNf3CigPDhvQJzXhU7hNjvF9uzzf198gq2lK0r FxvcvJqj42hfXvPh3s6+U6/2M6stfcDTsNhiq/28o5s+r2pgCcye+Uis6WOR5P3HDyvdxTfv Lf695qUQv/v0BIsZz2bI8qS/Knkup8vx9ufnwmSv5Wvk66euKiw4LrNBTWG9lshmFSWW4oxE Qy3mouJEANZcFEScAgAA Message-Id: <20181008093330eucas1p15363b8acc502292b24a6f6803073accc~bmFojGGtF2363023630eucas1p1_@eucas1p1.samsung.com> X-CMS-MailID: 20181008093330eucas1p15363b8acc502292b24a6f6803073accc X-Msg-Generator: CA X-RootMTR: 20181008093330eucas1p15363b8acc502292b24a6f6803073accc X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181008093330eucas1p15363b8acc502292b24a6f6803073accc References: <20181003094053eucas1p107c7a8a60c48dd68625fdaa223ef1996~aD9p3GwpI1866618666eucas1p1B@eucas1p1.samsung.com> <1538991182-12961-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Tue, 09 Oct 2018 07:34:35 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently blend mode is set accordingly to pixel format. Add pixel blend mode property and make that configurable. Fimd hardware doesn't support premultiplied mode, choose coverage as default. Tested on TRATS2 with Exynos 4412 CPU, on top of exynos-drm-next using modetest. Signed-off-by: Christoph Manszewski --- Similar to exynos5433_drm_decon, the driver exposes the "premultiplied" option for pixel blend mode property, although hardware doesn't support it, and it's hanlded by the driver as "coverage". Again, that's because the premultiplied mode is required and used as default. drivers/gpu/drm/exynos/exynos_drm_fimd.c | 28 ++++++++++++++++++++++------ include/video/samsung_fimd.h | 1 + 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 06d5d2422246..c4b0fb05a19b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -231,10 +231,10 @@ static const uint32_t fimd_formats[] = { static const unsigned int capabilities[WINDOWS_NR] = { 0, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, }; static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, @@ -576,6 +576,23 @@ static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, unsigned int alpha = state->base.alpha; u32 win_alpha = alpha >> 8; u32 val = 0; + unsigned int pixel_alpha; + + if (fb->format->has_alpha) + pixel_alpha = state->base.pixel_blend_mode; + else + pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; + + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + break; + case DRM_MODE_BLEND_COVERAGE: + default: + val |= WINCON1_ALPHA_SEL; + val |= WINCON1_BLD_PIX; + val |= WINCON1_ALPHA_MUL; + } + fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); /* OSD alpha */ val = VIDISD14C_ALPHA0_R(alpha >> 4) | @@ -639,7 +656,6 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; val |= WINCONx_WSWP; val |= WINCONx_BURSTLEN_16WORD; - val |= WINCON1_ALPHA_MUL; break; } @@ -656,7 +672,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, val |= WINCONx_BURSTLEN_4WORD; } - writel(val, ctx->regs + WINCON(win)); + fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); /* hardware window 0 doesn't support alpha channel. */ if (win != 0) diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index f070b7c0d2cf..bb1d5baa74d6 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -198,6 +198,7 @@ #define WINCONx_BURSTLEN_8WORD (0x1 << 9) #define WINCONx_BURSTLEN_4WORD (0x2 << 9) #define WINCONx_ENWIN (1 << 0) +#define WINCONx_BLEND_MODE_MASK (0xc2) #define WINCON0_BPPMODE_MASK (0xf << 2) #define WINCON0_BPPMODE_SHIFT 2