From patchwork Thu May 7 21:34:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11534951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93012139A for ; Thu, 7 May 2020 21:35:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6850821582 for ; Thu, 7 May 2020 21:35:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="e5y1nTJu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726948AbgEGVfb (ORCPT ); Thu, 7 May 2020 17:35:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726924AbgEGVf2 (ORCPT ); Thu, 7 May 2020 17:35:28 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65576C05BD0B for ; Thu, 7 May 2020 14:35:28 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id t40so3219674pjb.3 for ; Thu, 07 May 2020 14:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LNGO2aJpJ/k7WS6fZ43tNwyLQEHpwINjX6rCyLagYJg=; b=e5y1nTJuz9KyZAX++ny87kAS4+zpmhWHHmRpEAlvii3XsDxYRax21hzdX/FHDZCuEW MNxDL1UlrgVGba4huvYy398i3gZC7JbZWeGSqZyDeJq1YQhXL0l+XoRBfw4G3/x1sFre 25n3udhOaqw92npu9yFmVEbhVsXs8p6vH8Qms= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LNGO2aJpJ/k7WS6fZ43tNwyLQEHpwINjX6rCyLagYJg=; b=CgJrWI+5nOOn/p/gumU19SpWiHrw9OhGoImqlG63FRb3wno/plI/xZEdSgliq/27dE mzePADVXK8WaPU4DZ1Titg36ua1Yy4ju6K/pP7endu3dmeLbvXTDbi6keb3x+9LBHPxZ mmS6Khe6k2JzE8uLqjE8yB+pzwxM7pBVrs5860jbgWbrJpBfodS9MjwZYi2rNWDivcEF j++5R+ZcfiWlrRZQCaibTaulgMwfND2cRBK3VNICM/tymyeOys6vWJCnhSu0t56QgcYp YUC/2LG6m9lakcRnuLZbc4qtISkEBUbQ5+VImB5pprOoHB1npqkX206310rwjXuQexBv TAkw== X-Gm-Message-State: AGi0PubyS8KU1KSaUDFdfxTKXYulALc7cZXtBPCWOHHHWA5E3BAXE8qo /s3yQ5T7ZivSwHeU5atSMgDIwQ== X-Google-Smtp-Source: APiQypLU3f+NNIXHOyV7Z7a20GXQ9/HormM6jzwth+JcryEB6FOeECEBaWEwsldOpEXYjotwnzZRDA== X-Received: by 2002:a17:902:a513:: with SMTP id s19mr15709090plq.84.1588887327758; Thu, 07 May 2020 14:35:27 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id i10sm5884860pfa.166.2020.05.07.14.35.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 14:35:27 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, bjorn.andersson@linaro.org, swboyd@chromium.org, jernej.skrabec@siol.net, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, robdclark@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v5 1/6] drm/bridge: ti-sn65dsi86: Export bridge GPIOs to Linux Date: Thu, 7 May 2020 14:34:55 -0700 Message-Id: <20200507143354.v5.1.Ia50267a5549392af8b37e67092ca653a59c95886@changeid> X-Mailer: git-send-email 2.26.2.645.ge9eca65c58-goog In-Reply-To: <20200507213500.241695-1-dianders@chromium.org> References: <20200507213500.241695-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The ti-sn65dsi86 MIPI DSI to eDP bridge chip has 4 pins on it that can be used as GPIOs in a system. Each pin can be configured as input, output, or a special function for the bridge chip. These are: - GPIO1: SUSPEND Input - GPIO2: DSIA VSYNC - GPIO3: DSIA HSYNC or VSYNC - GPIO4: PWM Let's expose these pins as GPIOs. A few notes: - Access to ti-sn65dsi86 is via i2c so we set "can_sleep". - These pins can't be configured for IRQ. - There are no programmable pulls or other fancy features. - Keeping the bridge chip powered might be expensive. The driver is setup such that if all used GPIOs are only inputs we'll power the bridge chip on just long enough to read the GPIO and then power it off again. Setting a GPIO as output will keep the bridge powered. - If someone releases a GPIO we'll implicitly switch it to an input so we no longer need to keep the bridge powered for it. Because of all of the above limitations we just need to implement a bare-bones GPIO driver. The device tree bindings already account for this device being a GPIO controller so we only need the driver changes for it. NOTE: Despite the fact that these pins are nominally muxable I don't believe it makes sense to expose them through the pinctrl interface as well as the GPIO interface. The special functions are things that the bridge chip driver itself would care about and it can just configure the pins as needed. Signed-off-by: Douglas Anderson Cc: Linus Walleij Cc: Bartosz Golaszewski Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Reviewed-by: Linus Walleij --- Removed Stephen's review tag in v5 to confirm he's good with the way I implemented of_xlate. Changes in v5: - Use of_xlate so that numbers in dts start at 1, not 0. Changes in v4: - Don't include gpio.h - Use gpiochip_get_data() instead of container_of() to get data. - GPIOF_DIR_XXX => GPIO_LINE_DIRECTION_XXX - Use Linus W's favorite syntax to read a bit from a bitfield. - Define and use SN_GPIO_MUX_MASK. - Add a comment about why we use a bitmap for gchip_output. Changes in v3: - Becaue => Because - Add a kernel-doc to our pdata to clarify double-duty of gchip_output. - More comments about how powering off affects us (get_dir, dir_input). - Cleanup tail of ti_sn_setup_gpio_controller() to avoid one "return". - Use a bitmap rather than rolling my own. Changes in v2: - ("Export...GPIOs") is 1/2 of replacement for ("Allow...bridge GPIOs") drivers/gpu/drm/bridge/ti-sn65dsi86.c | 214 ++++++++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 6ad688b320ae..4e8df948b3b8 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -4,9 +4,11 @@ * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf */ +#include #include #include #include +#include #include #include #include @@ -54,6 +56,14 @@ #define BPP_18_RGB BIT(0) #define SN_HPD_DISABLE_REG 0x5C #define HPD_DISABLE BIT(0) +#define SN_GPIO_IO_REG 0x5E +#define SN_GPIO_INPUT_SHIFT 4 +#define SN_GPIO_OUTPUT_SHIFT 0 +#define SN_GPIO_CTRL_REG 0x5F +#define SN_GPIO_MUX_INPUT 0 +#define SN_GPIO_MUX_OUTPUT 1 +#define SN_GPIO_MUX_SPECIAL 2 +#define SN_GPIO_MUX_MASK 0x3 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) #define SN_AUX_ADDR_19_16_REG 0x74 #define SN_AUX_ADDR_15_8_REG 0x75 @@ -88,6 +98,35 @@ #define SN_REGULATOR_SUPPLY_NUM 4 +#define SN_NUM_GPIOS 4 +#define SN_GPIO_PHYSICAL_OFFSET 1 + +/** + * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver. + * @dev: Pointer to our device. + * @regmap: Regmap for accessing i2c. + * @aux: Our aux channel. + * @bridge: Our bridge. + * @connector: Our connector. + * @debugfs: Used for managing our debugfs. + * @host_node: Remote DSI node. + * @dsi: Our MIPI DSI source. + * @refclk: Our reference clock. + * @panel: Our panel. + * @enable_gpio: The GPIO we toggle to enable the bridge. + * @supplies: Data for bulk enabling/disabling our regulators. + * @dp_lanes: Count of dp_lanes we're using. + * + * @gchip: If we expose our GPIOs, this is used. + * @gchip_output: A cache of whether we've set GPIOs to output. This + * serves double-duty of keeping track of the direction and + * also keeping track of whether we've incremented the + * pm_runtime reference count for this pin, which we do + * whenever a pin is configured as an output. This is a + * bitmap so we can do atomic ops on it without an extra + * lock so concurrent users of our 4 GPIOs don't stomp on + * each other's read-modify-write. + */ struct ti_sn_bridge { struct device *dev; struct regmap *regmap; @@ -102,6 +141,9 @@ struct ti_sn_bridge { struct gpio_desc *enable_gpio; struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; int dp_lanes; + + struct gpio_chip gchip; + DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); }; static const struct regmap_range ti_sn_bridge_volatile_ranges[] = { @@ -874,6 +916,172 @@ static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata) return 0; } +static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) + return -EINVAL; + + if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[1]; + + return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; +} + +static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct ti_sn_bridge *pdata = gpiochip_get_data(chip); + + /* + * We already have to keep track of the direction because we use + * that to figure out whether we've powered the device. We can + * just return that rather than (maybe) powering up the device + * to ask its direction. + */ + return test_bit(offset, pdata->gchip_output) ? + GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + +static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ti_sn_bridge *pdata = gpiochip_get_data(chip); + unsigned int val; + int ret; + + /* + * When the pin is an input we don't forcibly keep the bridge + * powered--we just power it on to read the pin. NOTE: part of + * the reason this works is that the bridge defaults (when + * powered back on) to all 4 GPIOs being configured as GPIO input. + * Also note that if something else is keeping the chip powered the + * pm_runtime functions are lightweight increments of a refcount. + */ + pm_runtime_get_sync(pdata->dev); + ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); + pm_runtime_put(pdata->dev); + + if (ret) + return ret; + + return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); +} + +static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, + int val) +{ + struct ti_sn_bridge *pdata = gpiochip_get_data(chip); + int ret; + + if (!test_bit(offset, pdata->gchip_output)) { + dev_err(pdata->dev, "Ignoring GPIO set while input\n"); + return; + } + + val &= 1; + ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, + BIT(SN_GPIO_OUTPUT_SHIFT + offset), + val << (SN_GPIO_OUTPUT_SHIFT + offset)); +} + +static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct ti_sn_bridge *pdata = gpiochip_get_data(chip); + int shift = offset * 2; + int ret; + + if (!test_and_clear_bit(offset, pdata->gchip_output)) + return 0; + + ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, + SN_GPIO_MUX_MASK << shift, + SN_GPIO_MUX_INPUT << shift); + if (ret) { + set_bit(offset, pdata->gchip_output); + return ret; + } + + /* + * NOTE: if nobody else is powering the device this may fully power + * it off and when it comes back it will have lost all state, but + * that's OK because the default is input and we're now an input. + */ + pm_runtime_put(pdata->dev); + + return 0; +} + +static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + struct ti_sn_bridge *pdata = gpiochip_get_data(chip); + int shift = offset * 2; + int ret; + + if (test_and_set_bit(offset, pdata->gchip_output)) + return 0; + + pm_runtime_get_sync(pdata->dev); + + /* Set value first to avoid glitching */ + ti_sn_bridge_gpio_set(chip, offset, val); + + /* Set direction */ + ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, + SN_GPIO_MUX_MASK << shift, + SN_GPIO_MUX_OUTPUT << shift); + if (ret) { + clear_bit(offset, pdata->gchip_output); + pm_runtime_put(pdata->dev); + } + + return ret; +} + +static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + /* We won't keep pm_runtime if we're input, so switch there on free */ + ti_sn_bridge_gpio_direction_input(chip, offset); +} + +static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { + "GPIO1", "GPIO2", "GPIO3", "GPIO4" +}; + +static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata) +{ + int ret; + + /* Only init if someone is going to use us as a GPIO controller */ + if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) + return 0; + + pdata->gchip.label = dev_name(pdata->dev); + pdata->gchip.parent = pdata->dev; + pdata->gchip.owner = THIS_MODULE; + pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; + pdata->gchip.of_gpio_n_cells = 2; + pdata->gchip.free = ti_sn_bridge_gpio_free; + pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; + pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; + pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; + pdata->gchip.get = ti_sn_bridge_gpio_get; + pdata->gchip.set = ti_sn_bridge_gpio_set; + pdata->gchip.can_sleep = true; + pdata->gchip.names = ti_sn_bridge_gpio_names; + pdata->gchip.ngpio = SN_NUM_GPIOS; + ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata); + if (ret) + dev_err(pdata->dev, "can't add gpio chip\n"); + + return ret; +} + static int ti_sn_bridge_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -937,6 +1145,12 @@ static int ti_sn_bridge_probe(struct i2c_client *client, pm_runtime_enable(pdata->dev); + ret = ti_sn_setup_gpio_controller(pdata); + if (ret) { + pm_runtime_disable(pdata->dev); + return ret; + } + i2c_set_clientdata(client, pdata); pdata->aux.name = "ti-sn65dsi86-aux"; From patchwork Thu May 7 21:34:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11534953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8CF00139A for ; Thu, 7 May 2020 21:35:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72C4A20CC7 for ; Thu, 7 May 2020 21:35:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="JEPOGcmw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727071AbgEGVf6 (ORCPT ); Thu, 7 May 2020 17:35:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726937AbgEGVfa (ORCPT ); Thu, 7 May 2020 17:35:30 -0400 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF5ADC05BD0C for ; Thu, 7 May 2020 14:35:29 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id r4so3392955pgg.4 for ; Thu, 07 May 2020 14:35:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XfNEDCRiXjCC8oOylpb9JNhfA9+c9hrQufk7O01EutI=; b=JEPOGcmwFBfW5QCKms1+maouE+hSH796fyxNeSs6NafNDFXUhutuNYMqtyu+Cz4ftE smDDleCiYarIBTBNcvs9qhyaX4KxL7re6xdgs706c6CBvnOPokM8Q5Hjxqfd+u70iMzN L4Nfj73BfoYxzl3kVdWZnth1x62n3HdcVf5uo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XfNEDCRiXjCC8oOylpb9JNhfA9+c9hrQufk7O01EutI=; b=fo+lYahnQv4OhAXIcyxd4lhi/InI8oPa1GWuU7dFMXeXXr8TEJz6k9okRysBSAkPYf 2PyKAjv6qUgW429zI0SpIi/JuKHrjQSIBzDQsFcKr+PR/KgVlZZlKermYXUf9ohNAYu6 qLvc578BQKv+nVfYj3Q4tYJf/y2qSXV2IJORstVkpySFlwWsHvbP8/7JR+nn+VNLgU+p NXSxRu3NUbkCa3SLWQMj3NL+G5aSahXy4LO9U1JXmieBibAu5sWyc7GCkWTAdviN49yp KoFVdXTl/z2iKbrjiyoftJCRMxrvQClxaYDIGCq33RCv/3enxrinJEnEYDlf90x5RUQy vtfA== X-Gm-Message-State: AGi0PuYtdpy7pkQMtDQk3U7DoQNfgj7NmunnD2GBEuG58Fc/ltAstGSm TNQCoDlSqRSinyyxrWggvKHiJA== X-Google-Smtp-Source: APiQypIN4LGb4WwjVAsqDkdk6/Lm8XZyQnvUfoNsrt2XHG4HD0F4xJ4m0Ae8nle3ctmT2+GxbHwNUA== X-Received: by 2002:a63:741e:: with SMTP id p30mr13075429pgc.433.1588887329409; Thu, 07 May 2020 14:35:29 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id i10sm5884860pfa.166.2020.05.07.14.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 14:35:28 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, bjorn.andersson@linaro.org, swboyd@chromium.org, jernej.skrabec@siol.net, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, robdclark@chromium.org, Douglas Anderson , Laurent Pinchart , Sam Ravnborg , Thierry Reding , linux-kernel@vger.kernel.org Subject: [PATCH v5 2/6] dt-bindings: display: Add hpd-gpios to panel-common bindings Date: Thu, 7 May 2020 14:34:56 -0700 Message-Id: <20200507143354.v5.2.I1976736b400a3b30e46efa47782248b86b3bc627@changeid> X-Mailer: git-send-email 2.26.2.645.ge9eca65c58-goog In-Reply-To: <20200507213500.241695-1-dianders@chromium.org> References: <20200507213500.241695-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In the cases where there is no connector in a system there's no great place to put "hpd-gpios". As per discussion [1] the best place to put it is in the panel. Add this to the device tree bindings. [1] https://lore.kernel.org/r/20200417180819.GE5861@pendragon.ideasonboard.com Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Linus Walleij Reviewed-by: Laurent Pinchart --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - ("dt-bindings: display: Add hpd-gpios to panel-common...") new for v2 .../devicetree/bindings/display/panel/panel-common.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-common.yaml b/Documentation/devicetree/bindings/display/panel/panel-common.yaml index ed051ba12084..e9a04a3a4f5f 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-common.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-common.yaml @@ -96,6 +96,12 @@ properties: (hot plug detect) signal, but the signal isn't hooked up so we should hardcode the max delay from the panel spec when powering up the panel. + hpd-gpios: + maxItems: 1 + description: + If Hot Plug Detect (HPD) is connected to a GPIO in the system rather + than a dedicated HPD pin the pin can be specified here. + # Control I/Os # Many display panels can be controlled through pins driven by GPIOs. The nature From patchwork Thu May 7 21:34:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11534949 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2EA1914B4 for ; Thu, 7 May 2020 21:35:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1403020CC7 for ; Thu, 7 May 2020 21:35:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="UxYcP2Wv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727770AbgEGVfn (ORCPT ); Thu, 7 May 2020 17:35:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727100AbgEGVfd (ORCPT ); Thu, 7 May 2020 17:35:33 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26EBAC05BD43 for ; Thu, 7 May 2020 14:35:32 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id y25so3647676pfn.5 for ; Thu, 07 May 2020 14:35:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N1E8hpQtZ5Dwx/KP93WpgOlFW3tR/zc7YU1QsvmgG9E=; b=UxYcP2WvfAqPASGNjeeemSarAPyqIB5ndoLfcsfFgS9gQOwJrFk2aKOh1KzGZYYy82 MVqQM2Z9Eu6nEAMRz38aA8GtbyhtKb1LBugXREv71ZH7Kuhn4AiB/nQodsQk699Pd4iK LBd1QBUUbblSZzVCQcLBA0Dui7ESeYRg5Gc9Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N1E8hpQtZ5Dwx/KP93WpgOlFW3tR/zc7YU1QsvmgG9E=; b=LZnqTN1lF+fQEUcYZpvICzgwD4f1bMqutTac51fKgxDq9Haua3vfTHqS9ruYXOC1we o5ayerSLCeAAX0TUZ3CxOdDIX8FpD/yxjz+W/CeHiZlroHR3ntj950iWKbPGzWDk9sRw nyH4oLwKQzkQkzywwhsIbRqRxbKbJhxfENMXc99FAZKA4dkOg5CyvuRghCR9hrrGJtFT ie1bCcz5q6KQtKNi+A4aoxLuMpRKTVmxwdk6vEHZKZIZdyfVHMZjt5WntYss/nxE3nV2 IYSayk7yI8CJ28wKAXsgMWklNOv+WxO6D8Lu2nMfWJtc1gE5YrOlGrzQ4rEBqcZq8Qcz NvOA== X-Gm-Message-State: AGi0PubY1CVAW3I0bgZA9YZF3QFmSCKF2Y5VN02jfpy/Xp6xUJmpjP5I V/Jav7uqAcQpK+VwM3OVlIv1HQ== X-Google-Smtp-Source: APiQypJf8281mnDUYU9yJA5Uh+czWYF/8KtOZ4222MJHsTw/dKf4hUC4S7EBQIFd2vuunMvdXj/GFA== X-Received: by 2002:a63:f960:: with SMTP id q32mr12548727pgk.357.1588887330910; Thu, 07 May 2020 14:35:30 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id i10sm5884860pfa.166.2020.05.07.14.35.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 14:35:30 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, bjorn.andersson@linaro.org, swboyd@chromium.org, jernej.skrabec@siol.net, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, robdclark@chromium.org, Douglas Anderson , Sam Ravnborg , Thierry Reding , linux-kernel@vger.kernel.org Subject: [PATCH v5 3/6] drm/panel-simple: Support hpd-gpios for delaying prepare() Date: Thu, 7 May 2020 14:34:57 -0700 Message-Id: <20200507143354.v5.3.I53fed5b501a31e7a7fa13268ebcdd6b77bd0cadd@changeid> X-Mailer: git-send-email 2.26.2.645.ge9eca65c58-goog In-Reply-To: <20200507213500.241695-1-dianders@chromium.org> References: <20200507213500.241695-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org People use panel-simple when they have panels that are builtin to their device. In these cases the HPD (Hot Plug Detect) signal isn't really used for hotplugging devices but instead is used for power sequencing. Panel timing diagrams (especially for eDP panels) usually have the HPD signal in them and it acts as an indicator that the panel is ready for us to talk to it. Sometimes the HPD signal is hooked up to a normal GPIO on a system. In this case we need to poll it in the correct place to know that the panel is ready for us. In some system designs the right place for this is panel-simple. When adding this support, we'll account for the case that there might be a circular dependency between panel-simple and the provider of the GPIO. The case this was designed for was for the "ti-sn65dsi86" bridge chip. If HPD is hooked up to one of the GPIOs provided by the bridge chip then in our probe function we'll always get back -EPROBE_DEFER. Let's handle this by allowing this GPIO to show up late if we saw -EPROBE_DEFER during probe. NOTE: since the gpio_get_optional() is used, if the "hpd-gpios" isn't there our variable will just be NULL and we won't do anything in prepare(). Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Linus Walleij --- Changes in v5: None Changes in v4: None Changes in v3: - Remind how gpio_get_optional() works in the commit message. Changes in v2: - ("simple...hpd-gpios") is 1/2 of replacement for ("Allow...bridge GPIOs") drivers/gpu/drm/panel/panel-simple.c | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 3ad828eaefe1..f816e2aa29cd 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -108,6 +109,7 @@ struct panel_simple { struct i2c_adapter *ddc; struct gpio_desc *enable_gpio; + struct gpio_desc *hpd_gpio; struct drm_display_mode override_mode; }; @@ -259,11 +261,37 @@ static int panel_simple_unprepare(struct drm_panel *panel) return 0; } +static int panel_simple_get_hpd_gpio(struct device *dev, + struct panel_simple *p, bool from_probe) +{ + int err; + + p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); + if (IS_ERR(p->hpd_gpio)) { + err = PTR_ERR(p->hpd_gpio); + + /* + * If we're called from probe we won't consider '-EPROBE_DEFER' + * to be an error--we'll leave the error code in "hpd_gpio". + * When we try to use it we'll try again. This allows for + * circular dependencies where the component providing the + * hpd gpio needs the panel to init before probing. + */ + if (err != -EPROBE_DEFER || !from_probe) { + dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); + return err; + } + } + + return 0; +} + static int panel_simple_prepare(struct drm_panel *panel) { struct panel_simple *p = to_panel_simple(panel); unsigned int delay; int err; + int hpd_asserted; if (p->prepared) return 0; @@ -282,6 +310,26 @@ static int panel_simple_prepare(struct drm_panel *panel) if (delay) msleep(delay); + if (p->hpd_gpio) { + if (IS_ERR(p->hpd_gpio)) { + err = panel_simple_get_hpd_gpio(panel->dev, p, false); + if (err) + return err; + } + + err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, + hpd_asserted, hpd_asserted, + 1000, 2000000); + if (hpd_asserted < 0) + err = hpd_asserted; + + if (err) { + dev_err(panel->dev, + "error waiting for hpd GPIO: %d\n", err); + return err; + } + } + p->prepared = true; return 0; @@ -462,6 +510,11 @@ static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) panel->desc = desc; panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); + if (!panel->no_hpd) { + err = panel_simple_get_hpd_gpio(dev, panel, true); + if (err) + return err; + } panel->supply = devm_regulator_get(dev, "power"); if (IS_ERR(panel->supply)) From patchwork Thu May 7 21:34:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11534947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C500B81 for ; Thu, 7 May 2020 21:35:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A48C021473 for ; Thu, 7 May 2020 21:35:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jQ5jz7WS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727093AbgEGVfn (ORCPT ); Thu, 7 May 2020 17:35:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727096AbgEGVfd (ORCPT ); Thu, 7 May 2020 17:35:33 -0400 Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ECBCC05BD0C for ; Thu, 7 May 2020 14:35:33 -0700 (PDT) Received: by mail-pl1-x644.google.com with SMTP id m7so2607463plt.5 for ; Thu, 07 May 2020 14:35:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=encY90NiNO11WT8mT4z8+mXIuxdJxEWEMzs6bjYU5OE=; b=jQ5jz7WSEpKXanr+wx3z4ZJvRvEa0aKF+moVkUC3FD3BRTc1YqZRANavJNfYHYNHtw RzmqGVMP8ov/wHKSG2CuxLQthJnXiyKkeNhWh/O5sRDi1CRvkDOwlhuuOIEA4zf5xaV9 FInuFBsWyr1JpyRVGNtps4sZpHC/x+zp04OuA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=encY90NiNO11WT8mT4z8+mXIuxdJxEWEMzs6bjYU5OE=; b=gDNZC9IFKJJ35M5Y+7IKeorYh3foNG5ErowrmXdfW1vJbMuHsc5HwJEXaV/rQ6I738 V+TlONqXinlTmHA/qb8jeB9VeI0wZmDOze413XYYACuHk/fbjCKZkn2xquKcOC/ImrTc HyZKTShqNWhJud5Yu/GXXiYEr4tTglirpnSJpH9BnW3kREq6ojFqHgpYZgbAb0HJyjzJ nasrIG9mPbjQ+a+Z72hnAiFSvgs8hfMOOeewq2K1+4hZfje9lieHq+RNXarzEaputiGj rmHaTE3tgQy/WPPpBE0qzzNBc0Y5NQylOkpB4eZ1Cc76/61Z/odBqE1lB7sGnvqRhcqD LIsg== X-Gm-Message-State: AGi0PubMLIgQ5qoWmNNpioANdmH669ED+jHGtwZBvthiwH563MmdY5qh rFTvHBOVaB7YshzdZj9gV3rk9Q== X-Google-Smtp-Source: APiQypJRtQOIhiiSMjhSb2lZaC2A5c4fKxXF5z99f5EkQUAnhfpbx+8gmLySLSt75wloe7Xyg6Y8hA== X-Received: by 2002:a17:90a:e38c:: with SMTP id b12mr2466958pjz.102.1588887332487; Thu, 07 May 2020 14:35:32 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id i10sm5884860pfa.166.2020.05.07.14.35.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 14:35:32 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, bjorn.andersson@linaro.org, swboyd@chromium.org, jernej.skrabec@siol.net, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, robdclark@chromium.org, Douglas Anderson , Krzysztof Kozlowski , Laurent Pinchart , Paul Walmsley , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v5 4/6] dt-bindings: drm/bridge: ti-sn65dsi86: Convert to yaml Date: Thu, 7 May 2020 14:34:58 -0700 Message-Id: <20200507143354.v5.4.Ifcdc4ecb12742a27862744ee1e8753cb95a38a7f@changeid> X-Mailer: git-send-email 2.26.2.645.ge9eca65c58-goog In-Reply-To: <20200507213500.241695-1-dianders@chromium.org> References: <20200507213500.241695-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This moves the bindings over, based a lot on toshiba,tc358768.yaml. Unless there's someone known to be better, I've set the maintainer in the yaml as the first person to submit bindings. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd --- I removed Stephen's review tag on v5 since I squashed in a bunch of other stuff. Changes in v5: - Squash https://lore.kernel.org/r/20200506140208.v2.2.I0a2bca02b09c1fcb6b09479b489736d600b3e57f@changeid/ Changes in v4: None Changes in v3: None Changes in v2: - specification => specifier. - power up => power. - Added back missing suspend-gpios. - data-lanes and lane-polarities are are the right place now. - endpoints don't need to be patternProperties. - Specified more details for data-lanes and lane-polarities. - Added old example back in, fixing bugs in it. - Example i2c bus is just called "i2c", not "i2c1" now. .../bindings/display/bridge/ti,sn65dsi86.txt | 87 ------ .../bindings/display/bridge/ti,sn65dsi86.yaml | 285 ++++++++++++++++++ 2 files changed, 285 insertions(+), 87 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt deleted file mode 100644 index 8ec4a7f2623a..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt +++ /dev/null @@ -1,87 +0,0 @@ -SN65DSI86 DSI to eDP bridge chip --------------------------------- - -This is the binding for Texas Instruments SN65DSI86 bridge. -http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf - -Required properties: -- compatible: Must be "ti,sn65dsi86" -- reg: i2c address of the chip, 0x2d as per datasheet -- enable-gpios: gpio specification for bridge_en pin (active high) - -- vccio-supply: A 1.8V supply that powers up the digital IOs. -- vpll-supply: A 1.8V supply that powers up the displayport PLL. -- vcca-supply: A 1.2V supply that powers up the analog circuits. -- vcc-supply: A 1.2V supply that powers up the digital core. - -Optional properties: -- interrupts-extended: Specifier for the SN65DSI86 interrupt line. - -- gpio-controller: Marks the device has a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../../gpio/gpio.txt for more information. -- #pwm-cells : Should be one. See ../../pwm/pwm.yaml for description of - the cell formats. - -- clock-names: should be "refclk" -- clocks: Specification for input reference clock. The reference - clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. - -- data-lanes: See ../../media/video-interface.txt -- lane-polarities: See ../../media/video-interface.txt - -- suspend-gpios: specification for GPIO1 pin on bridge (active low) - -Required nodes: -This device has two video ports. Their connections are modelled using the -OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for DSI input -- Video port 1 for eDP output - -Example -------- - -edp-bridge@2d { - compatible = "ti,sn65dsi86"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2d>; - - enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; - suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>; - - interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; - - vccio-supply = <&pm8916_l17>; - vcca-supply = <&pm8916_l6>; - vpll-supply = <&pm8916_l17>; - vcc-supply = <&pm8916_l6>; - - clock-names = "refclk"; - clocks = <&input_refclk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - edp_bridge_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - port@1 { - reg = <1>; - - edp_bridge_out: endpoint { - data-lanes = <2 1 3 0>; - lane-polarities = <0 1 0 1>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; -} diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml new file mode 100644 index 000000000000..07d26121afca --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -0,0 +1,285 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SN65DSI86 DSI to eDP bridge chip + +maintainers: + - Sandeep Panda + +description: | + The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP. + http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf + +properties: + compatible: + const: ti,sn65dsi86 + + reg: + const: 0x2d + + enable-gpios: + maxItems: 1 + description: GPIO specifier for bridge_en pin (active high). + + suspend-gpios: + maxItems: 1 + description: GPIO specifier for GPIO1 pin on bridge (active low). + + vccio-supply: + description: A 1.8V supply that powers the digital IOs. + + vpll-supply: + description: A 1.8V supply that powers the DisplayPort PLL. + + vcca-supply: + description: A 1.2V supply that powers the analog circuits. + + vcc-supply: + description: A 1.2V supply that powers the digital core. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Clock specifier for input reference clock. The reference clock rate must + be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. + + clock-names: + const: refclk + + gpio-controller: true + '#gpio-cells': + const: 2 + description: + First cell is pin number, second cell is flags. GPIO pin numbers are + 1-based to match the datasheet. See ../../gpio/gpio.txt for more + information. + + '#pwm-cells': + const: 1 + description: See ../../pwm/pwm.yaml for description of the cell formats. + + ports: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + additionalProperties: false + + description: + Video port for MIPI DSI input + + properties: + reg: + const: 0 + + endpoint: + type: object + additionalProperties: false + properties: + remote-endpoint: true + + required: + - reg + + port@1: + type: object + additionalProperties: false + + description: + Video port for eDP output (panel or connector). + + properties: + reg: + const: 1 + + endpoint: + type: object + additionalProperties: false + + properties: + remote-endpoint: true + + data-lanes: + oneOf: + - minItems: 1 + maxItems: 1 + uniqueItems: true + items: + enum: + - 0 + - 1 + description: + If you have 1 logical lane the bridge supports routing + to either port 0 or port 1. Port 0 is suggested. + See ../../media/video-interface.txt for details. + + - minItems: 2 + maxItems: 2 + uniqueItems: true + items: + enum: + - 0 + - 1 + description: + If you have 2 logical lanes the bridge supports + reordering but only on physical ports 0 and 1. + See ../../media/video-interface.txt for details. + + - minItems: 4 + maxItems: 4 + uniqueItems: true + items: + enum: + - 0 + - 1 + - 2 + - 3 + description: + If you have 4 logical lanes the bridge supports + reordering in any way. + See ../../media/video-interface.txt for details. + + lane-polarities: + minItems: 1 + maxItems: 4 + items: + enum: + - 0 + - 1 + description: See ../../media/video-interface.txt + + dependencies: + lane-polarities: [data-lanes] + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - vccio-supply + - vpll-supply + - vcca-supply + - vcc-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + + interrupt-parent = <&tlmm>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&src_pp1800_s4a>; + vccio-supply = <&src_pp1800_s4a>; + vcca-supply = <&src_pp1200_l2a>; + vcc-supply = <&src_pp1200_l2a>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; + }; + - | + #include + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + + enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; + suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>; + + interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; + + vccio-supply = <&pm8916_l17>; + vcca-supply = <&pm8916_l6>; + vpll-supply = <&pm8916_l17>; + vcc-supply = <&pm8916_l6>; + + clock-names = "refclk"; + clocks = <&input_refclk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + data-lanes = <2 1 3 0>; + lane-polarities = <0 1 0 1>; + remote-endpoint = <&edp_panel_in>; + }; + }; + }; + }; + }; From patchwork Thu May 7 21:34:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11534943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0934114B4 for ; Thu, 7 May 2020 21:35:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E676121473 for ; Thu, 7 May 2020 21:35:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="ENdo3wyF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727099AbgEGVfn (ORCPT ); Thu, 7 May 2020 17:35:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727029AbgEGVff (ORCPT ); Thu, 7 May 2020 17:35:35 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54C14C05BD11 for ; Thu, 7 May 2020 14:35:34 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id 7so4291863pjo.0 for ; Thu, 07 May 2020 14:35:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fbjU22n436fNS4tm9Z/DQEhrNON6zU3/PI+8bjMf9/o=; b=ENdo3wyFIDnDOOps1rk+zv5ProXXQ+9MQz5G/1HA4jSM5UDNXkl9+hmeBnvG9M3leO NSh4AFWRaMg3Lf/9zJc93B0KoxcSPKM5Ml1/hYEPKQFxomyzrN2OmnKaWC1HQe39/uQm EOhKMqjbzPhv07nF6b2So6ZrxNKoRCqeCCMpU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbjU22n436fNS4tm9Z/DQEhrNON6zU3/PI+8bjMf9/o=; b=GZa4/l30k78IMxYdyneo2PO24GDOdzVQrhcr6Dnqic1g/qYSJOYT+wGddcmSw0vjYc 2SOaRiMESTTpvmMILBi038PpazX5z9vxDpNCiS31eL/qYb4cCpzFgc5BzwukOBygV/Cc qChOYlckeoy47ZHfoIWwjBquoeYd2N5E0krFYQ3dyfTI1ckIRuHQpFXBq+cwZ3rlRQAa o43lBSPWT2rCj+EVWD+EqUgJNs/enW44yJLpxUnnrjp6qbUO+/6N7WbzGdZlC2Kh4Ba+ jbFwi6G9uzapqJAcnEpIV2Adb/H5g8TgD/EdEa/U++o+pYsFKPvsAMufpr5ma2vXzu8E thYw== X-Gm-Message-State: AGi0PuaZnwNnR4h7+hQuz9UfkHkEbohsw9OJyvMD6zlzTINf+VI6inp4 Bhb6+ZWu4rrEMPgftWvBDcZQ5A== X-Google-Smtp-Source: APiQypJBBpiB37bVUcSXNEkVSPOGBlPdXdGwMwr4Q977C7AhF9IZS/u97Q/SlXzZLRIaBaM4TgLqgA== X-Received: by 2002:a17:90a:2ac2:: with SMTP id i2mr2277713pjg.91.1588887333807; Thu, 07 May 2020 14:35:33 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id i10sm5884860pfa.166.2020.05.07.14.35.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 14:35:33 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, bjorn.andersson@linaro.org, swboyd@chromium.org, jernej.skrabec@siol.net, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, robdclark@chromium.org, Douglas Anderson , Laurent Pinchart , linux-kernel@vger.kernel.org Subject: [PATCH v5 5/6] dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd Date: Thu, 7 May 2020 14:34:59 -0700 Message-Id: <20200507143354.v5.5.I72892d485088e57378a4748c86bc0f6c2494d807@changeid> X-Mailer: git-send-email 2.26.2.645.ge9eca65c58-goog In-Reply-To: <20200507213500.241695-1-dianders@chromium.org> References: <20200507213500.241695-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The ti-sn65dsi86 MIPI DSI to eDP bridge chip has a dedicated hardware HPD (Hot Plug Detect) pin on it, but it's mostly useless for eDP because of excessive debouncing in hardware. Specifically there is no way to disable the debouncing and for eDP debouncing hurts you because HPD is just used for knowing when the panel is ready, not for detecting physical plug events. Currently the driver in Linux just assumes that nobody has HPD hooked up. It relies on folks setting the "no-hpd" property in the panel node to specify that HPD isn't hooked up and then the panel driver using this to add some worst case delays when turning on the panel. Apparently it's also useful to specify "no-hpd" in the bridge node so that the bridge driver can make sure it's doing the right thing without peeking into the panel [1]. This would be used if anyone ever found it useful to implement support for the HW HPD pin on the bridge. Let's add this property to the bindings. NOTES: - This is somewhat of a backward-incompatible change. All current known users of ti-sn65dsi86 didn't have "no-hpd" specified in the bridge node yet none of them had HPD hooked up. This worked because the current Linux driver just assumed that HPD was never hooked up. We could make it less incompatible by saying that for this bridge it's assumed HPD isn't hooked up _unless_ a property is defined, but "no-hpd" is much more standard and it's unlikely to matter unless someone quickly goes and implements HPD in the driver. - It is sensible to specify "no-hpd" at the bridge chip level and specify "hpd-gpios" at the panel level. That would mean HPD is hooked up to some other GPIO in the system, just not the hardware HPD pin on the bridge chip. [1] https://lore.kernel.org/r/20200417180819.GE5861@pendragon.ideasonboard.com Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Linus Walleij Reviewed-by: Laurent Pinchart --- Changes in v5: None Changes in v4: - Tacked on "or is otherwise unusable." to description. Changes in v3: - useful implement => useful to implement Changes in v2: - ("dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd") new for v2. .../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml index 07d26121afca..be10e8cf31e1 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -28,6 +28,12 @@ properties: maxItems: 1 description: GPIO specifier for GPIO1 pin on bridge (active low). + no-hpd: + type: boolean + description: + Set if the HPD line on the bridge isn't hooked up to anything or is + otherwise unusable. + vccio-supply: description: A 1.8V supply that powers the digital IOs. @@ -213,6 +219,8 @@ examples: clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>; From patchwork Thu May 7 21:35:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11534939 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3528A139A for ; Thu, 7 May 2020 21:35:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1DE0A20CC7 for ; Thu, 7 May 2020 21:35:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jsEDGiwh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727094AbgEGVfl (ORCPT ); Thu, 7 May 2020 17:35:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727110AbgEGVfg (ORCPT ); Thu, 7 May 2020 17:35:36 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9524C05BD0B for ; Thu, 7 May 2020 14:35:35 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id a7so3227134pju.2 for ; Thu, 07 May 2020 14:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4v4vnXxurYJQOROnZvnzfPloWHp2bwE01an31yUPp4o=; b=jsEDGiwhIeWeIH5fsxZpLrFy4wAWrwHVPQ0Th5YaMdW+DiPGF2V2BrQMyLzoKF17KF qOZcFB9rQwZ1ibCZZ7iw4wbdZFNITQzkcLMUR6z/TFf0zAHfWY2lf/cGJq0O1FOcsMFr KWwrbKtdHEusvC97ESZz7VfnP6l0eiZX9wXIg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4v4vnXxurYJQOROnZvnzfPloWHp2bwE01an31yUPp4o=; b=hD0FQ0lngam3BN2CoMBNY/eVp+UJOg4pL7r5tpCfG6Ic1nxQpOVe2xyoZQj2YLj6xM Fhfe73HSZ7KlkapCYuyd3OrOiIE9tbCzXfP/DpzRaomNS1vMc4Ncya3/PmC1085mjUsZ +8pfTUt1A7pr2qnA8EWWfjywTRjbXxENodi3LTiXGLSRvlDKPZJDng5FCckOcpcDICOR /aG/ol4LvU0T8wNNpl6sqi5SVuN677nIwYFdm/gGRcl0QRq+YF3ZsRnjW3IBGLL1g12M RWrAm9zddKoCnupcjUbosl+WwVf2Xp9gAGcz4kGCLiw0BB9S7Ar/5vFhdHEnt64qaaJE hPGw== X-Gm-Message-State: AGi0PuaKciDKufmuLvpXcuMy1L9DTYY4JYtZ95VdkobV+aI8jqUUZtU6 64q222yplcrcCr0APP8FGHLt4w== X-Google-Smtp-Source: APiQypJrX9Sds2V0tZ/XbcQs1N2tNz4bQqjgUQgoczdv15D6aqrUlNeX63mmz/+P2v3/w/VqhJ8N3w== X-Received: by 2002:a17:902:9f90:: with SMTP id g16mr15528385plq.215.1588887335252; Thu, 07 May 2020 14:35:35 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id i10sm5884860pfa.166.2020.05.07.14.35.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 14:35:34 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, bjorn.andersson@linaro.org, swboyd@chromium.org, jernej.skrabec@siol.net, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, robdclark@chromium.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH v5 6/6] arm64: dts: sdm845: Add "no-hpd" to sn65dsi86 on cheza Date: Thu, 7 May 2020 14:35:00 -0700 Message-Id: <20200507143354.v5.6.I89df9b6094549b8149aa8b8347f7401c678055b0@changeid> X-Mailer: git-send-email 2.26.2.645.ge9eca65c58-goog In-Reply-To: <20200507213500.241695-1-dianders@chromium.org> References: <20200507213500.241695-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We don't have the HPD line hooked up to the bridge chip. Add it as suggested in the patch ("dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd"). NOTE: this patch isn't expected to have any effect but just keeps us cleaner for the future. Currently the driver in Linux just assumes that nobody has HPD hooked up. This change allows us to later implement HPD support in the driver without messing up sdm845-cheza. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - ("arm64: dts: sdm845: Add "no-hpd" to sn65dsi86 on cheza") new for v2. arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 9070be43a309..5938f8b2aa2f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -548,6 +548,8 @@ sn65dsi86_bridge: bridge@2d { clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>;