From patchwork Sat May 9 06:58:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11537981 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 48A2E17EA for ; Sat, 9 May 2020 06:58:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2DC0324969 for ; Sat, 9 May 2020 06:58:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sOlIWa+p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728944AbgEIG6d (ORCPT ); Sat, 9 May 2020 02:58:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728471AbgEIG6b (ORCPT ); Sat, 9 May 2020 02:58:31 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA938C061A0C; Fri, 8 May 2020 23:58:32 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id v63so2148160pfb.10; Fri, 08 May 2020 23:58:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1+50jpOtQ+yabtvOjIxdeqHbLW4bp1NAnAuKLsw1+do=; b=sOlIWa+ptEVcyXiLC/Bxln73BJva7q/80JuA5nMyFbl1isr96GlpRnuLTiIRXGrMvZ DBAeaHNoUDtcQUdx/w7pWDMhCtmoHwKGJM4udILbfyd/Sz10R3mBs0h4Ib3hos9TRIXh FnT/8XPlv9svitcANdJtArVywaD8oHJbX2QbjXHTm7WU2bX/iuorbNc22YS6L4DjcBKP PAaCuTDpQvv53QDfPqZddlPjWdtE6iAHjhOJGlIPlNERtF9zLgJNcgB+dHUawVl0Ta+B 5D7oeM98d+YhAWeaB6r0qs4zI95n51fa2YMxrCAaYMfT9BmeFjqkN+H7SKPJb/czRjZh ue4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1+50jpOtQ+yabtvOjIxdeqHbLW4bp1NAnAuKLsw1+do=; b=cUm+/YwTLuCPqD20XpJgH3TlbspvMjJzZAmLkX9rFd/2mXvtp2LiycV2zQPKxOByDu /EdW+jogo+tgjaQWw1oWdV5YjEHUvQd6iKSG0iwRXWte7Bqpj1AARAcaBdHVUUcF9tTJ rGqeo7EOfpzCW9Zw2xz2rBx2UFK2VagZeb91nQpe+iVz1hXLUqgpgllcKOkr7psC4SJq UQgSD7+iLFJS8uZ4JuC+eoiCaZPT/vTE+0h7b+IX+0J0k0PW6P2NRwTRH/st5P/rxcTG nhSPmuqzJmxdwzfoHh6csA4lTRB7KX4iaa+ZouqiXO57AoMcRjQFcG/3S63YXSwN4TxN Rf1g== X-Gm-Message-State: AGi0PuaMZYF2rfPnuoe0WF69QYUVq2SlJn9i/s+Taet3WKyTjhDTtAXF Pke9yFfL9ZPUXY6e7PEw3tc= X-Google-Smtp-Source: APiQypInpnXmSjjXJsppu2FYVV/nnWDkxAp8QyIQOIObhx4wp1sle8YpOuNdgiBAcaE2pnKKmuwEIA== X-Received: by 2002:a63:175c:: with SMTP id 28mr5011956pgx.44.1589007512399; Fri, 08 May 2020 23:58:32 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.190.146]) by smtp.gmail.com with ESMTPSA id w192sm3811572pff.126.2020.05.08.23.58.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 May 2020 23:58:32 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, broonie@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dillonhua@gmail.com, dillon min Subject: [PATCH 1/3] ARM: dts: stm32: Add pin map for spi5 on stm32f429-disco board Date: Sat, 9 May 2020 14:58:21 +0800 Message-Id: <1589007503-9523-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589007503-9523-1-git-send-email-dillon.minfei@gmail.com> References: <1589007503-9523-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: dillon min This patch adds the pin configuration for ltdc, spi5 controller on stm32f429-disco board. Signed-off-by: dillon min --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 392fa14..54c1b27 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -316,6 +316,23 @@ }; }; + spi5_pins: spi5-0 { + pins1 { + pinmux = , + /* SPI5_CLK */ + ; + /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + /* SPI5_MISO */ + bias-disable; + }; + }; + dcmi_pins: dcmi-0 { pins { pinmux = , /* DCMI_HSYNC */ From patchwork Sat May 9 06:58:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11537985 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 23593186E for ; Sat, 9 May 2020 06:58:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0CABA24953 for ; Sat, 9 May 2020 06:58:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="vXdN8oyp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729009AbgEIG6g (ORCPT ); Sat, 9 May 2020 02:58:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728471AbgEIG6f (ORCPT ); Sat, 9 May 2020 02:58:35 -0400 Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7060FC061A0C; Fri, 8 May 2020 23:58:36 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id l12so1951521pgr.10; Fri, 08 May 2020 23:58:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e7MiLH7+SCtzdt0PBk2oBWo6WTMfe3HTrl4Wg7fT5b8=; b=vXdN8oypTs3z11xY+tYCbwNsJsWc09M2NTfdgk362GzYGjuOhmweKw0fBqIjtJRioO 4Bv2v2sRxvLiDGjJmyCn4v9XqjuvHLlmlaZuKER9aC77SYKfRPygWHeEDqeDeL19wvXG jDY2fx0dJy2qJOM28eDgrAOcySYfq1+V+jbso60kjUwVPh0IlCO8X2HxsSQiJ+TkQnc6 RybMCGAZu6zTMRecBvOtL6h9sG6cXQ1va2DRKE1o14L5aOXP3Hb920UtA8Fz075lIUSA plWojAKpTbjrEFwUcnUiTwXg7Db3GhsX7TRNppYgWIgcJ7INMfsd9Q19BWcwqPdLlQl3 q+EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e7MiLH7+SCtzdt0PBk2oBWo6WTMfe3HTrl4Wg7fT5b8=; b=hiB6ibltfgtrFaRJIaDKOumMf+mEExmnZoSj3DPB57lCKKlUPtWCppDA7IfkGn9ANT MF+sMVZcmw+Df03FHnLQgv+rZXrGajhCZ2lI0s5qvfFMWrxKFrYrWiE/Y+YbdS0jPxfy +OJ3a3B40iLItWyIvoVc0cDPoTAiIh4hsaZvg11DzcnmEATrRiCeh7G/SkA7HndOUGsz T30S+DbyU2tuoI+Ch2EGxm8Sf/fKq4zzn7t1/qf9CG18ZBn34HUSpXreNECNICKPrvf9 Q6MEQS3M5mjrq5Gq92XN+zU7lVClWaBJf2DZCMQJMXS7omiuAWJruZdvHJIPqzZNslLa AzAA== X-Gm-Message-State: AGi0PuafQdPn6qrjVV0TlnLPVsndEnJdaj0yinuaNrtdaVsjXPeIkJgr 9CncR+NPGXYj/dOG3KyX2U4= X-Google-Smtp-Source: APiQypK3wT9LttykvZaRfxnpnUFiKYc9Ap/hkzHYXBDRd2HlFmINnaeauCt6vlHaxkkOFfT6f8Szuw== X-Received: by 2002:aa7:8509:: with SMTP id v9mr6968735pfn.110.1589007516067; Fri, 08 May 2020 23:58:36 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.190.146]) by smtp.gmail.com with ESMTPSA id w192sm3811572pff.126.2020.05.08.23.58.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 May 2020 23:58:35 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, broonie@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dillonhua@gmail.com, dillon min Subject: [PATCH 2/3] ARM: dts: stm32: enable l3gd20 on stm32429-disco board Date: Sat, 9 May 2020 14:58:22 +0800 Message-Id: <1589007503-9523-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589007503-9523-1-git-send-email-dillon.minfei@gmail.com> References: <1589007503-9523-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: dillon min Enable l3gd20 on stm32429-disco board. Signed-off-by: dillon min --- arch/arm/boot/dts/stm32f429-disco.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 30c0f67..d365358 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -49,6 +49,8 @@ #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" #include +#include +#include / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -127,3 +129,25 @@ pinctrl-names = "default"; status = "okay"; }; + +&spi5 { + status = "okay"; + pinctrl-0 = <&spi5_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + dmas = <&dma2 3 2 0x400 0x0>, + <&dma2 4 2 0x400 0x0>; + dma-names = "rx", "tx"; + l3gd20: l3gd20@0 { + compatible = "st,l3gd20-gyro"; + spi-max-frequency = <10000000>; + st,drdy-int-pin = <2>; + interrupt-parent = <&gpioa>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>, + <2 IRQ_TYPE_EDGE_RISING>; + reg = <0>; + status = "okay"; + }; +}; From patchwork Sat May 9 06:58:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11537987 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0FA4292A for ; Sat, 9 May 2020 06:58:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E76A52495A for ; Sat, 9 May 2020 06:58:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FTLFO1Bh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729021AbgEIG6l (ORCPT ); Sat, 9 May 2020 02:58:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728471AbgEIG6j (ORCPT ); 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[ 2.737504] st-gyro-spi: probe of spi0.0 failed with error -22 " after debug into spi-stm32 driver, st-gyro-spi split two steps to read l3gd20 id first: send command to l3gd20 with read id command in tx_buf, rx_buf is null. second: read id with tx_buf is null, rx_buf not null. so, for second step, stm32 driver recongise this process is SPI_SIMPLE_RX from stm32_spi_communication_type, but there is no related process for this type in stm32f4_spi_set_mode, then we get error from stm32_spi_transfer_one_setup. we can use two method to fix this bug. 1, use stm32 spi's "In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)". but as our code running in sdram, the read latency is too large to get so many receive overrun error in interrupts handler. 2, use stm32 spi's "In full-duplex (BIDIMODE=0 and RXONLY=0)", as tx_buf is null, we must add dummy data sent out before read data. so, add stm32f4_spi_tx_dummy to handle this situation. Signed-off-by: dillon min --- drivers/spi/spi-stm32.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 44ac6eb3..bcf1ba7 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -388,6 +388,13 @@ static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) return count; } +static void stm32f4_spi_tx_dummy(struct stm32_spi *spi) +{ + if (spi->cur_bpw == 16) + writew_relaxed(0x5555, spi->base + STM32F4_SPI_DR); + else + writeb_relaxed(0x55, spi->base + STM32F4_SPI_DR); +} /** * stm32f4_spi_get_bpw_mask - Return bits per word mask * @spi: pointer to the spi controller data structure @@ -811,7 +818,9 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) mask |= STM32F4_SPI_SR_TXE; } - if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) { + if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || + spi->cur_comm == SPI_SIMPLEX_RX || + spi->cur_comm == SPI_3WIRE_RX)) { /* TXE flag is set and is handled when RXNE flag occurs */ sr &= ~STM32F4_SPI_SR_TXE; mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; @@ -850,8 +859,10 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) stm32f4_spi_read_rx(spi); if (spi->rx_len == 0) end = true; - else /* Load data for discontinuous mode */ + else if (spi->tx_buf)/* Load data for discontinuous mode */ stm32f4_spi_write_tx(spi); + else if (spi->cur_comm == SPI_SIMPLEX_RX) + stm32f4_spi_tx_dummy(spi); } end_irq: @@ -1151,7 +1162,9 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) /* Enable the interrupts relative to the current communication mode */ if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { cr2 |= STM32F4_SPI_CR2_TXEIE; - } else if (spi->cur_comm == SPI_FULL_DUPLEX) { + } else if (spi->cur_comm == SPI_FULL_DUPLEX || + spi->cur_comm == SPI_SIMPLEX_RX || + spi->cur_comm == SPI_3WIRE_RX) { /* In transmit-only mode, the OVR flag is set in the SR register * since the received data are never read. Therefore set OVR * interrupt only when rx buffer is available. @@ -1170,6 +1183,8 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) /* starting data transfer when buffer is loaded */ if (spi->tx_buf) stm32f4_spi_write_tx(spi); + else if (spi->cur_comm == SPI_SIMPLEX_RX) + stm32f4_spi_tx_dummy(spi); spin_unlock_irqrestore(&spi->lock, flags); @@ -1462,10 +1477,16 @@ static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_BIDIMODE | STM32F4_SPI_CR1_BIDIOE); - } else if (comm_type == SPI_FULL_DUPLEX) { + } else if (comm_type == SPI_FULL_DUPLEX || + comm_type == SPI_SIMPLEX_RX) { stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_BIDIMODE | STM32F4_SPI_CR1_BIDIOE); + } else if (comm_type == SPI_3WIRE_RX) { + stm32_spi_set_bits(spi, STM32F4_SPI_CR1, + STM32F4_SPI_CR1_BIDIMODE); + stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, + STM32F4_SPI_CR1_BIDIOE); } else { return -EINVAL; }