From patchwork Tue May 12 07:36:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11542241 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E0A41913 for ; Tue, 12 May 2020 07:37:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8A2B20733 for ; Tue, 12 May 2020 07:37:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="G47sGn4T" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729065AbgELHhA (ORCPT ); Tue, 12 May 2020 03:37:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727859AbgELHhA (ORCPT ); Tue, 12 May 2020 03:37:00 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C904C061A0C; Tue, 12 May 2020 00:36:59 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id x10so5035592plr.4; Tue, 12 May 2020 00:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1+50jpOtQ+yabtvOjIxdeqHbLW4bp1NAnAuKLsw1+do=; b=G47sGn4TN89HEfDHIlpV4L/1OTdbO4A512abcr2Q6siKyVvi03Bex0c/ELQlwJIxeC tIZpjUJVEe7tdocPqLpuCIdwP37zsuHnu0unHBL/9tyMyfq1xvzsfWMgamvXnH+oueZR 0oOt/MwLxV7aWWjGONudiPRNYxzkoYYoEw0jmndA2AKTJIZZ7i0UYciPrlJjdTGNVwX8 L4fm20sFG926zL5N7wAcGAXpX5Ix5B/lirLwhzDXmd8U3B1P/u9toWrSxuaOZ1KI5/gJ +rv5oc7F+faxwweAeljXXxhEzJY90igkfcWkaPenQrTaS+0UzDx86i9KAACaGvXOCFo7 BRTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1+50jpOtQ+yabtvOjIxdeqHbLW4bp1NAnAuKLsw1+do=; b=PGshP2vQN7KEVdzFBGpaUY64ymL0HUQaa92XbZgklZK4y42a+uzAdUgFwR3hdbvWai knkZtQJBKnFF9JEWYyv+pEirq2rBuF7QEP1sBKGmexWQAPCOD+PrBuUoZCUyPYB14ra3 tbhk6JE90pVyu36pTI3gwY8ngUi7ZTJ7tSEUvtrzWI9415SQfhwSTuMHtZLu8VRkxGgi 1APqYvwLackl87l5/s5glXiqPe5D1iWwGANogRdG8+7LRiD50gxb9tqaqqA4WvidQLVj b41XJnn4kVFmtqqf374S1lWh6/eWmGUUNVgYXCbBRiJtHLmrjLExybGynMvrOh0h7YhL BV3Q== X-Gm-Message-State: AGi0PuZUYjaCBI9LfPVsV0x6h8xFlhr29RRDtVyPeBMZEb3mg4yrDuq0 zKBn/vfc3h1TtwsoNyHBAIQ= X-Google-Smtp-Source: APiQypIro3QqgqzACddslZcezZZ3teK8Kwq4T65hw26DXUKtwZPMtU58nk+jjImORx23aPyHjnHRfg== X-Received: by 2002:a17:90a:7046:: with SMTP id f64mr24142240pjk.205.1589269019133; Tue, 12 May 2020 00:36:59 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.190.146]) by smtp.gmail.com with ESMTPSA id 5sm11732471pjf.19.2020.05.12.00.36.55 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 May 2020 00:36:58 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, broonie@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dillonhua@gmail.com, dillon.minfei@gmail.com Subject: [PATCH v2 1/3] ARM: dts: stm32: Add pin map for spi5 on stm32f429-disco board Date: Tue, 12 May 2020 15:36:48 +0800 Message-Id: <1589269010-18472-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589269010-18472-1-git-send-email-dillon.minfei@gmail.com> References: <1589269010-18472-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: dillon min This patch adds the pin configuration for ltdc, spi5 controller on stm32f429-disco board. Signed-off-by: dillon min --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 392fa14..54c1b27 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -316,6 +316,23 @@ }; }; + spi5_pins: spi5-0 { + pins1 { + pinmux = , + /* SPI5_CLK */ + ; + /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + /* SPI5_MISO */ + bias-disable; + }; + }; + dcmi_pins: dcmi-0 { pins { pinmux = , /* DCMI_HSYNC */ From patchwork Tue May 12 07:36:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11542243 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB9E7913 for ; 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Tue, 12 May 2020 00:37:02 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.190.146]) by smtp.gmail.com with ESMTPSA id 5sm11732471pjf.19.2020.05.12.00.36.59 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 May 2020 00:37:02 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, broonie@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dillonhua@gmail.com, dillon.minfei@gmail.com Subject: [PATCH v2 2/3] ARM: dts: stm32: enable l3gd20 on stm32429-disco board Date: Tue, 12 May 2020 15:36:49 +0800 Message-Id: <1589269010-18472-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589269010-18472-1-git-send-email-dillon.minfei@gmail.com> References: <1589269010-18472-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: dillon min L3gd20, st mems motion sensor, 3-axis digital output gyroscope, connect to stm32f429 via spi5 Signed-off-by: dillon min --- Hi Alexandre, V2: 1, insert blank line at stm32f420-disco.dts line 143 2, add more description about l3gd20 in commit message V1: enable l3gd20 dts binding on stm32f429-disco thanks. dillon, arch/arm/boot/dts/stm32f429-disco.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 30c0f67..1bfb903 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -49,6 +49,8 @@ #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" #include +#include +#include / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -127,3 +129,26 @@ pinctrl-names = "default"; status = "okay"; }; + +&spi5 { + status = "okay"; + pinctrl-0 = <&spi5_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + dmas = <&dma2 3 2 0x400 0x0>, + <&dma2 4 2 0x400 0x0>; + dma-names = "rx", "tx"; + + l3gd20: l3gd20@0 { + compatible = "st,l3gd20-gyro"; + spi-max-frequency = <10000000>; + st,drdy-int-pin = <2>; + interrupt-parent = <&gpioa>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>, + <2 IRQ_TYPE_EDGE_RISING>; + reg = <0>; + status = "okay"; + }; +}; From patchwork Tue May 12 07:36:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11542245 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D1BAC14C0 for ; Tue, 12 May 2020 07:37:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BA5F9206B7 for ; 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Tue, 12 May 2020 00:37:06 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.190.146]) by smtp.gmail.com with ESMTPSA id 5sm11732471pjf.19.2020.05.12.00.37.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 May 2020 00:37:05 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, broonie@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dillonhua@gmail.com, dillon.minfei@gmail.com Subject: [PATCH v2 3/3] spi: stm32: Add SPI_SIMPLEX_RX, SPI_3WIRE_RX support for stm32f4 Date: Tue, 12 May 2020 15:36:50 +0800 Message-Id: <1589269010-18472-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589269010-18472-1-git-send-email-dillon.minfei@gmail.com> References: <1589269010-18472-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: dillon min in l3gd20 driver startup, there is a setup failed error return from stm32 spi driver " [ 2.687630] st-gyro-spi spi0.0: supply vdd not found, using dummy regulator [ 2.696869] st-gyro-spi spi0.0: supply vddio not found, using dummy regulator [ 2.706707] spi_stm32 40015000.spi: SPI transfer setup failed [ 2.713741] st-gyro-spi spi0.0: SPI transfer failed: -22 [ 2.721096] spi_master spi0: failed to transfer one message from queue [ 2.729268] iio iio:device0: failed to read Who-Am-I register. [ 2.737504] st-gyro-spi: probe of spi0.0 failed with error -22 " after debug into spi-stm32 driver, st-gyro-spi split two steps to read l3gd20 id first: send command to l3gd20 with read id command in tx_buf, rx_buf is null. second: read id with tx_buf is null, rx_buf not null. so, for second step, stm32 driver recongise this process is SPI_SIMPLE_RX from stm32_spi_communication_type, but there is no related process for this type in stm32f4_spi_set_mode, then we get error from stm32_spi_transfer_one_setup. we can use two method to fix this bug. 1, use stm32 spi's "In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)". but as our code running in sdram, the read latency is too large to get so many receive overrun error in interrupts handler. 2, use stm32 spi's "In full-duplex (BIDIMODE=0 and RXONLY=0)", as tx_buf is null, we must add dummy data sent out before read data. so, add stm32f4_spi_tx_dummy to handle this situation. Signed-off-by: dillon min --- drivers/spi/spi-stm32.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 44ac6eb3..bcf1ba7 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -388,6 +388,13 @@ static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) return count; } +static void stm32f4_spi_tx_dummy(struct stm32_spi *spi) +{ + if (spi->cur_bpw == 16) + writew_relaxed(0x5555, spi->base + STM32F4_SPI_DR); + else + writeb_relaxed(0x55, spi->base + STM32F4_SPI_DR); +} /** * stm32f4_spi_get_bpw_mask - Return bits per word mask * @spi: pointer to the spi controller data structure @@ -811,7 +818,9 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) mask |= STM32F4_SPI_SR_TXE; } - if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) { + if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || + spi->cur_comm == SPI_SIMPLEX_RX || + spi->cur_comm == SPI_3WIRE_RX)) { /* TXE flag is set and is handled when RXNE flag occurs */ sr &= ~STM32F4_SPI_SR_TXE; mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; @@ -850,8 +859,10 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) stm32f4_spi_read_rx(spi); if (spi->rx_len == 0) end = true; - else /* Load data for discontinuous mode */ + else if (spi->tx_buf)/* Load data for discontinuous mode */ stm32f4_spi_write_tx(spi); + else if (spi->cur_comm == SPI_SIMPLEX_RX) + stm32f4_spi_tx_dummy(spi); } end_irq: @@ -1151,7 +1162,9 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) /* Enable the interrupts relative to the current communication mode */ if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { cr2 |= STM32F4_SPI_CR2_TXEIE; - } else if (spi->cur_comm == SPI_FULL_DUPLEX) { + } else if (spi->cur_comm == SPI_FULL_DUPLEX || + spi->cur_comm == SPI_SIMPLEX_RX || + spi->cur_comm == SPI_3WIRE_RX) { /* In transmit-only mode, the OVR flag is set in the SR register * since the received data are never read. Therefore set OVR * interrupt only when rx buffer is available. @@ -1170,6 +1183,8 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) /* starting data transfer when buffer is loaded */ if (spi->tx_buf) stm32f4_spi_write_tx(spi); + else if (spi->cur_comm == SPI_SIMPLEX_RX) + stm32f4_spi_tx_dummy(spi); spin_unlock_irqrestore(&spi->lock, flags); @@ -1462,10 +1477,16 @@ static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_BIDIMODE | STM32F4_SPI_CR1_BIDIOE); - } else if (comm_type == SPI_FULL_DUPLEX) { + } else if (comm_type == SPI_FULL_DUPLEX || + comm_type == SPI_SIMPLEX_RX) { stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_BIDIMODE | STM32F4_SPI_CR1_BIDIOE); + } else if (comm_type == SPI_3WIRE_RX) { + stm32_spi_set_bits(spi, STM32F4_SPI_CR1, + STM32F4_SPI_CR1_BIDIMODE); + stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, + STM32F4_SPI_CR1_BIDIOE); } else { return -EINVAL; }