From patchwork Thu May 14 12:38:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11548619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3100860D for ; Thu, 14 May 2020 12:38:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 11B3720722 for ; Thu, 14 May 2020 12:38:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 11B3720722 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95F9C6EB35; Thu, 14 May 2020 12:38:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 439246EB32 for ; Thu, 14 May 2020 12:38:42 +0000 (UTC) IronPort-SDR: 2O/oD9v1BEo0c/A/UstuGjB4NNrubTp/J8dfvOX1gfVSupGI795DKDwGzyrlFtMCgAM5Y7RmRq 79FX1ynL4Tew== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2020 05:38:41 -0700 IronPort-SDR: bZNBxCXj6u75CvRRlJmQyhAhGHiUtrf59TH3btbbqBoA82MFi3maLgkc2ivQSmorcmkVIwblMS FBppXC2Uy78Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,391,1583222400"; d="scan'208";a="280841934" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 14 May 2020 05:38:39 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 14 May 2020 15:38:38 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 14 May 2020 15:38:36 +0300 Message-Id: <20200514123838.3017-1-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/3] drm/i915: Fix 400 MHz FSB readout on elk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Looks like elk redefines some of the CLKCFG FSB values to make room for 400 MHz FSB. The setting overlaps with one of the 266MHz settings (which is even documented in the ctg docs, and cofirmed to be correct on my ctg). So we limit the special case to elk only. Though it might also be that we have some kind of desktop vs. mobile difference going on here as eg. both g35 and elk use 0x0 for the 266 MHz setting, vs. 0x6 used by ctg). The g35 doesn't let me select 400MHz for the FSB strap so can't confirm which way it would go here. But anyways as it seems only elk has the 400MHz option we shouldn't lose anything by limiting the special case to it alone. My earlier experiments on this appear to have been nonsense as the comment I added claims that FSB strap of 400MHz results in a value of 0x4, but I've now retested it and I definitely get a value of 0x6 instead. So let's remove that bogus comment. v2: s/_ELK/_ALT/ in the define in anticipation of a full mobile vs. desktop CLKCFG split Signed-off-by: Ville Syrjälä Acked-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_cdclk.c | 9 +++++++-- drivers/gpu/drm/i915/i915_reg.h | 6 +----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 979a0241fdcb..c17cf611625c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2705,8 +2705,13 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) u32 clkcfg; /* hrawclock is 1/4 the FSB frequency */ - clkcfg = intel_de_read(dev_priv, CLKCFG); - switch (clkcfg & CLKCFG_FSB_MASK) { + clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; + + /* ELK seems to redefine some of the values */ + if (IS_G45(dev_priv) && clkcfg == CLKCFG_FSB_1600_ALT) + return 400000; + + switch (clkcfg) { case CLKCFG_FSB_400: return 100000; case CLKCFG_FSB_533: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6c076a24eb82..10187780e06c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3775,12 +3775,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ -/* - * Note that on at least on ELK the below value is reported for both - * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet - * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz. - */ #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ +#define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */ #define CLKCFG_FSB_MASK (7 << 0) #define CLKCFG_MEM_533 (1 << 4) #define CLKCFG_MEM_667 (2 << 4) From patchwork Thu May 14 12:38:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11548623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A80E960D for ; Thu, 14 May 2020 12:38:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 908B120722 for ; Thu, 14 May 2020 12:38:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 908B120722 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 180786EB32; Thu, 14 May 2020 12:38:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3697E6EB32 for ; Thu, 14 May 2020 12:38:45 +0000 (UTC) IronPort-SDR: T7Q8usbHLdvULBMvGJJgY1CouXOG2hgziv7gCCn5D5Lk7T6sCTyvgvPX9l7lY6pfzOXQwyBomJ M4vtFQF1URhw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2020 05:38:44 -0700 IronPort-SDR: p/MhGKW2V8xltSce/h0FyaCa91XiJyVkpA9X33QlSqimdzkCEcw/SRV8HIYf8RumDVhy/NDXrg UkOyjlGZOOjQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,391,1583222400"; d="scan'208";a="252067962" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 14 May 2020 05:38:42 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 14 May 2020 15:38:41 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 14 May 2020 15:38:37 +0300 Message-Id: <20200514123838.3017-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514123838.3017-1-ville.syrjala@linux.intel.com> References: <20200514123838.3017-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915: Document our lackluster FSB frequency readout X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Document the fact that we aren't reading out the actual FSB frequency but rather just the state of the FSB straps. Some BIOSen allow you to configure the two independently. So if someone sets the two up in an inconsistent manner we'll get the wrong answer here and thus will end up with incorrect aux/pps clock dividers. Alas, proper docs are no longer around so we can't do any better. Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c17cf611625c..d57dfec7e9a5 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2704,7 +2704,16 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) { u32 clkcfg; - /* hrawclock is 1/4 the FSB frequency */ + /* + * hrawclock is 1/4 the FSB frequency + * + * Note that this only reads the state of the FSB + * straps, not the actual FSB frequency. Some BIOSen + * let you configure each independently. Ideally we'd + * read out the actual FSB frequency but sadly we + * don't know which registers have that information, + * and all the relevant docs have gone to bit heaven :( + */ clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; /* ELK seems to redefine some of the values */ From patchwork Thu May 14 12:38:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11548631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 227F2739 for ; Thu, 14 May 2020 12:38:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B0CC20722 for ; Thu, 14 May 2020 12:38:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B0CC20722 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D0D26EB33; Thu, 14 May 2020 12:38:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id E15166EB33 for ; Thu, 14 May 2020 12:38:50 +0000 (UTC) IronPort-SDR: Gs1EM+bSsSGR9hCTXs/dHZCQf4qDbS4L+byL0k9N9P0pfEOgJG6kLK6e9cXvY9DuS0GUH806n8 JMNMtLNM/BgA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2020 05:38:50 -0700 IronPort-SDR: JmM4T2Wtw40gs2Zq+5unfum1vOdyJm4aSgf6luXXC4l61M++qP1jnp4z0OK6DqfWKvENKvZgQ1 cmwI+w0Cvr/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,391,1583222400"; d="scan'208";a="298020608" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 14 May 2020 05:38:45 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 14 May 2020 15:38:44 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 14 May 2020 15:38:38 +0300 Message-Id: <20200514123838.3017-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514123838.3017-1-ville.syrjala@linux.intel.com> References: <20200514123838.3017-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915: Read out hrawclk on all gen3+ platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä I've checked a bunch of gen3/4 machines and all seem to have consistent FSB frequency information in the CLKCFG register. So let's read out hrawclk on all gen3+ machines. Although apart from g4x/pnv aux/pps dividers we only really need this for for i965g/gm cs timestamp increment. The CLKCFG memory clock values seem less consistent but we don't care about those here. For posterity here's a list of CLKCFG vs. FSB dumps from a bunch of machines (only missing lpt for a full set): machine CLKCFG FSB alv1 0x00001411 533 alv2 0x00000420 400 (Chris) gdg1 0x20000022 800 gdg2 0x20000022 800 cst 0x00010043 666 blb 0x00002034 1333 pnv1 0x00000423 666 pnv2 0x00000433 666 965gm 0x00004342 800 946gz 0x00000022 800 965g 0x00000422 800 g35 0x00000430 1066 0x00000434 1333 ctg1 0x00644056 1066 ctg2 0x00644066 1066 elk1 0x00012420 1066 0x00012424 1333 0x00012436 1600 0x00012422 800 elk2 0x00012040 1066 For the mobile parts the chipset docs generally have these documented to some degree (alv being the exception). The two settings w/o any evidence are 0x5=400MHz on desktop and 0x7=1333MHz on mobile. Though the mobile 1333MHz case probably doesn't even exist since ctg is only documented to go up to 1066MHz. v2: Fix 400mhz readout for Chris's alv/celeron machine Do a clean mobile vs. dekstop split since that's really what seems to be going on Cc: Chris Wilson Cc: Lionel Landwerlin Signed-off-by: Ville Syrjälä Acked-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_cdclk.c | 64 ++++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 3 +- 2 files changed, 42 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index d57dfec7e9a5..9419a4724357 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2700,7 +2700,7 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv) CCK_DISPLAY_REF_CLOCK_CONTROL); } -static int g4x_hrawclk(struct drm_i915_private *dev_priv) +static int i9xx_hrawclk(struct drm_i915_private *dev_priv) { u32 clkcfg; @@ -2716,27 +2716,43 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) */ clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; - /* ELK seems to redefine some of the values */ - if (IS_G45(dev_priv) && clkcfg == CLKCFG_FSB_1600_ALT) - return 400000; - - switch (clkcfg) { - case CLKCFG_FSB_400: - return 100000; - case CLKCFG_FSB_533: - return 133333; - case CLKCFG_FSB_667: - return 166667; - case CLKCFG_FSB_800: - return 200000; - case CLKCFG_FSB_1067: - case CLKCFG_FSB_1067_ALT: - return 266667; - case CLKCFG_FSB_1333: - case CLKCFG_FSB_1333_ALT: - return 333333; - default: - return 133333; + if (IS_MOBILE(dev_priv)) { + switch (clkcfg) { + case CLKCFG_FSB_400: + return 100000; + case CLKCFG_FSB_533: + return 133333; + case CLKCFG_FSB_667: + return 166667; + case CLKCFG_FSB_800: + return 200000; + case CLKCFG_FSB_1067: + return 266667; + case CLKCFG_FSB_1333: + return 333333; + default: + MISSING_CASE(clkcfg); + return 133333; + } + } else { + switch (clkcfg) { + case CLKCFG_FSB_400_ALT: + return 100000; + case CLKCFG_FSB_533: + return 133333; + case CLKCFG_FSB_667: + return 166667; + case CLKCFG_FSB_800: + return 200000; + case CLKCFG_FSB_1067_ALT: + return 266667; + case CLKCFG_FSB_1333_ALT: + return 333333; + case CLKCFG_FSB_1600_ALT: + return 400000; + default: + return 133333; + } } } @@ -2757,8 +2773,8 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) freq = pch_rawclk(dev_priv); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) freq = vlv_hrawclk(dev_priv); - else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) - freq = g4x_hrawclk(dev_priv); + else if (INTEL_GEN(dev_priv) >= 3) + freq = i9xx_hrawclk(dev_priv); else /* no rawclk on other platforms, or no need to know it */ return 0; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 10187780e06c..f774ec2bcc99 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3768,7 +3768,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) /* Clocking configuration register */ #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) -#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ +#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */ +#define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */ #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */