From patchwork Fri May 15 10:51:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Prakash Ranjan X-Patchwork-Id: 11551175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 976DF913 for ; Fri, 15 May 2020 10:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 808D320759 for ; Fri, 15 May 2020 10:52:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="uEGVpH8g" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726160AbgEOKwN (ORCPT ); Fri, 15 May 2020 06:52:13 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:10387 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726206AbgEOKwK (ORCPT ); Fri, 15 May 2020 06:52:10 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1589539929; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=Ee8NO6/5OJ52E2zUjD2OXevvWt6lIkUWaN1XFxYR8Yc=; b=uEGVpH8g3G3EPHT0dJF0JKO/JfeT84rfvono/aGfSXdgyFDCYMeRnP4mk+R9X9sPxV33eWlX JgBIxIxrfL+6PdpLk3dHDMg58HGBTb+S70hOcxRqIshK4hHOcbyrtJs5St9CLNkgfCib/NsV PjmsrvggwFAM4p9KKAPOkI5PFxw= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 5ebe744f8ebbf95ecb8fbd53 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 15 May 2020 10:51:59 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 43333C43636; Fri, 15 May 2020 10:51:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-311.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id C7D77C433F2; Fri, 15 May 2020 10:51:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C7D77C433F2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=saiprakash.ranjan@codeaurora.org From: Sai Prakash Ranjan To: Mathieu Poirier , Suzuki K Poulose , Mike Leach , devicetree@vger.kernel.org, Rob Herring , Bjorn Andersson , Andy Gross Cc: Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, Sai Prakash Ranjan Subject: [PATCH 1/2] arm64: dts: qcom: sc7180: Support ETMv4 power management Date: Fri, 15 May 2020 16:21:36 +0530 Message-Id: X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that deep idle states are properly supported on SC7180, we need to add "coresight-loses-context-with-cpu" property to avoid failure of trace session because of losing context on entering deep idle states. Reviewed-by: Stephen Boyd Signed-off-by: Sai Prakash Ranjan --- Resending this because the last patch sent here - https://lore.kernel.org/patchwork/patch/1230367/ seems to have added "coresight-loses-context-with-cpu" to replicator node instead of etm7 node. --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4069bb1c93af..8b3707347547 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1656,6 +1656,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1674,6 +1675,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1692,6 +1694,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1710,6 +1713,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1728,6 +1732,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1746,6 +1751,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1764,6 +1770,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1782,6 +1789,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { From patchwork Fri May 15 10:51:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Prakash Ranjan X-Patchwork-Id: 11551171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B9FF697 for ; Fri, 15 May 2020 10:52:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 640272078C for ; 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spf=none smtp.mailfrom=saiprakash.ranjan@codeaurora.org From: Sai Prakash Ranjan To: Mathieu Poirier , Suzuki K Poulose , Mike Leach , devicetree@vger.kernel.org, Rob Herring , Bjorn Andersson , Andy Gross Cc: Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, Sai Prakash Ranjan Subject: [PATCH 2/2] arm64: dts: qcom: sc7180: Add support to skip powering up of ETM Date: Fri, 15 May 2020 16:21:37 +0530 Message-Id: <7599d58142dcefbcb08a2eaff71c7f411a1d52b1.1589539293.git.saiprakash.ranjan@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add "qcom,skip-power-up" property to skip powering up ETM on SC7180 SoC to workaround a hardware errata where CPU watchdog counter is stopped when ETM power up bit is set (i.e., when TRCPDCR.PU = 1). Signed-off-by: Sai Prakash Ranjan --- Depends on ETM driver change here - https://lore.kernel.org/patchwork/cover/1242100/ --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8b3707347547..de4bae4ec224 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1657,6 +1657,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1676,6 +1677,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1695,6 +1697,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1714,6 +1717,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1733,6 +1737,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1752,6 +1757,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1771,6 +1777,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1790,6 +1797,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port {