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Due to this we have two issues: 1. cpuhp_setup_state() is called multiple times 2. plic_starting_cpu() can crash for boot CPU if cpuhp_setup_state() is called before boot CPU PLIC handler is available. This patch fixes both above issues. Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 822e074c0600..7dc23edb3267 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -76,6 +76,7 @@ struct plic_handler { void __iomem *enable_base; struct plic_priv *priv; }; +static bool plic_cpuhp_setup_done; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); static inline void plic_toggle(struct plic_handler *handler, @@ -282,6 +283,7 @@ static int __init plic_init(struct device_node *node, int error = 0, nr_contexts, nr_handlers = 0, i; u32 nr_irqs; struct plic_priv *priv; + struct plic_handler *handler; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -310,7 +312,6 @@ static int __init plic_init(struct device_node *node, for (i = 0; i < nr_contexts; i++) { struct of_phandle_args parent; - struct plic_handler *handler; irq_hw_number_t hwirq; int cpu, hartid; @@ -364,9 +365,18 @@ static int __init plic_init(struct device_node *node, nr_handlers++; } - cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + /* + * We can have multiple PLIC instances so setup cpuhp state only + * when context handler for current/boot CPU is present. + */ + handler = this_cpu_ptr(&plic_handlers); + if (handler->present && !plic_cpuhp_setup_done) { + cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", plic_starting_cpu, plic_dying_cpu); + plic_cpuhp_setup_done = true; + } + pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); set_handle_irq(plic_handle_irq); From patchwork Sat May 16 06:38:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11553329 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE86314B7 for ; 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Sat, 16 May 2020 06:39:38 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 2/4] irqchip/sifive-plic: Improve boot prints for multiple PLIC instances Date: Sat, 16 May 2020 12:08:59 +0530 Message-Id: <20200516063901.18365-3-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200516063901.18365-1-anup.patel@wdc.com> References: <20200516063901.18365-1-anup.patel@wdc.com> X-ClientProxiedBy: MAXPR0101CA0002.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::12) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (49.207.60.36) by MAXPR0101CA0002.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.20 via Frontend Transport; Sat, 16 May 2020 06:39:33 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [49.207.60.36] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 12575aca-acdf-451e-615a-08d7f963e7de X-MS-TrafficTypeDiagnostic: DM6PR04MB4539: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:3826; 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Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 7dc23edb3267..2d3db927a551 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -284,6 +284,11 @@ static int __init plic_init(struct device_node *node, u32 nr_irqs; struct plic_priv *priv; struct plic_handler *handler; + struct resource iores; + + error = of_address_to_resource(node, 0, &iores); + if (error) + return error; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -377,8 +382,10 @@ static int __init plic_init(struct device_node *node, plic_cpuhp_setup_done = true; } - pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", - nr_irqs, nr_handlers, nr_contexts); + pr_info("interrupt-controller at 0x%llx " + "(interrupts=%d, contexts=%d, handlers=%d)\n", + (unsigned long long)iores.start, nr_irqs, + nr_contexts, nr_handlers); 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Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 2d3db927a551..e42fc082ad18 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -60,6 +60,7 @@ #define PLIC_ENABLE_THRESHOLD 0 struct plic_priv { + struct irq_chip chip; struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; @@ -76,6 +77,7 @@ struct plic_handler { void __iomem *enable_base; struct plic_priv *priv; }; +static unsigned int plic_count; static bool plic_cpuhp_setup_done; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); @@ -164,20 +166,12 @@ static void plic_irq_eoi(struct irq_data *d) writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); } -static struct irq_chip plic_chip = { - .name = "SiFive PLIC", - .irq_mask = plic_irq_mask, - .irq_unmask = plic_irq_unmask, - .irq_eoi = plic_irq_eoi, -#ifdef CONFIG_SMP - .irq_set_affinity = plic_set_affinity, -#endif -}; - static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { - irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, + struct plic_priv *priv = d->host_data; + + irq_domain_set_info(d, irq, hwirq, &priv->chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); return 0; @@ -294,6 +288,14 @@ static int __init plic_init(struct device_node *node, if (!priv) return -ENOMEM; + priv->chip.name = kasprintf(GFP_KERNEL, "PLIC%d", plic_count++); + priv->chip.irq_mask = plic_irq_mask, + priv->chip.irq_unmask = plic_irq_unmask, + priv->chip.irq_eoi = plic_irq_eoi, +#ifdef CONFIG_SMP + priv->chip.irq_set_affinity = plic_set_affinity, +#endif + priv->regs = of_iomap(node, 0); if (WARN_ON(!priv->regs)) { error = -EIO; @@ -383,9 +385,9 @@ static int __init plic_init(struct device_node *node, } pr_info("interrupt-controller at 0x%llx " - "(interrupts=%d, contexts=%d, handlers=%d)\n", + "(interrupts=%d, contexts=%d, handlers=%d) (%s)\n", (unsigned long long)iores.start, nr_irqs, - nr_contexts, nr_handlers); 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Currently, the default irq affinity for each PLIC interrupt is all online CPUs which is illegal value for default irq affinity when we have multiple PLIC instances. To fix this, we now set "lmask" as the default irq affinity in for each interrupt in plic_irqdomain_map(). Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index e42fc082ad18..9af5e2fd2574 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -174,6 +174,7 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_domain_set_info(d, irq, hwirq, &priv->chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); + irq_set_affinity(irq, &priv->lmask); return 0; }