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[61.228.240.171]) by smtp.gmail.com with ESMTPSA id k27sm3768323pgb.30.2020.05.16.05.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 May 2020 05:50:05 -0700 (PDT) From: Lecopzer Chen To: linux-kernel@vger.kernel.org Subject: [PATCH 1/3] arm_pmu: Add support for perf NMI interrupts registration Date: Sat, 16 May 2020 20:48:55 +0800 Message-Id: <20200516124857.75004-2-lecopzer@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200516124857.75004-1-lecopzer@gmail.com> References: <20200516124857.75004-1-lecopzer@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200516_055006_437714_FCBB72A1 X-CRM114-Status: GOOD ( 11.90 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:642 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [lecopzer[at]gmail.com] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lecopzer.chen@mediatek.com, Lecopzer Chen , alexander.shishkin@linux.intel.com, catalin.marinas@arm.com, jolsa@redhat.com, acme@kernel.org, peterz@infradead.org, mingo@redhat.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, namhyung@kernel.org, will@kernel.org, yj.chiang@mediatek.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Register perf interrupts by request_nmi()/percpu_nmi() when both ARM64_PSEUDO_NMI and ARM64_PSEUDO_NMI_PERF are enabled and nmi cpufreature is active. Signed-off-by: Lecopzer Chen --- drivers/perf/arm_pmu.c | 51 +++++++++++++++++++++++++++++++----- include/linux/perf/arm_pmu.h | 6 +++++ 2 files changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index df352b334ea7..fa37b72d19e2 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -559,6 +559,48 @@ void armpmu_free_irq(int irq, int cpu) per_cpu(cpu_irq, cpu) = 0; } +static void armpmu_prepare_percpu_nmi_other(void *info) +{ + /* + * We don't need to disable preemption since smp_call_function() + * did this for us. + */ + prepare_percpu_nmi((uintptr_t) info); +} + +static int _armpmu_request_irq(unsigned int irq, irq_handler_t handler, + unsigned long flags, int cpu) +{ + if (armpmu_support_nmi()) + return request_nmi(irq, handler, flags, "arm-pmu", + per_cpu_ptr(&cpu_armpmu, cpu)); + return request_irq(irq, handler, flags, "arm-pmu", + per_cpu_ptr(&cpu_armpmu, cpu)); +} + +static int _armpmu_request_percpu_irq(unsigned int irq, irq_handler_t handler) +{ + if (armpmu_support_nmi()) { + int err; + + err = request_percpu_nmi(irq, handler, "arm-pmu", + &cpu_armpmu); + if (err) + return err; + + preempt_disable(); + err = prepare_percpu_nmi(irq); + if (err) { + return err; + preempt_enable(); + } + smp_call_function(armpmu_prepare_percpu_nmi_other, + (void *)(uintptr_t) irq, true); + preempt_enable(); + } + return request_percpu_irq(irq, handler, "arm-pmu", + &cpu_armpmu); +} + int armpmu_request_irq(int irq, int cpu) { int err = 0; @@ -582,12 +624,9 @@ int armpmu_request_irq(int irq, int cpu) IRQF_NO_THREAD; irq_set_status_flags(irq, IRQ_NOAUTOEN); - err = request_irq(irq, handler, irq_flags, "arm-pmu", - per_cpu_ptr(&cpu_armpmu, cpu)); - } else if (armpmu_count_irq_users(irq) == 0) { - err = request_percpu_irq(irq, handler, "arm-pmu", - &cpu_armpmu); - } + err = _armpmu_request_irq(irq, handler, irq_flags, cpu); + } else if (armpmu_count_irq_users(irq) == 0) + err = _armpmu_request_percpu_irq(irq, handler); if (err) goto err_out; diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 5b616dde9a4c..5b878b5a22aa 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -160,6 +160,12 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn); static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } #endif +static inline bool armpmu_support_nmi(void) +{ + return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI_PERF) && + system_uses_irq_prio_masking(); +} + /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); struct arm_pmu *armpmu_alloc_atomic(void); From patchwork Sat May 16 12:48:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lecopzer Chen X-Patchwork-Id: 11553487 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED0DB59D for ; Sat, 16 May 2020 12:50:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9B95207C3 for ; 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[61.228.240.171]) by smtp.gmail.com with ESMTPSA id k27sm3768323pgb.30.2020.05.16.05.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 May 2020 05:50:10 -0700 (PDT) From: Lecopzer Chen To: linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: perf: Support NMI context for perf event ISR Date: Sat, 16 May 2020 20:48:56 +0800 Message-Id: <20200516124857.75004-3-lecopzer@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200516124857.75004-1-lecopzer@gmail.com> References: <20200516124857.75004-1-lecopzer@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200516_055011_702507_560D08F0 X-CRM114-Status: GOOD ( 12.49 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:543 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [lecopzer[at]gmail.com] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lecopzer.chen@mediatek.com, Lecopzer Chen , alexander.shishkin@linux.intel.com, catalin.marinas@arm.com, jolsa@redhat.com, acme@kernel.org, peterz@infradead.org, mingo@redhat.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, namhyung@kernel.org, will@kernel.org, yj.chiang@mediatek.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Perf ISR doesn't support for NMI context, thus add some necessary condition-if to handle NMI context: - We should not hold pmu_lock since it may have already been acquired before NMI triggered. - irq_work should not run at NMI context. Signed-off-by: Lecopzer Chen --- arch/arm64/kernel/perf_event.c | 36 +++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4d7879484cec..94b404509f02 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -313,6 +313,23 @@ static inline bool armv8pmu_event_is_chained(struct perf_event *event) (idx != ARMV8_IDX_CYCLE_COUNTER); } +/* + * NMI Perf interrupts may be triggered during kernel holding + * same lock. + * Avoid acquiring lock again in NMI context. + */ +#define armv8pmu_lock(lock, flags) \ + do { \ + if (!in_nmi()) \ + raw_spin_lock_irqsave(lock, flags); \ + } while (0) + +#define armv8pmu_unlock(lock, flags) \ + do { \ + if (!in_nmi()) \ + raw_spin_unlock_irqrestore(lock, flags);\ + } while (0) + /* * ARMv8 low level PMU access */ @@ -589,7 +606,7 @@ static void armv8pmu_enable_event(struct perf_event *event) * Enable counter and interrupt, and set the counter to count * the event that we're interested in. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* * Disable counter @@ -611,7 +628,7 @@ static void armv8pmu_enable_event(struct perf_event *event) */ armv8pmu_enable_event_counter(event); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static void armv8pmu_disable_event(struct perf_event *event) @@ -623,7 +640,7 @@ static void armv8pmu_disable_event(struct perf_event *event) /* * Disable counter and interrupt */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* * Disable counter @@ -635,7 +652,7 @@ static void armv8pmu_disable_event(struct perf_event *event) */ armv8pmu_disable_event_irq(event); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static void armv8pmu_start(struct arm_pmu *cpu_pmu) @@ -643,10 +660,10 @@ static void armv8pmu_start(struct arm_pmu *cpu_pmu) unsigned long flags; struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* Enable all counters */ armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static void armv8pmu_stop(struct arm_pmu *cpu_pmu) @@ -654,10 +671,10 @@ static void armv8pmu_stop(struct arm_pmu *cpu_pmu) unsigned long flags; struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* Disable all counters */ armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) @@ -722,7 +739,8 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) * platforms that can have the PMU interrupts raised as an NMI, this * will not work. */ - irq_work_run(); + if (!armpmu_support_nmi()) + irq_work_run(); return IRQ_HANDLED; } From patchwork Sat May 16 12:48:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lecopzer Chen X-Patchwork-Id: 11553491 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6512859D for ; Sat, 16 May 2020 12:51:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 430B320671 for ; Sat, 16 May 2020 12:51:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Z7/z5Eg9"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SqOx1Fs0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 430B320671 Authentication-Results: mail.kernel.org; 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[61.228.240.171]) by smtp.gmail.com with ESMTPSA id k27sm3768323pgb.30.2020.05.16.05.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 May 2020 05:50:14 -0700 (PDT) From: Lecopzer Chen To: linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: Kconfig: Add support for the Perf NMI Date: Sat, 16 May 2020 20:48:57 +0800 Message-Id: <20200516124857.75004-4-lecopzer@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200516124857.75004-1-lecopzer@gmail.com> References: <20200516124857.75004-1-lecopzer@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200516_055016_145227_DAA9CDC6 X-CRM114-Status: GOOD ( 10.27 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [lecopzer[at]gmail.com] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lecopzer.chen@mediatek.com, Lecopzer Chen , alexander.shishkin@linux.intel.com, catalin.marinas@arm.com, jolsa@redhat.com, acme@kernel.org, peterz@infradead.org, mingo@redhat.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, namhyung@kernel.org, will@kernel.org, yj.chiang@mediatek.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This is an extending function for Pseudo NMI that registering Perf events interrupts as NMI. It's helpful for sampling irq-off context when using perf. Signed-off-by: Lecopzer Chen --- arch/arm64/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 40fb05d96c60..f89c169771a0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1679,6 +1679,16 @@ config ARM64_PSEUDO_NMI If unsure, say N if ARM64_PSEUDO_NMI +config ARM64_PSEUDO_NMI_PERF + bool "Register Perf interrupts as Pseudo NMI" + depends on HW_PERF_EVENTS + depends on ARM_PMU + select HAVE_PERF_EVENTS_NMI + help + This registers Perf interrupts to NMI when Pseudo NMI is active. + This option is helpful when you need to debug any context disabled + irq and get more inforamtion. + + If unsure, say N + config ARM64_DEBUG_PRIORITY_MASKING bool "Debug interrupt priority masking" help