From patchwork Thu May 21 11:23:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 11562749 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 682FD60D for ; Thu, 21 May 2020 11:24:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B2552083E for ; Thu, 21 May 2020 11:24:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728414AbgEULYU (ORCPT ); Thu, 21 May 2020 07:24:20 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:47468 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728887AbgEULYU (ORCPT ); Thu, 21 May 2020 07:24:20 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id F079B301C4E315FE73B4; Thu, 21 May 2020 19:24:17 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 21 May 2020 19:24:07 +0800 From: Yicong Yang To: , , , CC: , , , Subject: [RFC PATCH 1/3] spi: spi-mem: add optional prepare/unprepare methods in spi_controller_mem_ops Date: Thu, 21 May 2020 19:23:49 +0800 Message-ID: <1590060231-23242-2-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1590060231-23242-1-git-send-email-yangyicong@hisilicon.com> References: <1590060231-23242-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Some prepare/unprepare works may be necessary before/after a set of operations of the spimem device. For example, before/after spi-nor flash's read/write/erase/lock/unlock. Add optional prepare/unprepare methods in spi_controller_mem_ops to allow the controller to do specific works after/before the operations. The upper user can use spi_mem_{prepare, unprepare}() to call the methods of the controller. Signed-off-by: Yicong Yang --- drivers/spi/spi-mem.c | 20 ++++++++++++++++++++ include/linux/spi/spi-mem.h | 11 +++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index adaa0c4..f09cef1 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -220,6 +220,26 @@ bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) } EXPORT_SYMBOL_GPL(spi_mem_supports_op); +int spi_mem_prepare(struct spi_mem *mem) +{ + struct spi_controller *ctlr = mem->spi->controller; + + if (ctlr->mem_ops && ctlr->mem_ops->prepare) + return ctlr->mem_ops->prepare(mem); + + return 0; +} +EXPORT_SYMBOL_GPL(spi_mem_prepare); + +void spi_mem_unprepare(struct spi_mem *mem) +{ + struct spi_controller *ctlr = mem->spi->controller; + + if (ctlr->mem_ops && ctlr->mem_ops->unprepare) + ctlr->mem_ops->unprepare(mem); +} +EXPORT_SYMBOL_GPL(spi_mem_unprepare); + static int spi_mem_access_start(struct spi_mem *mem) { struct spi_controller *ctlr = mem->spi->controller; diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index af9ff2f..e40b5c3 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -215,6 +215,12 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem) * limitations) * @supports_op: check if an operation is supported by the controller * @exec_op: execute a SPI memory operation + * @prepare: do some prepare works before a set of operations. for example, + * read/write/erase/lock/unlock operations of spi-nor flash. This + * method is optional. + * @unprepare: do some post works after a set of operations. for example, + * read/write/erase/lock/unlock operations of spi-nor flash. This + * method is optional. * @get_name: get a custom name for the SPI mem device from the controller. * This might be needed if the controller driver has been ported * to use the SPI mem layer and a custom name is used to keep @@ -253,6 +259,8 @@ struct spi_controller_mem_ops { int (*adjust_op_size)(struct spi_mem *mem, struct spi_mem_op *op); bool (*supports_op)(struct spi_mem *mem, const struct spi_mem_op *op); + int (*prepare)(struct spi_mem *mem); + void (*unprepare)(struct spi_mem *mem); int (*exec_op)(struct spi_mem *mem, const struct spi_mem_op *op); const char *(*get_name)(struct spi_mem *mem); @@ -329,6 +337,9 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); +int spi_mem_prepare(struct spi_mem *mem); +void spi_mem_unprepare(struct spi_mem *mem); + int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op); From patchwork Thu May 21 11:23:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 11562751 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FE1760D for ; Thu, 21 May 2020 11:24:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42690207FB for ; Thu, 21 May 2020 11:24:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728887AbgEULYV (ORCPT ); Thu, 21 May 2020 07:24:21 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:47478 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728922AbgEULYU (ORCPT ); Thu, 21 May 2020 07:24:20 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 0389779028A765082C68; Thu, 21 May 2020 19:24:18 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 21 May 2020 19:24:07 +0800 From: Yicong Yang To: , , , CC: , , , Subject: [RFC PATCH 2/3] mtd: spi-nor: Add prepare/unprepare support for spimem device Date: Thu, 21 May 2020 19:23:50 +0800 Message-ID: <1590060231-23242-3-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1590060231-23242-1-git-send-email-yangyicong@hisilicon.com> References: <1590060231-23242-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org spi-nor flash's read/write/erase/lock/unlock may be composed of a set of operations, and some prepare/unprepare works need to be done before/ after these operations in spi_nor_{lock, unlock}_and_{prep, unprep}(). Previously we only call spi-nor controllers' prepare/unprepare method in the functions, without spimem devices'. Add spimem devices' prepare/unprepare support. Call spi_mem_{prepare, unprepare}() function if it's a spimem device. Signed-off-by: Yicong Yang --- drivers/mtd/spi-nor/core.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index cc68ea8..3a7e40a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1103,7 +1103,9 @@ int spi_nor_lock_and_prep(struct spi_nor *nor) mutex_lock(&nor->lock); - if (nor->controller_ops && nor->controller_ops->prepare) { + if (nor->spimem) { + ret = spi_mem_prepare(nor->spimem); + } else if (nor->controller_ops && nor->controller_ops->prepare) { ret = nor->controller_ops->prepare(nor); if (ret) { mutex_unlock(&nor->lock); @@ -1115,7 +1117,9 @@ int spi_nor_lock_and_prep(struct spi_nor *nor) void spi_nor_unlock_and_unprep(struct spi_nor *nor) { - if (nor->controller_ops && nor->controller_ops->unprepare) + if (nor->spimem) + spi_mem_unprepare(nor->spimem); + else if (nor->controller_ops && nor->controller_ops->unprepare) nor->controller_ops->unprepare(nor); mutex_unlock(&nor->lock); } From patchwork Thu May 21 11:23:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 11562747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 572C690 for ; Thu, 21 May 2020 11:24:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48FB2207FB for ; Thu, 21 May 2020 11:24:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729040AbgEULYU (ORCPT ); Thu, 21 May 2020 07:24:20 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:47490 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728414AbgEULYT (ORCPT ); Thu, 21 May 2020 07:24:19 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 09BDBD8DE7A7168C8D15; Thu, 21 May 2020 19:24:18 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 21 May 2020 19:24:08 +0800 From: Yicong Yang To: , , , CC: , , , Subject: [RFC PATCH 3/3] spi: hisi-sfc-v3xx: Add prepare/unprepare methods to avoid race condition Date: Thu, 21 May 2020 19:23:51 +0800 Message-ID: <1590060231-23242-4-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1590060231-23242-1-git-send-email-yangyicong@hisilicon.com> References: <1590060231-23242-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The controller can be shared with the firmware, which may cause race problems. As most read/write/erase/lock/unlock of spi-nor flash are composed of a set of operations, while the firmware may use the controller and start its own operation in the middle of the process started by the kernel driver, which may lead to the kernel driver's function broken. Bit[20] in HISI_SFC_V3XX_CMD_CFG register plays a role of a lock, to protect the controller from firmware access, which means the firmware cannot reach the controller if the driver set the bit. Add prepare/ unprepare methods for the controller, we'll hold the lock in prepare method and release it in unprepare method, which will solve the race issue. Signed-off-by: Yicong Yang --- drivers/spi/spi-hisi-sfc-v3xx.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c index e3b5725..13c161c 100644 --- a/drivers/spi/spi-hisi-sfc-v3xx.c +++ b/drivers/spi/spi-hisi-sfc-v3xx.c @@ -18,6 +18,7 @@ #define HISI_SFC_V3XX_VERSION (0x1f8) #define HISI_SFC_V3XX_CMD_CFG (0x300) +#define HISI_SFC_V3XX_CMD_CFG_LOCK BIT(20) #define HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT (1 << 17) #define HISI_SFC_V3XX_CMD_CFG_DUAL_IO (2 << 17) #define HISI_SFC_V3XX_CMD_CFG_FULL_DIO (3 << 17) @@ -41,6 +42,34 @@ struct hisi_sfc_v3xx_host { int max_cmd_dword; }; +int hisi_sfc_v3xx_op_prepare(struct spi_mem *mem) +{ + struct spi_device *spi = mem->spi; + struct hisi_sfc_v3xx_host *host; + u32 reg = HISI_SFC_V3XX_CMD_CFG_LOCK; + + host = spi_controller_get_devdata(spi->master); + + writel(reg, host->regbase + HISI_SFC_V3XX_CMD_CFG); + + reg = readl(host->regbase + HISI_SFC_V3XX_CMD_CFG); + if (!(reg & HISI_SFC_V3XX_CMD_CFG_LOCK)) + return -EIO; + + return 0; +} + +void hisi_sfc_v3xx_op_unprepare(struct spi_mem *mem) +{ + struct spi_device *spi = mem->spi; + struct hisi_sfc_v3xx_host *host; + + host = spi_controller_get_devdata(spi->master); + + /* Release the lock and clear the command register. */ + writel(0, host->regbase + HISI_SFC_V3XX_CMD_CFG); +} + #define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000 #define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10 @@ -163,7 +192,15 @@ static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host, u8 chip_select) { int ret, len = op->data.nbytes; - u32 config = 0; + u32 config; + + /* + * The lock bit is in the command register. Clear the command + * field with lock bit held if it has been set in + * .prepare(). + */ + config = readl(host->regbase + HISI_SFC_V3XX_CMD_CFG); + config &= HISI_SFC_V3XX_CMD_CFG_LOCK; if (op->addr.nbytes) config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK; @@ -248,6 +285,8 @@ static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem, static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = { .adjust_op_size = hisi_sfc_v3xx_adjust_op_size, + .prepare = hisi_sfc_v3xx_op_prepare, + .unprepare = hisi_sfc_v3xx_op_unprepare, .exec_op = hisi_sfc_v3xx_exec_op, };