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Mon, 25 May 2020 00:12:37 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 1/9] irqchip/sun6i-r: Use a stacked irqchip driver Date: Sun, 24 May 2020 23:12:54 -0500 Message-Id: <20200525041302.51213-2-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211239_307856_B315A267 X-CRM114-Status: GOOD ( 23.34 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the original sun4i interrupt controller than the sun7i/sun9i NMI controller. It is used for two distinct purposes: 1) To control the trigger, latch, and mask for the NMI input pin 2) To provide the interrupt input for the ARISC coprocessor As this interrupt controller is not documented, information about it comes from vendor-provided ARISC firmware and from experimentation. Like the original sun4i interrupt controller, it has: - A VECTOR_REG at 0x00 (configurable via the BASE_ADDR_REG at 0x04) - A NMI_CTRL_REG, PENDING_REG, and ENABLE_REG as used by both the sun4i and sunxi-nmi drivers - A MASK_REG at 0x50 - A RESP_REG at 0x60 Differences from the sun4i interrupt controller appear to be: - It is only known to have one register of each kind (max 32 inputs) - There is no FIQ-related logic - There is no interrupt priority logic In order to fulfill its two purposes, this hardware block combines two types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0 pending" output from this chip, if enabled, is then routed to a SPI IRQ input on the GIC, as IRQ_TYPE_LEVEL_HIGH. In other words, bit 0 of ENABLE_REG *does* affect the NMI IRQ seen at the GIC. The NMI is then followed by a contiguous block of (at least) 15 IRQ inputs that are connected in parallel to both R_INTC and the GIC. Or in other words, the other bits of ENABLE_REG *do not* affect the IRQs seen at the GIC. Finally, the global "IRQ pending" output from R_INTC, after being masked by MASK_REG and RESP_REG, is connected to the "external interrupt" input of the ARISC CPU (an OR1200). This path is not relevant to Linux. Because of the 1:1 correspondence between R_INTC and GIC inputs, this is a perfect scenario for using a stacked irqchip driver. We want to hook into enabling/disabling IRQs to add more features to the GIC (specifically to allow masking the NMI and setting its trigger type), but we don't need to actually handle the IRQ in this driver. And since R_INTC is in the always-on power domain, and its output is connected directly in to the power management coprocessor, a stacked irqchip driver provides a simple way to add wakeup support to this set of IRQs. That is a future patch; for now, just the NMI is moved over. This driver keeps the same DT binding as the existing driver. The "interrupt" property of the R_INTC node is used to determine 1) the offset between GIC and R_INTC hwirq numbers and 2) the type of trigger between the R_INTC "IRQ 0 pending" output and the GIC NMI input. This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi: Support sun6i-a31-r-intc compatible"). Signed-off-by: Samuel Holland Acked-by: Maxime Ripard --- arch/arm/mach-sunxi/Kconfig | 4 + arch/arm64/Kconfig.platforms | 2 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sun6i-r.c | 216 ++++++++++++++++++++++++++++++++ drivers/irqchip/irq-sunxi-nmi.c | 26 +--- 5 files changed, 226 insertions(+), 23 deletions(-) create mode 100644 drivers/irqchip/irq-sun6i-r.c diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index eeadb1a4dcfe..216b5954d6a9 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -30,6 +30,8 @@ config MACH_SUN6I bool "Allwinner A31 (sun6i) SoCs support" default ARCH_SUNXI select ARM_GIC + select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS select MFD_SUN6I_PRCM select SUN5I_HSTIMER @@ -46,6 +48,8 @@ config MACH_SUN8I bool "Allwinner sun8i Family SoCs support" default ARCH_SUNXI select ARM_GIC + select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS select MFD_SUN6I_PRCM config MACH_SUN9I diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 55d70cfe0f9e..b9c3a7118a2c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -17,6 +17,8 @@ config ARCH_SUNXI bool "Allwinner sunxi 64-bit SoC Family" select ARCH_HAS_RESET_CONTROLLER select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS select PINCTRL select RESET_CONTROLLER help diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 37bbe39bf909..c9692bdaabfa 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o +obj-$(CONFIG_ARCH_SUNXI) += irq-sun6i-r.o obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c new file mode 100644 index 000000000000..f8bfa5515f20 --- /dev/null +++ b/drivers/irqchip/irq-sun6i-r.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Allwinner A31 and newer SoCs R_INTC driver +// + +#include +#include +#include +#include +#include +#include + +#include + +#define NMI_HWIRQ 0 +#define NMI_HWIRQ_BIT BIT(NMI_HWIRQ) + +#define SUN6I_R_INTC_NR_IRQS 16 + +#define SUN6I_R_INTC_NMI_CTRL 0x0c +#define SUN6I_R_INTC_PENDING 0x10 +#define SUN6I_R_INTC_ENABLE 0x40 + +static void __iomem *base; +static irq_hw_number_t parent_offset; +static u32 parent_type; + +static struct irq_chip sun6i_r_intc_edge; +static struct irq_chip sun6i_r_intc_level; + +static void sun6i_r_intc_nmi_ack(void) +{ + /* + * The NMI IRQ channel has a latch, separate from its trigger. + * This latch must be cleared to clear the output to the GIC. + */ + writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_PENDING); +} + +static void sun6i_r_intc_irq_ack(struct irq_data *data) +{ + if (data->hwirq == NMI_HWIRQ) + sun6i_r_intc_nmi_ack(); +} + +static void sun6i_r_intc_irq_eoi(struct irq_data *data) +{ + if (data->hwirq == NMI_HWIRQ) + sun6i_r_intc_nmi_ack(); + + irq_chip_eoi_parent(data); +} + +static int sun6i_r_intc_irq_set_type(struct irq_data *data, unsigned int type) +{ + /* + * Only the NMI IRQ is routed through this interrupt controller on its + * way to the GIC. Other IRQs are routed to the GIC in parallel and + * must have a trigger type appropriate for the GIC. + * + * The "External NMI" input to the GIC actually comes from bit 0 of + * this device's PENDING register. So the IRQ type of the NMI, as seen + * by the GIC, does not depend on the IRQ type of the NMI pin itself. + */ + if (data->hwirq == NMI_HWIRQ) { + u32 nmi_src_type; + + switch (type) { + case IRQ_TYPE_LEVEL_LOW: + nmi_src_type = 0; + break; + case IRQ_TYPE_EDGE_FALLING: + nmi_src_type = 1; + break; + case IRQ_TYPE_LEVEL_HIGH: + nmi_src_type = 2; + break; + case IRQ_TYPE_EDGE_RISING: + nmi_src_type = 3; + break; + default: + pr_err("%pOF: invalid trigger type %d for IRQ %d\n", + irq_domain_get_of_node(data->domain), type, + data->irq); + return -EBADR; + } + + if (type & IRQ_TYPE_EDGE_BOTH) { + irq_set_chip_handler_name_locked(data, + &sun6i_r_intc_edge, + handle_fasteoi_ack_irq, + NULL); + } else { + irq_set_chip_handler_name_locked(data, + &sun6i_r_intc_level, + handle_fasteoi_irq, + NULL); + } + + writel_relaxed(nmi_src_type, base + SUN6I_R_INTC_NMI_CTRL); + + /* Send the R_INTC -> GIC trigger type to the GIC driver. */ + type = parent_type; + } + + return irq_chip_set_type_parent(data, type); +} + +static struct irq_chip sun6i_r_intc_edge = { + .name = "sun6i-r-intc", + .irq_ack = sun6i_r_intc_irq_ack, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_type = sun6i_r_intc_irq_set_type, + .irq_get_irqchip_state = irq_chip_get_parent_state, + .irq_set_irqchip_state = irq_chip_set_parent_state, + .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, + .flags = IRQCHIP_SET_TYPE_MASKED, +}; + +static struct irq_chip sun6i_r_intc_level = { + .name = "sun6i-r-intc", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = sun6i_r_intc_irq_eoi, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_type = sun6i_r_intc_irq_set_type, + .irq_get_irqchip_state = irq_chip_get_parent_state, + .irq_set_irqchip_state = irq_chip_set_parent_state, + .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_EOI_THREADED, +}; + +static int sun6i_r_intc_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct irq_fwspec *fwspec = arg; + struct irq_fwspec gic_fwspec; + irq_hw_number_t hwirq; + unsigned int type; + int i, ret; + + ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + if (hwirq + nr_irqs > SUN6I_R_INTC_NR_IRQS) + return -EINVAL; + + /* Construct a GIC-compatible fwspec from this fwspec. */ + gic_fwspec = (struct irq_fwspec) { + .fwnode = domain->parent->fwnode, + .param_count = 3, + .param = { GIC_SPI, parent_offset + hwirq, type }, + }; + + for (i = 0; i < nr_irqs; ++i) + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &sun6i_r_intc_level, NULL); + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec); +} + +static const struct irq_domain_ops sun6i_r_intc_domain_ops = { + .translate = irq_domain_translate_twocell, + .alloc = sun6i_r_intc_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int __init sun6i_r_intc_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *domain, *parent_domain; + struct of_phandle_args parent_irq; + int ret; + + /* Extract the R_INTC -> GIC mapping from the OF node. */ + ret = of_irq_parse_one(node, 0, &parent_irq); + if (ret) + return ret; + if (parent_irq.args_count != 3 || parent_irq.args[0] != GIC_SPI) + return -EINVAL; + parent_offset = parent_irq.args[1]; + parent_type = parent_irq.args[2]; + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%pOF: Failed to obtain parent domain\n", node); + return -ENXIO; + } + + base = of_io_request_and_map(node, 0, NULL); + if (IS_ERR(base)) { + pr_err("%pOF: Failed to map MMIO region\n", node); + return PTR_ERR(base); + } + + domain = irq_domain_add_hierarchy(parent_domain, 0, + SUN6I_R_INTC_NR_IRQS, node, + &sun6i_r_intc_domain_ops, NULL); + if (!domain) { + pr_err("%pOF: Failed to allocate domain\n", node); + iounmap(base); + return -ENOMEM; + } + + /* Clear and enable the NMI. */ + writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_PENDING); + writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_ENABLE); + + return 0; +} +IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init); diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c index a412b5d5d0fa..9f2bd0c5d289 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -27,18 +27,12 @@ #define SUNXI_NMI_IRQ_BIT BIT(0) -#define SUN6I_R_INTC_CTRL 0x0c -#define SUN6I_R_INTC_PENDING 0x10 -#define SUN6I_R_INTC_ENABLE 0x40 - /* * For deprecated sun6i-a31-sc-nmi compatible. - * Registers are offset by 0x0c. */ -#define SUN6I_R_INTC_NMI_OFFSET 0x0c -#define SUN6I_NMI_CTRL (SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET) -#define SUN6I_NMI_PENDING (SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET) -#define SUN6I_NMI_ENABLE (SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET) +#define SUN6I_NMI_CTRL 0x00 +#define SUN6I_NMI_PENDING 0x04 +#define SUN6I_NMI_ENABLE 0x34 #define SUN7I_NMI_CTRL 0x00 #define SUN7I_NMI_PENDING 0x04 @@ -61,12 +55,6 @@ struct sunxi_sc_nmi_reg_offs { u32 enable; }; -static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = { - .ctrl = SUN6I_R_INTC_CTRL, - .pend = SUN6I_R_INTC_PENDING, - .enable = SUN6I_R_INTC_ENABLE, -}; - static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = { .ctrl = SUN6I_NMI_CTRL, .pend = SUN6I_NMI_PENDING, @@ -232,14 +220,6 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node, return ret; } -static int __init sun6i_r_intc_irq_init(struct device_node *node, - struct device_node *parent) -{ - return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs); -} -IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", - sun6i_r_intc_irq_init); - static int __init sun6i_sc_nmi_irq_init(struct device_node *node, struct device_node *parent) { From patchwork Mon May 25 04:12:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11568057 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2EDD13B4 for ; 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Mon, 25 May 2020 00:12:38 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 2/9] irqchip/sun6i-r: Add wakeup support Date: Sun, 24 May 2020 23:12:55 -0500 Message-Id: <20200525041302.51213-3-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211239_824753_0029029B X-CRM114-Status: GOOD ( 13.92 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Maintain a mask of wake-enabled IRQs, and enable them in hardware during the syscore phase of suspend. The restore the original mask of enabled IRQs (just the NMI) during resume. This serves two purposes. First, it lets power management firmware running on the ARISC coprocessor know which wakeup sources Linux wants to have enabled. That way, it can avoid turning them off when it shuts down the remainder of the clock tree. Second, it preconfigures the coprocessor's interrupt controller, so the firmware's wakeup logic is as simple as waiting for an interrupt to arrive. Signed-off-by: Samuel Holland Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun6i-r.c | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c index f8bfa5515f20..a5deea92057f 100644 --- a/drivers/irqchip/irq-sun6i-r.c +++ b/drivers/irqchip/irq-sun6i-r.c @@ -3,12 +3,14 @@ // Allwinner A31 and newer SoCs R_INTC driver // +#include #include #include #include #include #include #include +#include #include @@ -24,6 +26,9 @@ static void __iomem *base; static irq_hw_number_t parent_offset; static u32 parent_type; +#ifdef CONFIG_PM_SLEEP +static atomic_t wake_mask; +#endif static struct irq_chip sun6i_r_intc_edge; static struct irq_chip sun6i_r_intc_level; @@ -106,6 +111,20 @@ static int sun6i_r_intc_irq_set_type(struct irq_data *data, unsigned int type) return irq_chip_set_type_parent(data, type); } +#ifdef CONFIG_PM_SLEEP +static int sun6i_r_intc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + if (on) + atomic_or(BIT(data->hwirq), &wake_mask); + else + atomic_andnot(BIT(data->hwirq), &wake_mask); + + return 0; +} +#else +#define sun6i_r_intc_irq_set_wake NULL +#endif + static struct irq_chip sun6i_r_intc_edge = { .name = "sun6i-r-intc", .irq_ack = sun6i_r_intc_irq_ack, @@ -116,6 +135,7 @@ static struct irq_chip sun6i_r_intc_edge = { .irq_set_type = sun6i_r_intc_irq_set_type, .irq_get_irqchip_state = irq_chip_get_parent_state, .irq_set_irqchip_state = irq_chip_set_parent_state, + .irq_set_wake = sun6i_r_intc_irq_set_wake, .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, .flags = IRQCHIP_SET_TYPE_MASKED, }; @@ -129,6 +149,7 @@ static struct irq_chip sun6i_r_intc_level = { .irq_set_type = sun6i_r_intc_irq_set_type, .irq_get_irqchip_state = irq_chip_get_parent_state, .irq_set_irqchip_state = irq_chip_set_parent_state, + .irq_set_wake = sun6i_r_intc_irq_set_wake, .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_EOI_THREADED, @@ -170,6 +191,34 @@ static const struct irq_domain_ops sun6i_r_intc_domain_ops = { .free = irq_domain_free_irqs_common, }; +#ifdef CONFIG_PM_SLEEP +static int sun6i_r_intc_suspend(void) +{ + /* All wake IRQs are enabled during system sleep. */ + writel_relaxed(atomic_read(&wake_mask), base + SUN6I_R_INTC_ENABLE); + + return 0; +} + +static void sun6i_r_intc_resume(void) +{ + /* Only the NMI is relevant during normal operation. */ + writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_ENABLE); +} + +static struct syscore_ops sun6i_r_intc_syscore_ops = { + .suspend = sun6i_r_intc_suspend, + .resume = sun6i_r_intc_resume, +}; + +static void sun6i_r_intc_syscore_init(void) +{ + register_syscore_ops(&sun6i_r_intc_syscore_ops); +} +#else +static inline void sun6i_r_intc_syscore_init(void) {} +#endif + static int __init sun6i_r_intc_init(struct device_node *node, struct device_node *parent) { @@ -211,6 +260,8 @@ static int __init sun6i_r_intc_init(struct device_node *node, writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_PENDING); writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_ENABLE); + sun6i_r_intc_syscore_init(); + return 0; } IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init); From patchwork Mon May 25 04:12:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11568055 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9566913B4 for ; Mon, 25 May 2020 04:13:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42717204EC for ; Mon, 25 May 2020 04:13:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="jHlhuEB5"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=sholland.org header.i=@sholland.org header.b="nFR0dsSc"; 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Mon, 25 May 2020 00:12:38 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 3/9] dt-bindings: irq: Add a compatible for the H3 R_INTC Date: Sun, 24 May 2020 23:12:56 -0500 Message-Id: <20200525041302.51213-4-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211240_391996_36B492E5 X-CRM114-Status: GOOD ( 11.35 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Allwinner H3 SoC contains an R_INTC that is, as far as we know, compatible with the R_INTC present in other sun8i/sun50i SoCs starting with the A31. Since the R_INTC hardware is undocumented, introduce a new compatible for the R_INTC variant in this SoC, in case there turns out to be some difference. Signed-off-by: Samuel Holland Reviewed-by: Rob Herring --- .../allwinner,sun7i-a20-sc-nmi.yaml | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index cf09055da78b..973fe5d17af0 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -26,15 +26,13 @@ properties: - const: allwinner,sun6i-a31-sc-nmi deprecated: true - const: allwinner,sun7i-a20-sc-nmi - - items: - - const: allwinner,sun8i-a83t-r-intc - - const: allwinner,sun6i-a31-r-intc - const: allwinner,sun9i-a80-sc-nmi - items: - - const: allwinner,sun50i-a64-r-intc - - const: allwinner,sun6i-a31-r-intc - - items: - - const: allwinner,sun50i-h6-r-intc + - enum: + - allwinner,sun8i-a83t-r-intc + - allwinner,sun8i-h3-r-intc + - allwinner,sun50i-a64-r-intc + - allwinner,sun50i-h6-r-intc - const: allwinner,sun6i-a31-r-intc reg: From patchwork Mon May 25 04:12:57 2020 Content-Type: text/plain; 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Mon, 25 May 2020 00:12:39 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 4/9] ARM: dts: sunxi: h3/h5: Add r_intc node Date: Sun, 24 May 2020 23:12:57 -0500 Message-Id: <20200525041302.51213-5-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211240_956260_F319CB29 X-CRM114-Status: GOOD ( 10.17 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The H3 and H5 SoCs have an additional interrupt controller in the RTC power domain that can be used to enable wakeup for certain IRQs. Add a node for it. Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 01a5df9aa71b..94f648ad1c9e 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -836,6 +836,15 @@ rtc: rtc@1f00000 { #clock-cells = <1>; }; + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-h3-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; From patchwork Mon May 25 04:12:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11568061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B48B8913 for ; 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Mon, 25 May 2020 00:12:40 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 5/9] ARM: dts: sunxi: h3/h5: Move wakeup-capable IRQs to r_intc Date: Sun, 24 May 2020 23:12:58 -0500 Message-Id: <20200525041302.51213-6-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211241_481405_FEBA4A21 X-CRM114-Status: GOOD ( 11.48 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. For the H3/H5, r_intc IRQ numbers are offset by 32 from the GIC IRQ numbers. Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 94f648ad1c9e..93e7ce60a64b 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -829,8 +829,9 @@ hdmi_phy: hdmi-phy@1ef0000 { rtc: rtc@1f00000 { /* compatible is in per SoC .dtsi file */ reg = <0x01f00000 0x400>; - interrupts = , - ; + interrupt-parent = <&r_intc>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out", "iosc"; clocks = <&osc32k>; #clock-cells = <1>; @@ -865,7 +866,8 @@ ir: ir@1f02000 { clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; resets = <&r_ccu RST_APB0_IR>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x400>; status = "disabled"; }; @@ -886,7 +888,8 @@ r_i2c: i2c@1f02400 { r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; From patchwork Mon May 25 04:12:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11568067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8A4AA913 for ; Mon, 25 May 2020 04:15:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65418207DA for ; Mon, 25 May 2020 04:15:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fV33tUk9"; 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Mon, 25 May 2020 00:12:40 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 6/9] ARM: dts: sunxi: a83t: Move wakeup-capable IRQs to r_intc Date: Sun, 24 May 2020 23:12:59 -0500 Message-Id: <20200525041302.51213-7-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211242_039529_282D3DAB X-CRM114-Status: GOOD ( 11.96 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. For the A83T, r_intc IRQ numbers are offset by 32 from the GIC IRQ numbers. Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 655404d6d3a3..fcfc573eb96d 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1130,7 +1130,8 @@ r_cir: ir@1f02000 { clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; resets = <&r_ccu RST_APB0_IR>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x400>; pinctrl-names = "default"; pinctrl-0 = <&r_cir_pin>; @@ -1140,14 +1141,16 @@ r_cir: ir@1f02000 { r_lradc: lradc@1f03c00 { compatible = "allwinner,sun8i-a83t-r-lradc"; reg = <0x01f03c00 0x100>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a83t-r-pinctrl"; reg = <0x01f02c00 0x400>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc16Md512>; clock-names = "apb", "hosc", "losc"; From patchwork Mon May 25 04:13:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11568065 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DBAC4912 for ; Mon, 25 May 2020 04:15:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A58EA207DA for ; Mon, 25 May 2020 04:15:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hhZMuG8q"; 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Mon, 25 May 2020 00:12:41 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 7/9] arm64: dts: allwinner: a64: Move wakeup-capable IRQs to r_intc Date: Sun, 24 May 2020 23:13:00 -0500 Message-Id: <20200525041302.51213-8-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211242_885322_DF4C5792 X-CRM114-Status: GOOD ( 11.50 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. For the A64, r_intc IRQ numbers are offset by 32 from the GIC IRQ numbers. Signed-off-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index c26cc1fcaffd..33f2ce0d93aa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1176,8 +1176,9 @@ rtc: rtc@1f00000 { compatible = "allwinner,sun50i-a64-rtc", "allwinner,sun8i-h3-rtc"; reg = <0x01f00000 0x400>; - interrupts = , - ; + interrupt-parent = <&r_intc>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out", "iosc"; clocks = <&osc32k>; #clock-cells = <1>; @@ -1227,7 +1228,8 @@ r_ir: ir@1f02000 { clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; resets = <&r_ccu RST_APB0_IR>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&r_ir_rx_pin>; status = "disabled"; @@ -1247,7 +1249,8 @@ r_pwm: pwm@1f03800 { r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; From patchwork Mon May 25 04:13:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11568069 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 98D0F913 for ; Mon, 25 May 2020 04:15:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 76DB2207DA for ; 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Mon, 25 May 2020 00:12:41 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 8/9] arm64: dts: allwinner: h6: Fix indentation of IR node Date: Sun, 24 May 2020 23:13:01 -0500 Message-Id: <20200525041302.51213-9-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211243_259932_0588252D X-CRM114-Status: GOOD ( 10.68 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This node was indented by two tabs when added instead of one. Remove the extra tab. Signed-off-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index b9ab7d8fa8af..d912188dc6ea 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -901,17 +901,17 @@ r_ir_rx_pin: r-ir-rx-pin { }; r_ir: ir@7040000 { - compatible = "allwinner,sun50i-h6-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "disabled"; + compatible = "allwinner,sun50i-h6-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_R_APB1_IR>; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "disabled"; }; r_i2c: i2c@7081400 { From patchwork Mon May 25 04:13:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11568071 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7435A912 for ; Mon, 25 May 2020 04:16:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 51F25207DA for ; Mon, 25 May 2020 04:16:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="eD1VMiQq"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=sholland.org header.i=@sholland.org header.b="Yl7IF+bM"; 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Mon, 25 May 2020 00:12:42 -0400 (EDT) From: Samuel Holland To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Russell King , Catalin Marinas , Will Deacon Subject: [PATCH v2 9/9] arm64: dts: allwinner: h6: Move wakeup-capable IRQs to r_intc Date: Sun, 24 May 2020 23:13:02 -0500 Message-Id: <20200525041302.51213-10-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200525041302.51213-1-samuel@sholland.org> References: <20200525041302.51213-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_211243_747755_E6F7DDFE X-CRM114-Status: GOOD ( 11.13 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.221 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. For the H6, r_intc IRQ numbers are offset by 96 from the GIC IRQ numbers. Signed-off-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index d912188dc6ea..188699f47dea 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -844,8 +844,9 @@ tcon_tv_out_tcon_top: endpoint@1 { rtc: rtc@7000000 { compatible = "allwinner,sun50i-h6-rtc"; reg = <0x07000000 0x400>; - interrupts = , - ; + interrupt-parent = <&r_intc>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, + <6 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out", "iosc"; #clock-cells = <1>; }; @@ -880,8 +881,9 @@ r_intc: interrupt-controller@7021000 { r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h6-r-pinctrl"; reg = <0x07022000 0x400>; - interrupts = , - ; + interrupt-parent = <&r_intc>; + interrupts = < 9 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; @@ -904,7 +906,8 @@ r_ir: ir@7040000 { compatible = "allwinner,sun50i-h6-ir", "allwinner,sun6i-a31-ir"; reg = <0x07040000 0x400>; - interrupts = ; + interrupt-parent = <&r_intc>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB1_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir";