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[91.76.17.204]) by smtp.gmail.com with ESMTPSA id y130sm241192lfc.22.2020.05.26.13.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2020 13:58:23 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding Subject: [PATCH v1] drm/tegra: gr2d: Add tiled PATBASE address register Date: Tue, 26 May 2020 23:57:53 +0300 Message-Id: <20200526205753.14423-1-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 27 May 2020 07:15:42 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There are two PATBASE address registers, one for linear layout and other for tiled. The driver's address registers list misses the tiled PATBASE register. Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/gr2d.c | 1 + drivers/gpu/drm/tegra/gr2d.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c index 48363f744bb9..1a0d3ba6e525 100644 --- a/drivers/gpu/drm/tegra/gr2d.c +++ b/drivers/gpu/drm/tegra/gr2d.c @@ -177,6 +177,7 @@ static const u32 gr2d_addr_regs[] = { GR2D_DSTC_BASE_ADDR, GR2D_SRCA_BASE_ADDR, GR2D_SRCB_BASE_ADDR, + GR2D_PATBASE_ADDR, GR2D_SRC_BASE_ADDR_SB, GR2D_DSTA_BASE_ADDR_SB, GR2D_DSTB_BASE_ADDR_SB, diff --git a/drivers/gpu/drm/tegra/gr2d.h b/drivers/gpu/drm/tegra/gr2d.h index 2398486f0699..9b7d66e15b9f 100644 --- a/drivers/gpu/drm/tegra/gr2d.h +++ b/drivers/gpu/drm/tegra/gr2d.h @@ -14,6 +14,7 @@ #define GR2D_DSTC_BASE_ADDR 0x2d #define GR2D_SRCA_BASE_ADDR 0x31 #define GR2D_SRCB_BASE_ADDR 0x32 +#define GR2D_PATBASE_ADDR 0x47 #define GR2D_SRC_BASE_ADDR_SB 0x48 #define GR2D_DSTA_BASE_ADDR_SB 0x49 #define GR2D_DSTB_BASE_ADDR_SB 0x4a