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Thu, 11 Oct 2018 08:15:40 +0000 Received: from VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123]) by VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123%3]) with mapi id 15.20.1207.024; Thu, 11 Oct 2018 08:15:40 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "linux-spi@vger.kernel.org" , "tudor.ambarus@microchip.com" CC: "marek.vasut@gmail.com" , "cyrille.pitchen@wedev4u.fr" , "boris.brezillon@bootlin.com" , "computersforpeace@gmail.com" , "frieder.schrempf@exceet.de" , "linux-kernel@vger.kernel.org" , Yogesh Narayan Gaur Subject: [PATCH v2 1/2] mtd: spi-nor: add macros related to MICRON flash Thread-Topic: [PATCH v2 1/2] mtd: spi-nor: add macros related to MICRON flash Thread-Index: AQHUYTqZJSSqGPTqb0+Lq8HmDDDYbQ== Date: Thu, 11 Oct 2018 08:15:40 +0000 Message-ID: <1539245630-26611-2-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1539245630-26611-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1539245630-26611-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR06CA0088.apcprd06.prod.outlook.com (2603:1096:3:14::14) To VI1PR04MB1038.eurprd04.prod.outlook.com (2a01:111:e400:5092::16) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [14.143.30.134] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;VI1PR04MB1294;6:SQUeJRr5vcWC3tp564RX2u77kaCkg2VGI0KBiiaXGo2pH3ySLtnTrOiFp+UX+sywYs2m1ECbYZvwDfl5ail4PXlpeeKoSnVW5qlFrJc5xYOg+gSlJimC5mcDvsFInfcg0cCv0RWVVLIRgYc/XLRtTKKlnf3AL90DnHRJpdm4YZYfmwkNuOQAZXXrpEv6DnT+eOGeyORwJmfUC8crGnUWwhZTLeyATy382hqJ1vjJUW69YZJ2EinAlDKb9+ZqGUPRId2XJKdE564fbxbvGHPB03Bv/f9ylaeMCZaKxwY05a1BUt7lfoV3vTwV4OH+po2nsstU7pVPw8URymGYqGhuqglBJuQViIvWl4qDKyPSU95+bjolZ3OyGOFmCrDKAwZvOZarhZWI6T362iuuN+UGh04VqHw+yXctezbFgg5yjRJ2WgA5jXGfvbn5RqpQ73wUwniK2/aJN5L83xtceDVRWQ==;5:3r4tSmzQX6B4oVk6IPNOPVZwj9Y05Nd2fCfLoguLwnduREF4xSbsUcK/nEQmNnm+TPkG0MChEzkADp7u3hWO8wn8w+R95zkPXg5AMw4px5eYIVX1xs1Seq1sQghv/QjthBUo9K9mcBIOHi9ZSmpG0wQUqcRtwOSSZ7AUy/++vBc=;7:e2dqeo/fOu3KS+USMCqnBuZ+40V4RcxPwNCeQ8Rw8q5Y5JgkchpOaaOFQgdqma/AplwtNIbGJlTtpxkjnEnKk+UXtOVZ9gnVbCTponC9AV3oIoGktdBOEcWwcE2rG+qO2YrpcNIfJC76ZZLfiMexuIxceEW9v39pcjOuDjTTtq5dWSQcyh3e3bdFAcYAqLuysDy1T/khPOgCUZMZUWqzvXEdVXRBRP0UkKDy7+c9zkAMxAAsKSMOHPs5PlpzJst3 x-ms-office365-filtering-correlation-id: de07ccf0-3790-4801-31eb-08d62f51bb2b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:VI1PR04MB1294; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; x-microsoft-antispam-message-info: 1y7vIOqAMInmFz+5QNJiZiYSZpmKd29PR/fFmCD2BHTboMwMmfZYdElWO9TOyz6CT0J69tas9r4MBPZ+uHOYLb/Px/koZe13r+NS3APDj4OjQYeM/SQN0HMTpmIa4z6TPJzLKVuecOpdEV5glV160HjQ+9UwVe6hEwvsPiSWqd2dVwSdd1+Uf/6Br0Xfa6dOiECLIZ/QCvEJsZoeYMn3ESewev6sd0dSwjSf59dUeoR4MOTW2NT13cqr5Dodjh7uNSn8BaeGiaJ4mIg0FiixxdbKCTscxy++y3gZNXbI8lh2tcKNPoMC0OMqJKPjLzkDNKtcb7Ipk8qBTH2fI+/a7nbaTceSPZuwlAW6bWaPWz8= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: de07ccf0-3790-4801-31eb-08d62f51bb2b X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Oct 2018 08:15:40.6499 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1294 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some MICRON related macros in spi-nor domain were ST. Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. Added entry of MFR Id for Micron flashes, 0x002C. Signed-off-by: Yogesh Gaur Reviewed-by: Tudor Ambarus --- Changes for v2: - None drivers/mtd/spi-nor/spi-nor.c | 9 ++++++--- include/linux/mtd/cfi.h | 1 + include/linux/mtd/spi-nor.h | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 9407ca5..b8b494f 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, u8 cmd; switch (JEDEC_MFR(info)) { + case SNOR_MFR_ST: case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; @@ -1388,7 +1389,7 @@ static const struct flash_info spi_nor_ids[] = { { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, - /* Micron */ + /* Micron <--> ST Micro */ { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor, params->quad_enable = macronix_quad_enable; break; + case SNOR_MFR_ST: case SNOR_MFR_MICRON: break; @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, mtd->_resume = spi_nor_resume; /* NOR protection support for STmicro/Micron chips and similar */ - if (JEDEC_MFR(info) == SNOR_MFR_MICRON || - info->flags & SPI_NOR_HAS_LOCK) { + if (JEDEC_MFR(info) == SNOR_MFR_ST || + JEDEC_MFR(info) == SNOR_MFR_MICRON || + info->flags & SPI_NOR_HAS_LOCK) { nor->flash_lock = stm_lock; nor->flash_unlock = stm_unlock; nor->flash_is_locked = stm_is_locked; diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 9b57a9b..cbf7716 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -377,6 +377,7 @@ struct cfi_fixup { #define CFI_MFR_SHARP 0x00B0 #define CFI_MFR_SST 0x00BF #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ +#define CFI_MFR_MICRON 0x002C /* Micron */ #define CFI_MFR_TOSHIBA 0x0098 #define CFI_MFR_WINBOND 0x00DA diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 7f0c730..8b1acf6 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -23,7 +23,8 @@ #define SNOR_MFR_ATMEL CFI_MFR_ATMEL #define SNOR_MFR_GIGADEVICE 0xc8 #define SNOR_MFR_INTEL CFI_MFR_INTEL -#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ +#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ +#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST From patchwork Thu Oct 11 08:15:45 2018 Content-Type: text/plain; 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Thu, 11 Oct 2018 08:15:45 +0000 Received: from VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123]) by VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123%3]) with mapi id 15.20.1207.024; Thu, 11 Oct 2018 08:15:45 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "linux-spi@vger.kernel.org" , "tudor.ambarus@microchip.com" CC: "marek.vasut@gmail.com" , "cyrille.pitchen@wedev4u.fr" , "boris.brezillon@bootlin.com" , "computersforpeace@gmail.com" , "frieder.schrempf@exceet.de" , "linux-kernel@vger.kernel.org" , Yogesh Narayan Gaur Subject: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Thread-Topic: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Thread-Index: AQHUYTqbs6sSLLIYmE2VBnAqytu3EQ== Date: Thu, 11 Oct 2018 08:15:45 +0000 Message-ID: <1539245630-26611-3-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1539245630-26611-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1539245630-26611-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR06CA0088.apcprd06.prod.outlook.com (2603:1096:3:14::14) To VI1PR04MB1038.eurprd04.prod.outlook.com (2a01:111:e400:5092::16) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [14.143.30.134] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;VI1PR04MB1294;6:bSeWnt3t7fKb+CJuFEqJc2ICz81DZI1VFYWnirFXKhorHMn0AzzJ4NTPGW7WP+5IH5qNkAEL0rCT0AfBLGqIVEMORo0h36TxG7NXOihXNC+zt4OjqVWONVmQJLzz+TnFfY4EwSfNF9wg6UXypCRXN7C6jZ2Vq+3c6dE+m4UfBPmekfw5q2j4ZSKJzKzPU2yvgVGn9gBMZc9waw2pNiFAYI8eSzKQFjOE+Ehj6zEvC00TvSwAYbfUot94TuQqNFjuGAC3ehlrDOzWlRE295z5zIGrzzhglm6UA/j5+EYU1ZMB5g21Kllj5J0HQ5vYXe4ycEMbiFoIF2bhU2s+YTSxwsvnrd35fO9gVvjt/eItG9Ij/HhvSYrEdtNt+MYFqXTLMPsDNv0konoCfmJv8ZG+ytJpLvdYPOxeGmC5tzo7pW6JCTWjhiyLxBMYbiMW4uaZ83UBRe4OsV7+zXmrg2bc7w==;5:/sWa8uU22S5AAJJwb4/0ILqJLSBV+L9M91arb4gqa0NeeNOOb9rf7nQYKypcYGWmECHZ07m2r1lKujwUxTolI3tttYvy+HxsHHM+IrWJGUkCCvDuSr6/+vjJX0aN9Uq/rRWJFW33yS3ieJfGaSj+1+ctd5nAohkWfjghkc4VQp0=;7:EiRGkMWIl5TgdPpdln/u38vx0LlyyvFaYd3A6l3xRJrvtVw8bc7UQvnz11fNgC8aDm3aC7+/JIy8WzqvcATxDXSbzw6P8VKF+bNkSdgwbal/BdkuMqsAC5BlvFs4JdLs0W9Sgg8+TAnZ7gibkNMu7zQe6rhaB3tLxeYQWftcVCt1sm6c3UpP5L+Uv7qpc0Lr3UYtsXKc/MtBjGgKfhB+aWLlN8vbYQX4eFygauhSvgEES9bYzGUJOi1xpQLT7fA2 x-ms-office365-filtering-correlation-id: ffb787c9-9826-4ffa-884e-08d62f51be09 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:VI1PR04MB1294; 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This flash is having uniform sector erase size of 128KB, have support of FSR(flag status register), flash size is 64MB and supports 4-byte commands. Signed-off-by: Yogesh Gaur Reviewed-by: Tudor Ambarus --- Changes for v2: - Removed checkpatch warning, 80 character limit. drivers/mtd/spi-nor/spi-nor.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..e0d95ac 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = { { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + /* Micron */ + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) }, + /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },