From patchwork Fri May 29 09:23:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11578207 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE97892A for ; Fri, 29 May 2020 09:23:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96C30208A7 for ; Fri, 29 May 2020 09:23:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MUfbobrp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726519AbgE2JXQ (ORCPT ); Fri, 29 May 2020 05:23:16 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:9059 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725790AbgE2JXQ (ORCPT ); Fri, 29 May 2020 05:23:16 -0400 X-UUID: 93b4a5988c9f4d6e9b86390d1bb89a48-20200529 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uzfw9R1d1VOhip5QwrPTSrk84wKyVcP93tK5NZw6nGU=; b=MUfbobrpT7qYztbauBkf6fKsVCXZlRGY2QrZL6JkU4vH+t61Tc6JheMHNpy+4T0z/1QvwltAaVP0Ji0R2wWtMmNLH+wdWyShDdlCIt7/T+517wQJi5xxCBm44vaCwNkLaoPJWcdlWUxKq/RIdZGZpkQilKqRc7JjW1TAw5Oruoo=; X-UUID: 93b4a5988c9f4d6e9b86390d1bb89a48-20200529 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 744379384; Fri, 29 May 2020 17:23:13 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 May 2020 17:23:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 May 2020 17:23:10 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v2 1/5] scsi: ufs-mediatek: Fix imprecise waiting time for ref-clk control Date: Fri, 29 May 2020 17:23:06 +0800 Message-ID: <20200529092310.1106-2-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200529092310.1106-1-stanley.chu@mediatek.com> References: <20200529092310.1106-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Currently ref-clk control timeout is implemented by Jiffies. However jiffies is not accurate enough thus "false timeout" may happen. Use more accurate delay mechanism instead, for example, ktime. Signed-off-by: Stanley Chu Reviewed-by: Andy Teng Reviewed-by: Avri Altman --- drivers/scsi/ufs/ufs-mediatek.c | 7 ++++--- drivers/scsi/ufs/ufs-mediatek.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index d56ce8d97d4e..523ee5573921 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -120,7 +120,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); struct arm_smccc_res res; - unsigned long timeout; + ktime_t timeout, time_checked; u32 value; if (host->ref_clk_enabled == on) @@ -135,8 +135,9 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) } /* Wait for ack */ - timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS); + timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US); do { + time_checked = ktime_get(); value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL); /* Wait until ack bit equals to req bit */ @@ -144,7 +145,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) goto out; usleep_range(100, 200); - } while (time_before(jiffies, timeout)); + } while (ktime_before(time_checked, timeout)); dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value); diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index 5bbd3e9cbae2..fc42dcbfd800 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -28,7 +28,7 @@ #define REFCLK_REQUEST BIT(0) #define REFCLK_ACK BIT(1) -#define REFCLK_REQ_TIMEOUT_MS 3 +#define REFCLK_REQ_TIMEOUT_US 3000 /* * Vendor specific pre-defined parameters From patchwork Fri May 29 09:23:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11578201 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9067492A for ; Fri, 29 May 2020 09:23:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78176207D4 for ; Fri, 29 May 2020 09:23:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="uX2clnuH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726860AbgE2JX3 (ORCPT ); Fri, 29 May 2020 05:23:29 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:37427 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726487AbgE2JXR (ORCPT ); Fri, 29 May 2020 05:23:17 -0400 X-UUID: e73b78c6067148eeaebfdf9f45aa441d-20200529 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ew+RGCuaV2Y1qHcybtLqf6q5Y9tu1r8jPZYZhoV+ToI=; b=uX2clnuHFeTnEABY73ouX/22G12TdLGnSzsxsTAAl0A++gCX6UKLBna06mmK1MeiuabF6x9VCvZfkzyx7dMW4qffuWutCXtV/1FGpxfdMRzZhjKS622gF4/O3rpTqYkVr3CsdcINRgG0/1Dqo0CADBIwfOYMIr/RIrvH5/7Q8Z8=; X-UUID: e73b78c6067148eeaebfdf9f45aa441d-20200529 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1831169926; Fri, 29 May 2020 17:23:14 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 May 2020 17:23:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 May 2020 17:23:10 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v2 2/5] scsi: ufs-mediatek: Do not gate clocks if auto-hibern8 is not entered yet Date: Fri, 29 May 2020 17:23:07 +0800 Message-ID: <20200529092310.1106-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200529092310.1106-1-stanley.chu@mediatek.com> References: <20200529092310.1106-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 179AB46C744F75B7EDC9180CC11DB5285C4CC2C633C70B26C2D576272C883EEC2000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org There are some chances that link enters hibern8 lately by auto-hibern8 scheme during the clock-gating flow. Clocks shall not be gated if link is still active otherwise host or device may hang. Fix this by returning error code to the caller __ufshcd_setup_clocks() to skip gating clocks there if link is not confirmed in hibern8 state yet. Also allow some waiting time for the hibern8 state transition. Signed-off-by: Stanley Chu Reviewed-by: Andy Teng --- drivers/scsi/ufs/ufs-mediatek.c | 36 ++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 523ee5573921..3c85f5e97dea 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -178,15 +178,30 @@ static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba, host->ref_clk_ungating_wait_us = ungating_us; } -static u32 ufs_mtk_link_get_state(struct ufs_hba *hba) +int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, + unsigned long max_wait_ms) { + ktime_t timeout, time_checked; u32 val; - ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); - val = ufshcd_readl(hba, REG_UFS_PROBE); - val = val >> 28; + timeout = ktime_add_us(ktime_get(), ms_to_ktime(max_wait_ms)); + do { + time_checked = ktime_get(); + ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); + val = ufshcd_readl(hba, REG_UFS_PROBE); + val = val >> 28; + + if (val == state) + return 0; - return val; + /* Sleep for max. 200us */ + usleep_range(100, 200); + } while (ktime_before(time_checked, timeout)); + + if (val == state) + return 0; + + return -ETIMEDOUT; } /** @@ -221,10 +236,13 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, * triggered by Auto-Hibern8. */ if (!ufshcd_can_hibern8_during_gating(hba) && - ufshcd_is_auto_hibern8_enabled(hba) && - ufs_mtk_link_get_state(hba) == - VS_LINK_HIBERN8) - ufs_mtk_setup_ref_clk(hba, on); + ufshcd_is_auto_hibern8_enabled(hba)) { + ret = ufs_mtk_wait_link_state(hba, + VS_LINK_HIBERN8, + 15); + if (!ret) + ufs_mtk_setup_ref_clk(hba, on); + } } } else if (on && status == POST_CHANGE) { ret = phy_power_on(host->mphy); From patchwork Fri May 29 09:23:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11578205 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BAA514F6 for ; Fri, 29 May 2020 09:23:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 32410207D4 for ; Fri, 29 May 2020 09:23:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HEFKWHlT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726568AbgE2JXR (ORCPT ); Fri, 29 May 2020 05:23:17 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:12839 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725795AbgE2JXQ (ORCPT ); Fri, 29 May 2020 05:23:16 -0400 X-UUID: 420d9dc2520d4636ae9fc7b53231bcd0-20200529 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ckHEM7GVI4e4nimxXTABhbmcvCORVQbBj1jfInkgoAg=; b=HEFKWHlTSIeuubldwrrsmrXO91sFckAW6b3Ogl7IJpmuxDN1kgOIbNTJBVFsm7738Qc2TKXDPwrK24H2hZuPe8l4e9FsYvEhzKgqNGTXfxgIfVkS4GBM5DZ+rzJ8jmpR6fU9J35f7TKrnRqBrAQRj0FYC/BJB33nJ4f4e/Mcqqw=; X-UUID: 420d9dc2520d4636ae9fc7b53231bcd0-20200529 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 793116554; Fri, 29 May 2020 17:23:13 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 May 2020 17:23:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 May 2020 17:23:10 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v2 3/5] scsi: ufs-mediatek: Introduce low-power mode for device power supply Date: Fri, 29 May 2020 17:23:08 +0800 Message-ID: <20200529092310.1106-4-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200529092310.1106-1-stanley.chu@mediatek.com> References: <20200529092310.1106-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Allow device power supply to enter low-power mode if device will do nothing to save more power. Signed-off-by: Stanley Chu Reviewed-by: Pengshun Zhao --- drivers/scsi/ufs/ufs-mediatek.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 3c85f5e97dea..5f41b7b7db8f 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "ufshcd.h" @@ -521,6 +522,19 @@ static int ufs_mtk_link_set_lpm(struct ufs_hba *hba) return 0; } +static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm) +{ + if (!hba->vreg_info.vccq2) + return; + + if (lpm & !hba->vreg_info.vcc->enabled) + regulator_set_mode(hba->vreg_info.vccq2->reg, + REGULATOR_MODE_IDLE); + else if (!lpm) + regulator_set_mode(hba->vreg_info.vccq2->reg, + REGULATOR_MODE_NORMAL); +} + static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { int err; @@ -537,6 +551,12 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) ufshcd_set_link_off(hba); return -EAGAIN; } + /* + * Make sure no error will be returned to prevent + * ufshcd_suspend() re-enabling regulators while vreg is still + * in low-power mode. + */ + ufs_mtk_vreg_set_lpm(hba, true); } if (!ufshcd_is_link_active(hba)) @@ -554,6 +574,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) phy_power_on(host->mphy); if (ufshcd_is_link_hibern8(hba)) { + ufs_mtk_vreg_set_lpm(hba, false); err = ufs_mtk_link_set_hpm(hba); if (err) { err = ufshcd_link_recovery(hba); From patchwork Fri May 29 09:23:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11578197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04EF8912 for ; Fri, 29 May 2020 09:23:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF511207F5 for ; Fri, 29 May 2020 09:23:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GQgGtA2y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726774AbgE2JXV (ORCPT ); Fri, 29 May 2020 05:23:21 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:37427 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726644AbgE2JXS (ORCPT ); Fri, 29 May 2020 05:23:18 -0400 X-UUID: bb431eba164c4b839de1b208f8d91198-20200529 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=NOKlv7zM4LRTruut6jgdhOjKQWFJHmbjuA06RuI5wcQ=; b=GQgGtA2y+2a6srv8ldiq1g47YvQxUB5fqMKbjAE7fE7jc9Z0A920YW63wNAiBq7cCJQzGepW/zyhJbtxkTSsv8m5AIXVBa7mPrrbfENcr+XFVx28dNov42ThCTdi16+lo+cXr6V9XKbqZx5nh9euHX0i8iLYMZ7OnhaLiXzyZDQ=; X-UUID: bb431eba164c4b839de1b208f8d91198-20200529 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 47945482; Fri, 29 May 2020 17:23:14 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 May 2020 17:23:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 May 2020 17:23:10 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v2 4/5] scsi: ufs-mediatek: Fix unbalanced clock on/off Date: Fri, 29 May 2020 17:23:09 +0800 Message-ID: <20200529092310.1106-5-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200529092310.1106-1-stanley.chu@mediatek.com> References: <20200529092310.1106-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 83DAA400323415FEC60197EA0FAEFFA75DFAD431B49159932AD28C3CD9C819842000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org MediaTek UFS clocks are separated to two parts and controlled by different modules: ufs-mediatek and phy-ufs-mediatek. If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control is not balanced thus unbalanced control also happens to the clocks probed by phy-ufs-mediatek module. Fix this issue by - Promise usage of phy_power_on/off balanced - Remove phy_power_on/off control in suspend/resume vops since both can be handled in setup_clock vops only Signed-off-by: Stanley Chu Reviewed-by: Peter Wang --- drivers/scsi/ufs/ufs-mediatek.c | 56 +++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 24 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 5f41b7b7db8f..de9e643fb8dd 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -205,6 +205,23 @@ int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, return -ETIMEDOUT; } +static void ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + struct phy *mphy = host->mphy; + + if (!mphy) + return; + + if (on && !host->mphy_powered_on) + phy_power_on(mphy); + else if (!on && host->mphy_powered_on) + phy_power_off(mphy); + else + return; + host->mphy_powered_on = on; +} + /** * ufs_mtk_setup_clocks - enables/disable clocks * @hba: host controller instance @@ -228,25 +245,24 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, return 0; if (!on && status == PRE_CHANGE) { - if (!ufshcd_is_link_active(hba)) { - ufs_mtk_setup_ref_clk(hba, on); - ret = phy_power_off(host->mphy); - } else { - /* - * Gate ref-clk if link state is in Hibern8 - * triggered by Auto-Hibern8. - */ - if (!ufshcd_can_hibern8_during_gating(hba) && - ufshcd_is_auto_hibern8_enabled(hba)) { - ret = ufs_mtk_wait_link_state(hba, - VS_LINK_HIBERN8, - 15); - if (!ret) - ufs_mtk_setup_ref_clk(hba, on); + /* + * Gate ref-clk and poweroff mphy if link state is in OFF + * or Hibern8 by either ufshcd_link_state_transition() or + * Auto-Hibern8. + */ + if (!ufshcd_is_link_active(hba) || + (!ufshcd_can_hibern8_during_gating(hba) && + ufshcd_is_auto_hibern8_enabled(hba))) { + ret = ufs_mtk_wait_link_state(hba, + VS_LINK_HIBERN8, + 15); + if (!ret) { + ufs_mtk_setup_ref_clk(hba, on); + ufs_mtk_mphy_power_on(hba, on); } } } else if (on && status == POST_CHANGE) { - ret = phy_power_on(host->mphy); + ufs_mtk_mphy_power_on(hba, on); ufs_mtk_setup_ref_clk(hba, on); } @@ -538,7 +554,6 @@ static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm) static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { int err; - struct ufs_mtk_host *host = ufshcd_get_variant(hba); if (ufshcd_is_link_hibern8(hba)) { err = ufs_mtk_link_set_lpm(hba); @@ -559,20 +574,13 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) ufs_mtk_vreg_set_lpm(hba, true); } - if (!ufshcd_is_link_active(hba)) - phy_power_off(host->mphy); - return 0; } static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) { - struct ufs_mtk_host *host = ufshcd_get_variant(hba); int err; - if (!ufshcd_is_link_active(hba)) - phy_power_on(host->mphy); - if (ufshcd_is_link_hibern8(hba)) { ufs_mtk_vreg_set_lpm(hba, false); err = ufs_mtk_link_set_hpm(hba); From patchwork Fri May 29 09:23:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11578199 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 81B6992A for ; Fri, 29 May 2020 09:23:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 693D220810 for ; Fri, 29 May 2020 09:23:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="KwTZZDkA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726827AbgE2JXZ (ORCPT ); Fri, 29 May 2020 05:23:25 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:4907 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726549AbgE2JXR (ORCPT ); Fri, 29 May 2020 05:23:17 -0400 X-UUID: 8ae41f0dddb64b6c87ab748084eeb24b-20200529 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=4xEpx/TR5nABOEWlUURKNlyYrrqiM9TJ/MUnzRuryNo=; b=KwTZZDkAIWumGSURBvHi/MkEzOdtzSDG5OkFGzfJDV3FCxN+ekl8udQO9RQiNU/44leRavlOtIH+ubEpVAgRuRGSdufDqvisbIYkQ7CkQsoK4RdMA1u1009TgPZEYVDYK9Xa6kMgCv4J1yqrMp3yZxN2POLHslFmH+BtUQlFV8E=; X-UUID: 8ae41f0dddb64b6c87ab748084eeb24b-20200529 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1236833289; Fri, 29 May 2020 17:23:14 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 May 2020 17:23:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 May 2020 17:23:11 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v2 5/5] scsi: ufs-mediatek: Allow unbound mphy Date: Fri, 29 May 2020 17:23:10 +0800 Message-ID: <20200529092310.1106-6-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200529092310.1106-1-stanley.chu@mediatek.com> References: <20200529092310.1106-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 451FC8FF6AD885113447FC16F8CFD0DF8E384566BE623E31C5FFF9080F619BF32000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Allow unbound MPHY module since not every MediaTek UFS platform needs specific MPHY control. Signed-off-by: Stanley Chu Reviewed-by: Peter Wang --- drivers/scsi/ufs/ufs-mediatek.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index de9e643fb8dd..d587b3276aa8 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -113,6 +113,12 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba) if (err) host->mphy = NULL; + /* + * Allow unbound mphy because not every platform needs specific + * mphy control. + */ + if (err == -ENODEV) + err = 0; return err; }