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Signed-off-by: Parshuram Thombare --- Documentation/driver-api/i3c/index.rst | 1 + .../i3c/master-initialization-flow.rst | 187 ++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 Documentation/driver-api/i3c/master-initialization-flow.rst diff --git a/Documentation/driver-api/i3c/index.rst b/Documentation/driver-api/i3c/index.rst index 783d6dad054b..604f1c5e4a5b 100644 --- a/Documentation/driver-api/i3c/index.rst +++ b/Documentation/driver-api/i3c/index.rst @@ -9,3 +9,4 @@ I3C subsystem protocol device-driver-api master-driver-api + master-initialization-flow diff --git a/Documentation/driver-api/i3c/master-initialization-flow.rst b/Documentation/driver-api/i3c/master-initialization-flow.rst new file mode 100644 index 000000000000..b5849f4e229e --- /dev/null +++ b/Documentation/driver-api/i3c/master-initialization-flow.rst @@ -0,0 +1,187 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================== +I3C Master Initialization Flow +============================== + +.. kernel-render:: DOT + :alt: I3C Master Initialization digraph + :caption: I3C Master Initialization Flow + + digraph master_init { + ranksep=.25; size="35,35"; + subgraph cluster_0 { + style=dashed + x0[shape=ellipse, label="I3C driver probe", style="filled"] + x1[shape=diamond, label="Secondary Master ?"] + a1[shape=box, label="Do I3C master controller specific initialization"] + b1[shape=box, label="Do I3C master controller specific initialization,\n + except enabling the DEFSLVS interrupt."] + a2[shape=box, label="Call i3c_primary_master_register"] + b2[shape=box, label="Call i3c_secondary_master_register"] + x0->x1; + x1->a1[label="No"]; + x1->b1[label="Yes"]; + a1->a2; b1->b2; + } + + subgraph cluster_1 { + style=dashed + label="Current Master"; + a3[shape=ellipse, label="i3c_primary_master_register", style="filled"] + a4[shape=box, label="Initialize I3C master controller object."] + a5[shape=box, label="Create I2C objects for devices in DTS and add to I2C list."] + a6[shape=box, label="Set appropriate bus mode based on I2C devices information."] + a7[shape=box, label="Create a work queue."] + a8[shape=box, label="Call i3c_primary_master_bus_init"] + a19[shape=box, label="Add I3C object representing this master to the system."] + a20[shape=box, label="Expose our I3C bus as an I2C adapter so that I2C devices\n + are exposed through the I2C subsystem."] + a21[shape=box, label="Register all I3C devices."] + a22[shape=box, label="Broadcast ENEC MR, HJ message."] + a3->a4->a5->a6->a7->a8; a19->a20->a21->a22; + a8->a19[style="invisible"]; + } + + subgraph cluster_2 { + style=dashed + label="Current Master"; + a9[shape=ellipse, label="i3c_primary_master_bus_init", style="filled"] + a10[shape=box, label="Call bus_init to do controller specific bus initialization\n + and enabling the controller."] + a11[shape=box, label="Create I3C object representing the master and add it to\n + the I3C device list."] + a12[shape=box, label="Set current master to the object created to represent I3C\n + master device."] + a13[shape=box, label="Reset all dynamic address that may have been assigned before."] + a14[shape=box, label="Disable all slave events before starting DAA."] + a15[shape=box, label="Pre-assign dynamic address and retrieve device information."] + a16[shape=box, label="Do dynamic address assignment to all I3C devices currenly\n + present on the bus."] + a17[shape=box, label="Create I3C objects representing devices found during DAA."] + a18[shape=box, label="Send DEFSVLS message containing information about all\n + known I3C and I2C devices."] + a9->a10->a11->a12->a13->a14->a15->a16->a17->a18; + } + + subgraph cluster_3 { + style=dashed + label="Current Master"; + h1[shape=ellipse, label="MR request interrupt", style="filled"] + h2[shape=box, label="Bottom half i3c_master_yield_bus"] + h1->h2; + } + + subgraph cluster_4 { + style=dashed + label="Current Master"; + i1[shape=ellipse, label="i3c_master_yield_bus", style="filled"] + i2[shape=box, label="Check if this device is still a master to handle a case of\n + multiple MR requests from different devices at a same time."] + i3[shape=box, label="Broadcast DISEC MR, HJ message.\n + New master should broadcast ENEC MR, HJ once its usage of bus is done."] + i4[shape=box, label="Get accept mastership acknowldege from requesting master."] + i5[shape=box, label="In case of failure reenable MR requests by broadcasting ENEC MR, HJ."] + i6[shape=box, label="Mastership hand over is done."] + i1->i2->i3->i4->i5->i6; + } + + subgraph cluster_5 { + style=dashed + b3[shape=ellipse, label="i3c_secondary_master_register", style="filled"] + b4[shape=box, label="Initialize I3C master controller object."] + b5[shape=box, label="Create I2C objects for devices in DTS and add to I2C list."] + b6[shape=box, label="Set appropriate bus mode based on I2C devices information."] + b7[shape=box, label="Create a work queue."] + b8[shape=box, label="Call i3c_secondary_master_bus_init."] + b12[shape=box, label="Allocate memory for defslvs_data, that will be used to pass I3C\n + device list received in DEFSLVS to the I3C core DEFSLVS processing."] + b13[shape=box, label="Add I3C object representing this master to the system."] + b14[shape=box, label="Expose our I3C bus as an I2C adapter so that I2C devices are\n + exposed through the I2C subsystem."] + b3->b4->b5->b6->b7->b8; b12->b13->b14; + b8->b12[style="invisible"] + } + + subgraph cluster_6 { + style=dashed + b9[shape=ellipse, label="i3c_secondary_master_bus_init", style="filled"] + b10[shape=box, label="Call bus_init to do controller specific bus initialization\n + and enabling the controller."] + b11[shape=box, label="Create I3C object representing the master and add it to\n + the I3C device list."] + b9->b10->b11; + } + + subgraph cluster_7 { + style=dashed + d1[shape=ellipse, label="DEFSLVS interrupt", style="filled"] + d2[shape=box, label="Controller driver can chose how to to handle I2C devices received\n + in DEFSLVS."] + d3[shape=box, label="Read all I3C devices information from DEFSLVS message\n + to defslvs_data structure in the master object."] + d4[shape=box, label="Call i3c_master_process_defslvs."] + d1->d2->d3->d4; + } + + subgraph cluster_8 { + style=dashed + d5[shape=ellipse, label="i3c_master_process_defslvs", style="filled"] + d6[shape=box, label="Acquire I3C bus mastership."] + d7[shape=diamond, label="Bus acquired ?"] + d8[shape=box, label="Handle I3C device list from DEFSLVS."] + d9[shape=box, label="Call i3c_master_populate_bus"] + d10[shape=box, label="Queue defslvs processing task for retry."] + d5->d6; + d7->d8[label="Yes"]; + d8->d9; + d7->d10[label="No"]; + d6->d7[style="invisible"]; + d10->d5[style="dotted", constraint=false]; + } + + subgraph cluster_9 { + style=dashed + e1[shape=ellipse, label="i3c_master_acquire_bus", style="filled"] + e2[shape=box, label="If device is already holding the mastership,\n + just broadcast DISEC MR, HJ message and return success."] + e3[shape=box, label="Call request_mastership method"] + e1->e2->e3; + } + + subgraph cluster_10 { + style=dashed + f1[shape=ellipse, label="request_mastership", style="filled"] + f2[shape=box, label="Return success if device is already in master mode."] + f3[shape=box, label="Return error if device don't have dyn_addr."] + f4[shape=box, label="Return error if MR requests are disabled by current master."] + f5[shape=box, label="Send MR request"] + f6[shape=box, label="Wait with timeout until MR_DONE interrupt is received."] + f1->f2->f3->f4->f5->f6; + } + + subgraph cluster_11 { + style=dashed + g1[shape=ellipse, label="i3c_master_populate_bus", style="filled"] + g2[shape=box, label="Free up all I3C addresses to handle address\n + re assignment by main master."] + g3[shape=box, label="Master acquire dyn_addr received from the driver."] + g4[shape=box, label="For every I3C device in the defslvs_data\n + call i3c_master_add_i3c_dev_locked."] + g1->g2->g3->g4; + } + + a2->a3; a8->a9; a18->a19; + b2->b3; b8->b9; b11->b12; + b14->d1[style=invisible]; + a22->h1[style=invisible]; + d4->d5; + d6->e1; + e3->f1; + f6->d7[constraint=false]; + h2->i1; + d9->g1; + a18->d1[style="dotted", constraint=false]; + f5->h1[style="dotted", constraint=false]; + i4->f6[style="dotted", constraint=false]; + } From patchwork Sun May 31 07:12:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 11580601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E47CE1392 for ; Sun, 31 May 2020 07:12:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C037E207BC for ; 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Signed-off-by: Parshuram Thombare --- drivers/i3c/master.c | 74 +++++++++++++++++----------- drivers/i3c/master/dw-i3c-master.c | 4 +- drivers/i3c/master/i3c-master-cdns.c | 4 +- include/linux/i3c/master.h | 7 ++- 4 files changed, 51 insertions(+), 38 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 5f4bd52121fe..574c3603db38 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1613,7 +1613,7 @@ static void i3c_master_detach_free_devs(struct i3c_master_controller *master) } /** - * i3c_master_bus_init() - initialize an I3C bus + * i3c_primary_master_bus_init() - initialize an I3C bus * @master: main master initializing the bus * * This function is following all initialisation steps described in the I3C @@ -1642,7 +1642,7 @@ static void i3c_master_detach_free_devs(struct i3c_master_controller *master) * * Return: a 0 in case of success, an negative error code otherwise. */ -static int i3c_master_bus_init(struct i3c_master_controller *master) +static int i3c_primary_master_bus_init(struct i3c_master_controller *master) { enum i3c_addr_slot_status status; struct i2c_dev_boardinfo *i2cboardinfo; @@ -2391,31 +2391,10 @@ static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops) return 0; } -/** - * i3c_master_register() - register an I3C master - * @master: master used to send frames on the bus - * @parent: the parent device (the one that provides this I3C master - * controller) - * @ops: the master controller operations - * @secondary: true if you are registering a secondary master. Will return - * -ENOTSUPP if set to true since secondary masters are not yet - * supported - * - * This function takes care of everything for you: - * - * - creates and initializes the I3C bus - * - populates the bus with static I2C devs if @parent->of_node is not - * NULL - * - registers all I3C devices added by the controller during bus - * initialization - * - registers the I2C adapter and all I2C devices - * - * Return: 0 in case of success, a negative error code otherwise. - */ -int i3c_master_register(struct i3c_master_controller *master, - struct device *parent, - const struct i3c_master_controller_ops *ops, - bool secondary) +static int i3c_master_init(struct i3c_master_controller *master, + struct device *parent, + const struct i3c_master_controller_ops *ops, + bool secondary) { struct i3c_bus *i3cbus = i3c_master_get_bus(master); enum i3c_bus_mode mode = I3C_BUS_MODE_PURE; @@ -2478,10 +2457,46 @@ int i3c_master_register(struct i3c_master_controller *master, goto err_put_dev; } - ret = i3c_master_bus_init(master); + ret = i3c_primary_master_bus_init(master); if (ret) goto err_put_dev; + return 0; + +err_put_dev: + put_device(&master->dev); + + return ret; +} + +/** + * i3c_primary_master_register() - register an I3C master + * @master: master used to send frames on the bus + * @parent: the parent device (the one that provides this I3C master + * controller) + * @ops: the master controller operations + * + * This function takes care of everything for you: + * + * - creates and initializes the I3C bus + * - populates the bus with static I2C devs if @parent->of_node is not + * NULL + * - registers all I3C devices added by the controller during bus + * initialization + * - registers the I2C adapter and all I2C devices + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int i3c_primary_master_register(struct i3c_master_controller *master, + struct device *parent, + const struct i3c_master_controller_ops *ops) +{ + int ret; + + ret = i3c_master_init(master, parent, ops, false); + if (ret) + return ret; + ret = device_add(&master->dev); if (ret) goto err_cleanup_bus; @@ -2511,12 +2526,11 @@ int i3c_master_register(struct i3c_master_controller *master, err_cleanup_bus: i3c_master_bus_cleanup(master); -err_put_dev: put_device(&master->dev); return ret; } -EXPORT_SYMBOL_GPL(i3c_master_register); +EXPORT_SYMBOL_GPL(i3c_primary_master_register); /** * i3c_master_unregister() - unregister an I3C master diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c index 1d83c97431c7..47d47aa97569 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -1157,8 +1157,8 @@ static int dw_i3c_probe(struct platform_device *pdev) master->maxdevs = ret >> 16; master->free_pos = GENMASK(master->maxdevs - 1, 0); - ret = i3c_master_register(&master->base, &pdev->dev, - &dw_mipi_i3c_ops, false); + ret = i3c_primary_master_register(&master->base, &pdev->dev, + &dw_mipi_i3c_ops); if (ret) goto err_assert_rst; diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c index 8889a4fdb454..c7db02543e33 100644 --- a/drivers/i3c/master/i3c-master-cdns.c +++ b/drivers/i3c/master/i3c-master-cdns.c @@ -1614,8 +1614,8 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) writel(MST_INT_IBIR_THR, master->regs + MST_IER); writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL); - ret = i3c_master_register(&master->base, &pdev->dev, - &cdns_i3c_master_ops, false); + ret = i3c_primary_master_register(&master->base, &pdev->dev, + &cdns_i3c_master_ops); if (ret) goto err_disable_sysclk; diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index f13fd8b1dd79..a19d0ad4de8a 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -531,10 +531,9 @@ int i3c_master_do_daa(struct i3c_master_controller *master); int i3c_master_set_info(struct i3c_master_controller *master, const struct i3c_device_info *info); -int i3c_master_register(struct i3c_master_controller *master, - struct device *parent, - const struct i3c_master_controller_ops *ops, - bool secondary); +int i3c_primary_master_register(struct i3c_master_controller *master, + struct device *parent, + const struct i3c_master_controller_ops *ops); int i3c_master_unregister(struct i3c_master_controller *master); /** From patchwork Sun May 31 07:13:18 2020 Content-Type: text/plain; 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Signed-off-by: Parshuram Thombare --- drivers/i3c/master.c | 154 ++++++++++++++++++++++++++++++++++++- include/linux/i3c/master.h | 3 + 2 files changed, 156 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 574c3603db38..62f39997a6db 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1768,6 +1768,90 @@ static int i3c_primary_master_bus_init(struct i3c_master_controller *master) return ret; } +/** + * i3c_secondary_master_bus_init() - initialize an I3C bus for secondary + * master + * @master: secondary master initializing the bus + * + * This function does + * + * 1. Attach I2C devs to the master + * + * 2. Call &i3c_master_controller_ops->bus_init() method to initialize + * the master controller. That's usually where the bus mode is selected + * (pure bus or mixed fast/slow bus) + * + * Once this is done, I2C devices should be usable. + * + * Return: a 0 in case of success, an negative error code otherwise. + */ +static int i3c_secondary_master_bus_init(struct i3c_master_controller *master) +{ + enum i3c_addr_slot_status status; + struct i2c_dev_boardinfo *i2cboardinfo; + struct i2c_dev_desc *i2cdev; + int ret; + + /* + * First attach all devices with static definitions provided by the + * FW. + */ + list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) { + status = i3c_bus_get_addr_slot_status(&master->bus, + i2cboardinfo->base.addr); + if (status != I3C_ADDR_SLOT_FREE) { + ret = -EBUSY; + goto err_detach_devs; + } + + i3c_bus_set_addr_slot_status(&master->bus, + i2cboardinfo->base.addr, + I3C_ADDR_SLOT_I2C_DEV); + + i2cdev = i3c_master_alloc_i2c_dev(master, i2cboardinfo); + if (IS_ERR(i2cdev)) { + ret = PTR_ERR(i2cdev); + goto err_detach_devs; + } + + ret = i3c_master_attach_i2c_dev(master, i2cdev); + if (ret) { + i3c_master_free_i2c_dev(i2cdev); + goto err_detach_devs; + } + } + + /* + * Now execute the controller specific ->bus_init() routine, which + * might configure its internal logic to match the bus limitations. + */ + ret = master->ops->bus_init(master); + if (ret) + goto err_detach_devs; + + /* + * The master device should have been instantiated in ->bus_init(), + * complain if this was not the case. + */ + if (!master->this) { + dev_err(&master->dev, + "master_set_info() was not called in ->bus_init()\n"); + ret = -EINVAL; + goto err_bus_cleanup; + } + + return 0; + +err_bus_cleanup: + if (master->ops->bus_cleanup) + master->ops->bus_cleanup(master); + +err_detach_devs: + i3c_master_detach_free_devs(master); + + return ret; +} + static void i3c_master_bus_cleanup(struct i3c_master_controller *master) { if (master->ops->bus_cleanup) @@ -2457,7 +2541,10 @@ static int i3c_master_init(struct i3c_master_controller *master, goto err_put_dev; } - ret = i3c_primary_master_bus_init(master); + if (secondary) + ret = i3c_secondary_master_bus_init(master); + else + ret = i3c_primary_master_bus_init(master); if (ret) goto err_put_dev; @@ -2532,6 +2619,71 @@ int i3c_primary_master_register(struct i3c_master_controller *master, } EXPORT_SYMBOL_GPL(i3c_primary_master_register); +/** + * i3c_secondary_master_register() - register an I3C secondary master + * @master: master used to send frames on the bus + * @parent: the parent device (the one that provides this I3C master + * controller) + * @ops: the master controller operations + * + * This function does minimal required initialization for secondary + * master, rest functionality like creating and registering I2C + * and I3C devices is done in defslvs processing. + * + * i3c_secondary_master_register() does following things - + * - creates and initializes the I3C bus + * - populates the bus with static I2C devs if @parent->of_node is not + * NULL + * initialization + * - allocate memory for defslvs_data.devs, which is used to receive + * defslvs list + * - create I3C device representing this master + * - registers the I2C adapter and all I2C devices + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int i3c_secondary_master_register(struct i3c_master_controller *master, + struct device *parent, + const struct i3c_master_controller_ops *ops) +{ + int ret; + + ret = i3c_master_init(master, parent, ops, true); + if (ret) + return ret; + + ret = device_add(&master->dev); + if (ret) + goto err_cleanup_bus; + + /* + * Expose our I3C bus as an I2C adapter so that I2C devices are exposed + * through the I2C subsystem. + */ + ret = i3c_master_i2c_adapter_init(master); + if (ret) + goto err_del_dev; + + /* + * We're done initializing the bus and the controller, we can now + * register I3C devices from defslvs list. + */ + master->init_done = true; + + return 0; + +err_del_dev: + device_del(&master->dev); + +err_cleanup_bus: + i3c_master_bus_cleanup(master); + + put_device(&master->dev); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_secondary_master_register); + /** * i3c_master_unregister() - unregister an I3C master * @master: master used to send frames on the bus diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index a19d0ad4de8a..c3d05f66fceb 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -534,6 +534,9 @@ int i3c_master_set_info(struct i3c_master_controller *master, int i3c_primary_master_register(struct i3c_master_controller *master, struct device *parent, const struct i3c_master_controller_ops *ops); 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Signed-off-by: Parshuram Thombare --- drivers/i3c/master.c | 176 +++++++++++++++++++++++++++++++++++-- include/linux/i3c/master.h | 6 ++ 2 files changed, 173 insertions(+), 9 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 62f39997a6db..f9ab21e8f6ee 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -43,6 +43,16 @@ static void i3c_bus_maintenance_lock(struct i3c_bus *bus) down_write(&bus->lock); } +/** + * i3c_bus_maintenance_downgrade_lock - Downgrade maintenance lock to + * normaluse lock. + * @bus: I3C bus to take the lock on + */ +static void i3c_bus_maintenance_downgrade_lock(struct i3c_bus *bus) +{ + downgrade_write(&bus->lock); +} + /** * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance * operation @@ -467,6 +477,59 @@ static const char * const i3c_bus_mode_strings[] = { [I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow", }; +static int i3c_master_enable_mr_events(struct i3c_master_controller *master) +{ + int ret; + + master->ops->enable_mr_events(master); + i3c_bus_maintenance_lock(&master->bus); + ret = i3c_master_enec_locked(master, I3C_BROADCAST_ADDR, + I3C_CCC_EVENT_MR | I3C_CCC_EVENT_HJ); + i3c_bus_maintenance_unlock(&master->bus); + + return ret; +} + +/** + * i3c_master_acquire_bus() - acquire I3C bus mastership + * @m: I3C master object + * + * This function may sleep. + * It is expected to be called with normaluse_lock. + */ +static int i3c_master_acquire_bus(struct i3c_master_controller *m) +{ + int ret = 0; + + /* + * Request mastership needs maintenance(write) lock. So, to avoid + * deadlock, release normaluse(read) lock, which is expected to be + * held before calling this function. + * normaluse(read) lock is expected to be held before calling + * this function to avoid race with maintenance activities + * like DEFSLVS processing etc + */ + i3c_bus_normaluse_unlock(&m->bus); + i3c_bus_maintenance_lock(&m->bus); + + if (m->this && m->this == m->bus.cur_master) { + i3c_master_disec_locked(m, I3C_BROADCAST_ADDR, + I3C_CCC_EVENT_MR | + I3C_CCC_EVENT_HJ); + goto mr_req_done; + } + + ret = m->ops->request_mastership(m); + if (ret) + goto mr_req_done; + + m->bus.cur_master = m->this; + +mr_req_done: + i3c_bus_maintenance_downgrade_lock(&m->bus); + return ret; +} + static ssize_t mode_show(struct device *dev, struct device_attribute *da, char *buf) @@ -685,6 +748,33 @@ static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master, return 0; } +static int i3c_master_get_accmst_locked(struct i3c_master_controller *master, + u8 addr) +{ + struct i3c_ccc_getaccmst *accmst; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + accmst = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*accmst)); + if (!accmst) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETACCMST, &dest, 1); + + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + if (dest.payload.len != sizeof(*accmst)) + ret = -EIO; + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + static struct i2c_dev_desc * i3c_master_find_i2c_dev_by_addr(const struct i3c_master_controller *master, u16 addr) @@ -1558,10 +1648,6 @@ int i3c_master_set_info(struct i3c_master_controller *master, if (!i3c_bus_dev_addr_is_avail(&master->bus, info->dyn_addr)) return -EINVAL; - if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER && - master->secondary) - return -EINVAL; - if (master->this) return -EINVAL; @@ -1570,7 +1656,9 @@ int i3c_master_set_info(struct i3c_master_controller *master, return PTR_ERR(i3cdev); master->this = i3cdev; - master->bus.cur_master = master->this; + + if (!master->secondary) + master->bus.cur_master = master->this; ret = i3c_master_attach_i3c_dev(master, i3cdev); if (ret) @@ -1612,6 +1700,74 @@ static void i3c_master_detach_free_devs(struct i3c_master_controller *master) } } +/** + * i3c_master_yield_bus() - yield I3C bus mastership + * @m: I3C master object + * @sec_mst_dyn_addr: address of device requesting mastership + * + * This function may sleep. + * It is expected to be called with normaluse_lock. + */ +void +i3c_master_yield_bus(struct i3c_master_controller *m, u8 sec_mst_dyn_addr) +{ + struct i3c_dev_desc *i3cdev; + bool dev_found = false; + int ret = 0; + + i3c_bus_maintenance_lock(&m->bus); + if (m->this != m->bus.cur_master) + goto mr_yield_done; + + i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { + if (sec_mst_dyn_addr == i3cdev->info.dyn_addr) { + dev_found = true; + break; + } + } + + /* Requesting device not found on i3c list. This should never happen. */ + if (!dev_found) + goto mr_yield_done; + + /* + * Maintenance lock and master check above is used to + * avoid race amongst devices sending MR requests + * at the same time, as soon as ENEC MST is sent by the current + * master. It ensure that only one MR request is processed, + * rest MR requests on losing devices will timeout in wait MR + * DONE state. And next MR requests are blocked due to DISEC MST + * sent by current master in yield operation. + * New master should send ENEC MST once it's work is done. + * maintainanace lock is also needed for i3c_master_get_accmst_locked. + */ + + ret = i3c_master_disec_locked(m, I3C_BROADCAST_ADDR, + I3C_CCC_EVENT_MR | + I3C_CCC_EVENT_HJ); + /* + * Once mastership is given to the new master, it is expected that + * MR is disabled prior to that and new master is responsible to + * enable it by broadcasting ENEC MR when it's work is done. + * If DISEC MR fails and we still go ahead with handover, chances + * are new master will get interrupted by unexpected MR requests. + */ + if (ret) + goto mr_yield_done; + + ret = i3c_master_get_accmst_locked(m, sec_mst_dyn_addr); + if (ret) + goto mr_yield_done; + + m->bus.cur_master = i3cdev; + +mr_yield_done: + i3c_bus_maintenance_unlock(&m->bus); + if (ret) + i3c_master_enable_mr_events(m); +} +EXPORT_SYMBOL_GPL(i3c_master_yield_bus); + /** * i3c_primary_master_bus_init() - initialize an I3C bus * @master: main master initializing the bus @@ -2472,6 +2628,9 @@ static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops) !ops->recycle_ibi_slot)) return -EINVAL; + if (ops->request_mastership && !ops->enable_mr_events) + return -EINVAL; + return 0; } @@ -2485,10 +2644,6 @@ static int i3c_master_init(struct i3c_master_controller *master, struct i2c_dev_boardinfo *i2cbi; int ret; - /* We do not support secondary masters yet. */ - if (secondary) - return -ENOTSUPP; - ret = i3c_master_check_ops(ops); if (ret) return ret; @@ -2605,6 +2760,9 @@ int i3c_primary_master_register(struct i3c_master_controller *master, i3c_master_register_new_i3c_devs(master); i3c_bus_normaluse_unlock(&master->bus); + if (ops->request_mastership) + ret = i3c_master_enable_mr_events(master); + return 0; err_del_dev: diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index c3d05f66fceb..693b920bfd54 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -418,6 +418,8 @@ struct i3c_bus { * for a future IBI * This method is mandatory only if ->request_ibi is not * NULL. + * @request_mastership: send mastership request to the current master + * @enable_mr_events: enable mastership request handling by the controller */ struct i3c_master_controller_ops { int (*bus_init)(struct i3c_master_controller *master); @@ -445,6 +447,8 @@ struct i3c_master_controller_ops { int (*disable_ibi)(struct i3c_dev_desc *dev); void (*recycle_ibi_slot)(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot); + int (*request_mastership)(struct i3c_master_controller *master); + void (*enable_mr_events)(struct i3c_master_controller *m); }; /** @@ -510,6 +514,8 @@ struct i3c_master_controller { #define i3c_bus_for_each_i3cdev(bus, dev) \ list_for_each_entry(dev, &(bus)->devs.i3c, common.node) +void i3c_master_yield_bus(struct i3c_master_controller *m, + u8 sec_mst_dyn_addr); int i3c_master_do_i2c_xfers(struct i3c_master_controller *master, const struct i2c_msg *xfers, int nxfers); From patchwork Sun May 31 07:15:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 11580607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BEEA913 for ; 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Ip=[158.140.1.148]; Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR07MB3494 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-05-31_01:2020-05-28, 2020-05-31 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 malwarescore=0 mlxlogscore=999 suspectscore=0 phishscore=0 adultscore=0 cotscore=-2147483648 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2005310057 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200531_001512_528328_6FBFAB84 X-CRM114-Status: GOOD ( 18.59 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [208.84.65.235 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux I3C List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mparab@cadence.com, Parshuram Thombare , praneeth@ti.com, linux-kernel@vger.kernel.org, pgaj@cadence.com, linux-i3c@lists.infradead.org Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=patchwork.kernel.org@lists.infradead.org Added defslvs processing code to the I3C master subsystem. Signed-off-by: Parshuram Thombare --- drivers/i3c/master.c | 68 ++++++++++++++++++++++++++++++++++++-- include/linux/i3c/master.h | 7 ++++ 2 files changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index f9ab21e8f6ee..de3cb39df9ff 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2127,7 +2127,7 @@ int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, else expected_dyn_addr = newdev->info.dyn_addr; - if (newdev->info.dyn_addr != expected_dyn_addr) { + if (!master->secondary && newdev->info.dyn_addr != expected_dyn_addr) { /* * Try to apply the expected dynamic address. If it fails, keep * the address assigned by the master. @@ -2804,12 +2804,20 @@ int i3c_secondary_master_register(struct i3c_master_controller *master, struct device *parent, const struct i3c_master_controller_ops *ops) { - int ret; + int ret, sz; ret = i3c_master_init(master, parent, ops, true); if (ret) return ret; + sz = sizeof(struct i3c_ccc_dev_desc) * I3C_BUS_MAX_DEVS; + master->defslvs_data.devs = devm_kzalloc(&master->dev, sz, + GFP_KERNEL); + if (!master->defslvs_data.devs) { + ret = -ENOMEM; + goto err_cleanup_bus; + } + ret = device_add(&master->dev); if (ret) goto err_cleanup_bus; @@ -2842,6 +2850,62 @@ int i3c_secondary_master_register(struct i3c_master_controller *master, } EXPORT_SYMBOL_GPL(i3c_secondary_master_register); +static int +i3c_master_populate_bus(struct i3c_master_controller *master, u8 dyn_addr) +{ + struct i3c_dev_desc *olddev; + struct i3c_ccc_dev_desc *desc; + int ret, slot; + + i3c_bus_for_each_i3cdev(&master->bus, olddev) + i3c_master_put_i3c_addrs(olddev); + + master->this->info.dyn_addr = dyn_addr; + i3c_master_get_i3c_addrs(master->this); + + desc = master->defslvs_data.devs; + for (slot = 1; slot < master->defslvs_data.ndevs; slot++) { + ret = i3c_master_add_i3c_dev_locked(master, + desc[slot].dyn_addr); + if (ret) + break; + } + + return ret; +} + +/** + * i3c_master_process_defslvs() - process I3C device list received in + * DEFSLVS for device plug/unplug and address change. + * @m: I3C master object + * @dyn_addr: Current dynamic address of this device + * + * This function may sleep, so should not be called in the atomic context. + */ +int i3c_master_process_defslvs(struct i3c_master_controller *m, u8 dyn_addr) +{ + int ret; + + i3c_bus_normaluse_lock(&m->bus); + ret = i3c_master_acquire_bus(m); + i3c_bus_normaluse_unlock(&m->bus); + if (ret) + return ret; + + i3c_bus_maintenance_lock(&m->bus); + ret = i3c_master_populate_bus(m, dyn_addr); + i3c_bus_maintenance_unlock(&m->bus); + if (!ret) { + i3c_bus_normaluse_lock(&m->bus); + i3c_master_register_new_i3c_devs(m); + i3c_bus_normaluse_unlock(&m->bus); + } + i3c_master_enable_mr_events(m); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_master_process_defslvs); + /** * i3c_master_unregister() - unregister an I3C master * @master: master used to send frames on the bus diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index 693b920bfd54..48803736ba17 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -471,6 +471,8 @@ struct i3c_master_controller_ops { * in a thread context. Typical examples are Hot Join processing which * requires taking the bus lock in maintenance, which in turn, can only * be done from a sleep-able context + * @defslvs_data: list used to pass i3c device list received in DEFSLVS message, + * from DEFSLVS controller driver to I3C core * * A &struct i3c_master_controller has to be registered to the I3C subsystem * through i3c_master_register(). None of &struct i3c_master_controller fields @@ -490,6 +492,10 @@ struct i3c_master_controller { } boardinfo; struct i3c_bus bus; struct workqueue_struct *wq; + struct { + u32 ndevs; + struct i3c_ccc_dev_desc *devs; + } defslvs_data; }; /** @@ -516,6 +522,7 @@ struct i3c_master_controller { void i3c_master_yield_bus(struct i3c_master_controller *m, u8 sec_mst_dyn_addr); +int i3c_master_process_defslvs(struct i3c_master_controller *m, u8 dyn_addr); int i3c_master_do_i2c_xfers(struct i3c_master_controller *master, const struct i2c_msg *xfers, int nxfers); From patchwork Sun May 31 07:15:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 11580609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E70AD1392 for ; Sun, 31 May 2020 07:15:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C3333207BC for ; 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Signed-off-by: Parshuram Thombare --- drivers/i3c/master.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index de3cb39df9ff..17c0c9a6099d 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -596,6 +596,23 @@ static ssize_t i2c_scl_frequency_show(struct device *dev, } static DEVICE_ATTR_RO(i2c_scl_frequency); +static ssize_t i3c_acquire_bus_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i3c_master_controller *master = dev_to_i3cmaster(dev); + int ret; + + i3c_bus_normaluse_lock(&master->bus); + ret = i3c_master_acquire_bus(master); + i3c_bus_normaluse_unlock(&master->bus); + if (!ret) + i3c_master_enable_mr_events(master); + + return ret ?: count; +} +static DEVICE_ATTR_WO(i3c_acquire_bus); + static struct attribute *i3c_masterdev_attrs[] = { &dev_attr_mode.attr, &dev_attr_current_master.attr, @@ -606,6 +623,7 @@ static struct attribute *i3c_masterdev_attrs[] = { &dev_attr_pid.attr, &dev_attr_dynamic_address.attr, &dev_attr_hdrcap.attr, + &dev_attr_i3c_acquire_bus.attr, NULL, }; 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Ip=[199.43.4.23]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR0701MB3785 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-05-31_01:2020-05-28, 2020-05-31 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 malwarescore=0 mlxlogscore=999 suspectscore=2 phishscore=0 adultscore=0 cotscore=-2147483648 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2005310057 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200531_001623_210610_62A2647F X-CRM114-Status: GOOD ( 17.11 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [208.84.65.235 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux I3C List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mparab@cadence.com, Parshuram Thombare , praneeth@ti.com, linux-kernel@vger.kernel.org, pgaj@cadence.com, linux-i3c@lists.infradead.org Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=patchwork.kernel.org@lists.infradead.org Added I3C bus mastership handover and DEFSLVS message handling code to Cadence's I3C master controller driver. Signed-off-by: Parshuram Thombare --- drivers/i3c/master/i3c-master-cdns.c | 329 +++++++++++++++++++++++++-- 1 file changed, 306 insertions(+), 23 deletions(-) diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c index c7db02543e33..fa54725be47c 100644 --- a/drivers/i3c/master/i3c-master-cdns.c +++ b/drivers/i3c/master/i3c-master-cdns.c @@ -157,6 +157,7 @@ #define SLV_IMR 0x48 #define SLV_ICR 0x4c #define SLV_ISR 0x50 +#define SLV_INT_DEFSLVS BIT(21) #define SLV_INT_TM BIT(20) #define SLV_INT_ERROR BIT(19) #define SLV_INT_EVENT_UP BIT(18) @@ -189,7 +190,7 @@ #define SLV_STATUS1_HJ_DIS BIT(18) #define SLV_STATUS1_MR_DIS BIT(17) #define SLV_STATUS1_PROT_ERR BIT(16) -#define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9) +#define SLV_STATUS1_DA(s) (((s) & GENMASK(15, 9)) >> 9) #define SLV_STATUS1_HAS_DA BIT(8) #define SLV_STATUS1_DDR_RX_FULL BIT(7) #define SLV_STATUS1_DDR_TX_FULL BIT(6) @@ -390,6 +391,9 @@ struct cdns_i3c_xfer { struct cdns_i3c_master { struct work_struct hj_work; + struct work_struct mr_yield_work; + struct work_struct defslvs_work; + struct completion mr_done; struct i3c_master_controller base; u32 free_rr_slots; unsigned int maxdevs; @@ -408,6 +412,7 @@ struct cdns_i3c_master { struct clk *pclk; struct cdns_i3c_master_caps caps; unsigned long i3c_scl_lim; + u8 mr_addr; }; static inline struct cdns_i3c_master * @@ -1187,10 +1192,6 @@ static int cdns_i3c_master_do_daa(struct i3c_master_controller *m) cdns_i3c_master_upd_i3c_scl_lim(master); - /* Unmask Hot-Join and Mastership request interrupts. */ - i3c_master_enec_locked(m, I3C_BROADCAST_ADDR, - I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR); - return 0; } @@ -1199,21 +1200,21 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) struct cdns_i3c_master *master = to_cdns_i3c_master(m); unsigned long pres_step, sysclk_rate, max_i2cfreq; struct i3c_bus *bus = i3c_master_get_bus(m); - u32 ctrl, prescl0, prescl1, pres, low; + u32 ctrl, prescl0, prescl1, pres, low, bus_mode; struct i3c_device_info info = { }; int ret, ncycles; switch (bus->mode) { case I3C_BUS_MODE_PURE: - ctrl = CTRL_PURE_BUS_MODE; + bus_mode = CTRL_PURE_BUS_MODE; break; case I3C_BUS_MODE_MIXED_FAST: - ctrl = CTRL_MIXED_FAST_BUS_MODE; + bus_mode = CTRL_MIXED_FAST_BUS_MODE; break; case I3C_BUS_MODE_MIXED_SLOW: - ctrl = CTRL_MIXED_SLOW_BUS_MODE; + bus_mode = CTRL_MIXED_SLOW_BUS_MODE; break; default: @@ -1244,7 +1245,6 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5); prescl0 |= PRESCL_CTRL0_I2C(pres); - writel(prescl0, master->regs + PRESCL_CTRL0); /* Calculate OD and PP low. */ pres_step = 1000000000 / (bus->scl_rate.i3c * 4); @@ -1252,7 +1252,6 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) if (ncycles < 0) ncycles = 0; prescl1 = PRESCL_CTRL1_OD_LOW(ncycles); - writel(prescl1, master->regs + PRESCL_CTRL1); /* Get an address for the master. */ ret = i3c_master_get_free_addr(m, 0); @@ -1270,13 +1269,21 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) if (ret) return ret; + ctrl = readl(master->regs + CTRL); + if (ctrl & CTRL_DEV_EN) + cdns_i3c_master_disable(master); + writel(prescl0, master->regs + PRESCL_CTRL0); + writel(prescl1, master->regs + PRESCL_CTRL1); + ctrl &= ~CTRL_BUS_MODE_MASK; + ctrl |= bus_mode | CTRL_HALT_EN | CTRL_MCS_EN; /* * Enable Hot-Join, and, when a Hot-Join request happens, disable all * events coming from this device. * * We will issue ENTDAA afterwards from the threaded IRQ handler. */ - ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN; + if (!m->secondary) + ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC; writel(ctrl, master->regs + CTRL); cdns_i3c_master_enable(master); @@ -1340,6 +1347,7 @@ static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master, static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master) { + struct i3c_dev_desc *dev; u32 status0; writel(MST_INT_IBIR_THR, master->regs + MST_ICR); @@ -1361,6 +1369,14 @@ static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master) case IBIR_TYPE_MR: WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR)); + if (ibir & IBIR_ACKED) { + dev = master->ibi.slots[IBIR_SLVID(ibir)]; + master->mr_addr = dev->info.dyn_addr; + queue_work(master->base.wq, + &master->mr_yield_work); + } + break; + default: break; } @@ -1372,16 +1388,42 @@ static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data) struct cdns_i3c_master *master = data; u32 status; - status = readl(master->regs + MST_ISR); - if (!(status & readl(master->regs + MST_IMR))) - return IRQ_NONE; + if (master->base.this && + master->base.this == master->base.bus.cur_master) { + status = readl(master->regs + MST_ISR); + if (!(status & readl(master->regs + MST_IMR))) + return IRQ_NONE; + + spin_lock(&master->xferqueue.lock); + cdns_i3c_master_end_xfer_locked(master, status); + spin_unlock(&master->xferqueue.lock); + + if (status & MST_INT_IBIR_THR) + cnds_i3c_master_demux_ibis(master); + + if (status & MST_INT_MR_DONE) { + writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO, + master->regs + FLUSH_CTRL); + writel(MST_INT_MR_DONE, master->regs + MST_ICR); + } + } else { + status = (readl(master->regs + SLV_ISR) & + readl(master->regs + SLV_IMR)); + + if (!status) + return IRQ_NONE; + + if (status & SLV_INT_MR_DONE) { + writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO, + master->regs + FLUSH_CTRL); + complete(&master->mr_done); + } - spin_lock(&master->xferqueue.lock); - cdns_i3c_master_end_xfer_locked(master, status); - spin_unlock(&master->xferqueue.lock); + if (status & SLV_INT_DEFSLVS) + queue_work(master->base.wq, &master->defslvs_work); - if (status & MST_INT_IBIR_THR) - cnds_i3c_master_demux_ibis(master); + writel(status, master->regs + SLV_ICR); + } return IRQ_HANDLED; } @@ -1505,6 +1547,106 @@ static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); } +static int cdns_i3c_master_find_ibi_slot(struct cdns_i3c_master *master, + struct i3c_dev_desc *dev, + s16 *slot) +{ + unsigned long flags; + unsigned int i; + int ret = -ENOENT; + + spin_lock_irqsave(&master->ibi.lock, flags); + for (i = 0; i < master->ibi.num_slots; i++) { + if (master->ibi.slots[i] == dev) { + *slot = i; + ret = 0; + break; + } + } + + if (ret) { + for (i = 0; i < master->ibi.num_slots; i++) { + if (!master->ibi.slots[i]) { + master->ibi.slots[i] = dev; + *slot = i; + ret = 0; + break; + } + } + } + spin_unlock_irqrestore(&master->ibi.lock, flags); + + return ret; +} + +static int cdns_i3c_request_mastership(struct i3c_master_controller *m) +{ + struct cdns_i3c_master *master = to_cdns_i3c_master(m); + int status; + + status = readl(master->regs + MST_STATUS0); + if (status & MST_STATUS0_MASTER_MODE) + return 0; + + status = readl(master->regs + SLV_STATUS1); + if (!(status & SLV_STATUS1_HAS_DA)) + return -EACCES; + + if (status & SLV_STATUS1_MR_DIS) + return -EACCES; + + writel(readl(master->regs + CTRL) | CTRL_MST_INIT | CTRL_MST_ACK, + master->regs + CTRL); + + init_completion(&master->mr_done); + if (!wait_for_completion_timeout(&master->mr_done, + msecs_to_jiffies(1000))) + return -ETIMEDOUT; + + return 0; +} + +static void +cdns_i3c_master_enable_mastership_events(struct i3c_master_controller *m) +{ + struct cdns_i3c_master *master = to_cdns_i3c_master(m); + struct cdns_i3c_i2c_dev_data *data; + struct i3c_dev_desc *i3cdev; + unsigned long flags; + u32 sircfg, sirmap; + int ret; + + i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { + if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) != + I3C_BCR_I3C_MASTER || + m->this == i3cdev) + continue; + + data = i3c_dev_get_master_data(i3cdev); + if (!data) + continue; + + ret = cdns_i3c_master_find_ibi_slot(master, i3cdev, &data->ibi); + if (ret) + continue; + + spin_lock_irqsave(&master->ibi.lock, flags); + sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi)); + sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi); + sircfg = SIR_MAP_DEV_ROLE(i3cdev->info.bcr >> 6) | + SIR_MAP_DEV_DA(i3cdev->info.dyn_addr) | + SIR_MAP_DEV_PL(i3cdev->info.max_ibi_len) | + SIR_MAP_DEV_ACK; + + if (i3cdev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) + sircfg |= SIR_MAP_DEV_SLOW; + + sirmap |= SIR_MAP_DEV_CONF(data->ibi, sircfg); + writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi)); + spin_unlock_irqrestore(&master->ibi.lock, flags); + } +} + static const struct i3c_master_controller_ops cdns_i3c_master_ops = { .bus_init = cdns_i3c_master_bus_init, .bus_cleanup = cdns_i3c_master_bus_cleanup, @@ -1524,6 +1666,8 @@ static const struct i3c_master_controller_ops cdns_i3c_master_ops = { .request_ibi = cdns_i3c_master_request_ibi, .free_ibi = cdns_i3c_master_free_ibi, .recycle_ibi_slot = cdns_i3c_master_recycle_ibi_slot, + .request_mastership = cdns_i3c_request_mastership, + .enable_mr_events = cdns_i3c_master_enable_mastership_events, }; static void cdns_i3c_master_hj(struct work_struct *work) @@ -1535,10 +1679,135 @@ static void cdns_i3c_master_hj(struct work_struct *work) i3c_master_do_daa(&master->base); } +static void cdns_i3c_master_yield(struct work_struct *work) +{ + struct cdns_i3c_master *master = container_of(work, + struct cdns_i3c_master, + mr_yield_work); + + i3c_master_yield_bus(&master->base, master->mr_addr); +} + +static void cdns_i3c_sec_master_defslvs(struct work_struct *work) +{ + struct cdns_i3c_master *master = container_of(work, + struct cdns_i3c_master, + defslvs_work); + struct i3c_master_controller *m = &master->base; + struct i3c_ccc_dev_desc *desc; + struct cdns_i3c_i2c_dev_data *data; + struct i2c_dev_desc *i2cdev; + u32 devs, val, rr, slot; + u32 r0, r1, r2; + u8 saddr; + + devs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK; + master->free_rr_slots = GENMASK(master->maxdevs, 1) & ~devs; + + /* + * We chose to ignore I2C devices received from + * main master and use I2C device info from boardinfo. + * Since I2C device from boardinfo are already + * registered during bus_init, we just use same slot + * and if any I3C device is received in DEFSLVS in that + * place, just move that I3C device to other free slot. + * If there is no free slot, then such I3C devices + * are ignored. + * Master controller driver can chose how to handle I2C + * devices in DEFSLVS and pass only I3C devices list to + * I3C core DEFSVLS processing to handle hotplug and + * I3C device address changes. + */ + for (slot = 0; slot < master->maxdevs; slot++) { + if (!(devs & BIT(slot))) + continue; + + val = readl(master->regs + DEV_ID_RR0(slot)); + if (!(val & DEV_ID_RR0_IS_I3C)) { + writel(readl(master->regs + DEVS_CTRL) | + DEVS_CTRL_DEV_CLR(slot), + master->regs + DEVS_CTRL); + master->free_rr_slots |= BIT(slot); + } + } + + val = 0; + devs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK; + i3c_bus_for_each_i2cdev(&m->bus, i2cdev) { + data = i2c_dev_get_master_data(i2cdev); + if (devs & BIT(data->id)) { + rr = readl(master->regs + DEV_ID_RR0(data->id)); + saddr = DEV_ID_RR0_GET_DEV_ADDR(rr); + if (saddr != i2cdev->boardinfo->base.addr) { + r0 = readl(master->regs + DEV_ID_RR0(data->id)); + r1 = readl(master->regs + DEV_ID_RR1(data->id)); + r2 = readl(master->regs + DEV_ID_RR2(data->id)); + slot = ffs(master->free_rr_slots) - 1; + if (slot > 0) { + writel(r0, + master->regs + DEV_ID_RR0(slot)); + writel(r1, + master->regs + DEV_ID_RR1(slot)); + writel(r2, + master->regs + DEV_ID_RR2(slot)); + writel(readl(master->regs + DEVS_CTRL) | + DEVS_CTRL_DEV_ACTIVE(slot), + master->regs + DEVS_CTRL); + master->free_rr_slots &= ~BIT(slot); + } + } else { + continue; + } + } + writel(readl(master->regs + DEVS_CTRL) | + DEVS_CTRL_DEV_CLR(data->id), + master->regs + DEVS_CTRL); + writel(readl(master->regs + DEVS_CTRL) | + DEVS_CTRL_DEV_ACTIVE(data->id), + master->regs + DEVS_CTRL); + writel(prepare_rr0_dev_address(i2cdev->boardinfo->base.addr) | + (i2cdev->boardinfo->base.flags & I2C_CLIENT_TEN ? + DEV_ID_RR0_LVR_EXT_ADDR : 0), + master->regs + DEV_ID_RR0(data->id)); + writel(i2cdev->boardinfo->lvr, + master->regs + DEV_ID_RR2(data->id)); + master->free_rr_slots &= ~BIT(data->id); + } + + master->base.defslvs_data.ndevs = 0; + desc = master->base.defslvs_data.devs; + devs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK; + + for (slot = 0; slot < master->maxdevs; slot++) { + if (!(devs & BIT(slot))) + continue; + + val = readl(master->regs + DEV_ID_RR0(slot)); + if (val & DEV_ID_RR0_IS_I3C) { + memset(desc, 0, sizeof(struct i3c_ccc_dev_desc)); + rr = readl(master->regs + DEV_ID_RR0(slot)); + desc->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr); + rr = readl(master->regs + DEV_ID_RR2(slot)); + desc->dcr = rr; + desc->bcr = rr >> 8; + master->base.defslvs_data.ndevs++; + desc++; + } + } + + val = readl(master->regs + SLV_STATUS1); + if (!(val & SLV_STATUS1_HAS_DA) || + i3c_master_process_defslvs(m, SLV_STATUS1_DA(val))) { + queue_work(master->base.wq, work); + return; + } +} + static int cdns_i3c_master_probe(struct platform_device *pdev) { struct cdns_i3c_master *master; struct resource *res; + bool secondary; int ret, irq; u32 val; @@ -1579,6 +1848,7 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) spin_lock_init(&master->xferqueue.lock); INIT_LIST_HEAD(&master->xferqueue.list); + INIT_WORK(&master->mr_yield_work, cdns_i3c_master_yield); INIT_WORK(&master->hj_work, cdns_i3c_master_hj); writel(0xffffffff, master->regs + MST_IDR); writel(0xffffffff, master->regs + SLV_IDR); @@ -1590,6 +1860,7 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) platform_set_drvdata(pdev, master); val = readl(master->regs + CONF_STATUS0); + secondary = (val & CONF_STATUS0_SEC_MASTER) ? true : false; /* Device ID0 is reserved to describe this master. */ master->maxdevs = CONF_STATUS0_DEVS_NUM(val); @@ -1610,12 +1881,24 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) if (!master->ibi.slots) goto err_disable_sysclk; + if (secondary) + INIT_WORK(&master->defslvs_work, cdns_i3c_sec_master_defslvs); + writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL); - writel(MST_INT_IBIR_THR, master->regs + MST_IER); + writel(MST_INT_IBIR_THR | MST_INT_MR_DONE, master->regs + MST_IER); writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL); - ret = i3c_primary_master_register(&master->base, &pdev->dev, - &cdns_i3c_master_ops); + if (secondary) { + ret = i3c_secondary_master_register(&master->base, &pdev->dev, + &cdns_i3c_master_ops); + if (!ret) + writel(SLV_INT_DEFSLVS | SLV_INT_MR_DONE, + master->regs + SLV_IER); + } else { + ret = i3c_primary_master_register(&master->base, &pdev->dev, + &cdns_i3c_master_ops); + } + if (ret) goto err_disable_sysclk;