From patchwork Mon Jun 1 10:46:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11581869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BB7360D for ; Mon, 1 Jun 2020 10:47:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30AC520810 for ; Mon, 1 Jun 2020 10:47:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="FMgPkk0N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726383AbgFAKq6 (ORCPT ); Mon, 1 Jun 2020 06:46:58 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:39213 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726110AbgFAKqw (ORCPT ); Mon, 1 Jun 2020 06:46:52 -0400 X-UUID: 06b4e07e9ac94e858c24ff9c73383e81-20200601 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dAJ6kQkuED5Us38miQWm8ZMdm7uCNWRKUju7pfkDY6k=; b=FMgPkk0NMETlIKu/y74w5lJrmsBNW2eGz6UFPhfaiRACdIgMRpFxDlDYDPGvUogtjRwgtN9eRnzCRR+QyZzbM8/oggrP85oYj84R9gNhK9bdYPcbhREICGrqju6cPBHUas/wqJjzCXaONNkWLYJAPa10NOTPas3sfDlQsC2+AtY=; X-UUID: 06b4e07e9ac94e858c24ff9c73383e81-20200601 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 147685464; Mon, 01 Jun 2020 18:46:48 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 1 Jun 2020 18:46:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 1 Jun 2020 18:46:45 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v3 1/5] scsi: ufs-mediatek: Fix imprecise waiting time for ref-clk control Date: Mon, 1 Jun 2020 18:46:42 +0800 Message-ID: <20200601104646.15436-2-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200601104646.15436-1-stanley.chu@mediatek.com> References: <20200601104646.15436-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Currently ref-clk control timeout is implemented by Jiffies. However jiffies is not accurate enough thus "false timeout" may happen. Use more accurate delay mechanism instead, for example, ktime. Signed-off-by: Stanley Chu Reviewed-by: Andy Teng Reviewed-by: Avri Altman --- drivers/scsi/ufs/ufs-mediatek.c | 7 ++++--- drivers/scsi/ufs/ufs-mediatek.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index d56ce8d97d4e..523ee5573921 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -120,7 +120,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); struct arm_smccc_res res; - unsigned long timeout; + ktime_t timeout, time_checked; u32 value; if (host->ref_clk_enabled == on) @@ -135,8 +135,9 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) } /* Wait for ack */ - timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS); + timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US); do { + time_checked = ktime_get(); value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL); /* Wait until ack bit equals to req bit */ @@ -144,7 +145,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) goto out; usleep_range(100, 200); - } while (time_before(jiffies, timeout)); + } while (ktime_before(time_checked, timeout)); dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value); diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index 5bbd3e9cbae2..fc42dcbfd800 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -28,7 +28,7 @@ #define REFCLK_REQUEST BIT(0) #define REFCLK_ACK BIT(1) -#define REFCLK_REQ_TIMEOUT_MS 3 +#define REFCLK_REQ_TIMEOUT_US 3000 /* * Vendor specific pre-defined parameters From patchwork Mon Jun 1 10:46:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11581861 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2ACC960D for ; Mon, 1 Jun 2020 10:47:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 11DEE20772 for ; Mon, 1 Jun 2020 10:47:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="A7SGOhvh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726936AbgFAKq7 (ORCPT ); Mon, 1 Jun 2020 06:46:59 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:29099 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726078AbgFAKqv (ORCPT ); Mon, 1 Jun 2020 06:46:51 -0400 X-UUID: 931f637218ee4d9da891b52c24ce2845-20200601 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ew+RGCuaV2Y1qHcybtLqf6q5Y9tu1r8jPZYZhoV+ToI=; b=A7SGOhvht8wg2PLc3KmLquUNvZkUAe0xivrZoBQTKyf0lXl/uu6Qba4BlrVx4AdRLS+l5FERi3m50Mly/90752MweMcSg+n5EKwPPKpjWhXDpO3P88DpzdpK2SJqmhW/kGefAtQeCwESpORnQj0m/THGDF5ywBQDzmUgINptH44=; X-UUID: 931f637218ee4d9da891b52c24ce2845-20200601 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 85323176; Mon, 01 Jun 2020 18:46:49 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 1 Jun 2020 18:46:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 1 Jun 2020 18:46:45 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v3 2/5] scsi: ufs-mediatek: Do not gate clocks if auto-hibern8 is not entered yet Date: Mon, 1 Jun 2020 18:46:43 +0800 Message-ID: <20200601104646.15436-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200601104646.15436-1-stanley.chu@mediatek.com> References: <20200601104646.15436-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: A3A38F099F244B213021D7716C53E5E2CFB044CE2A7C2B50457DA796582604B42000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org There are some chances that link enters hibern8 lately by auto-hibern8 scheme during the clock-gating flow. Clocks shall not be gated if link is still active otherwise host or device may hang. Fix this by returning error code to the caller __ufshcd_setup_clocks() to skip gating clocks there if link is not confirmed in hibern8 state yet. Also allow some waiting time for the hibern8 state transition. Signed-off-by: Stanley Chu Reviewed-by: Andy Teng --- drivers/scsi/ufs/ufs-mediatek.c | 36 ++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 523ee5573921..3c85f5e97dea 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -178,15 +178,30 @@ static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba, host->ref_clk_ungating_wait_us = ungating_us; } -static u32 ufs_mtk_link_get_state(struct ufs_hba *hba) +int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, + unsigned long max_wait_ms) { + ktime_t timeout, time_checked; u32 val; - ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); - val = ufshcd_readl(hba, REG_UFS_PROBE); - val = val >> 28; + timeout = ktime_add_us(ktime_get(), ms_to_ktime(max_wait_ms)); + do { + time_checked = ktime_get(); + ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); + val = ufshcd_readl(hba, REG_UFS_PROBE); + val = val >> 28; + + if (val == state) + return 0; - return val; + /* Sleep for max. 200us */ + usleep_range(100, 200); + } while (ktime_before(time_checked, timeout)); + + if (val == state) + return 0; + + return -ETIMEDOUT; } /** @@ -221,10 +236,13 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, * triggered by Auto-Hibern8. */ if (!ufshcd_can_hibern8_during_gating(hba) && - ufshcd_is_auto_hibern8_enabled(hba) && - ufs_mtk_link_get_state(hba) == - VS_LINK_HIBERN8) - ufs_mtk_setup_ref_clk(hba, on); + ufshcd_is_auto_hibern8_enabled(hba)) { + ret = ufs_mtk_wait_link_state(hba, + VS_LINK_HIBERN8, + 15); + if (!ret) + ufs_mtk_setup_ref_clk(hba, on); + } } } else if (on && status == POST_CHANGE) { ret = phy_power_on(host->mphy); From patchwork Mon Jun 1 10:46:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11581875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9512660D for ; Mon, 1 Jun 2020 10:47:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E8952077D for ; Mon, 1 Jun 2020 10:47:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qnN/SsqG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726265AbgFAKq6 (ORCPT ); Mon, 1 Jun 2020 06:46:58 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:19803 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725838AbgFAKqv (ORCPT ); Mon, 1 Jun 2020 06:46:51 -0400 X-UUID: 466e592f65ab4626a02a4b3263d9c3fe-20200601 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ckHEM7GVI4e4nimxXTABhbmcvCORVQbBj1jfInkgoAg=; b=qnN/SsqGEXsZ18dqu2xVroL2VBVeEEMEczfG/pDyYCVrhvUl8L5hQh06i+noZP9ZEkh1JUF2WeYH/p2ivFVDzCCNvuUlaxL25TfZj5jJB/T0pZf24humDsJroV31H/4gQeIEuJTkDeLzYTY0SEMkiffNvIbjPxqMuXuloKATZyo=; X-UUID: 466e592f65ab4626a02a4b3263d9c3fe-20200601 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 571622865; Mon, 01 Jun 2020 18:46:48 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 1 Jun 2020 18:46:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 1 Jun 2020 18:46:46 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v3 3/5] scsi: ufs-mediatek: Introduce low-power mode for device power supply Date: Mon, 1 Jun 2020 18:46:44 +0800 Message-ID: <20200601104646.15436-4-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200601104646.15436-1-stanley.chu@mediatek.com> References: <20200601104646.15436-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Allow device power supply to enter low-power mode if device will do nothing to save more power. Signed-off-by: Stanley Chu Reviewed-by: Pengshun Zhao --- drivers/scsi/ufs/ufs-mediatek.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 3c85f5e97dea..5f41b7b7db8f 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "ufshcd.h" @@ -521,6 +522,19 @@ static int ufs_mtk_link_set_lpm(struct ufs_hba *hba) return 0; } +static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm) +{ + if (!hba->vreg_info.vccq2) + return; + + if (lpm & !hba->vreg_info.vcc->enabled) + regulator_set_mode(hba->vreg_info.vccq2->reg, + REGULATOR_MODE_IDLE); + else if (!lpm) + regulator_set_mode(hba->vreg_info.vccq2->reg, + REGULATOR_MODE_NORMAL); +} + static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { int err; @@ -537,6 +551,12 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) ufshcd_set_link_off(hba); return -EAGAIN; } + /* + * Make sure no error will be returned to prevent + * ufshcd_suspend() re-enabling regulators while vreg is still + * in low-power mode. + */ + ufs_mtk_vreg_set_lpm(hba, true); } if (!ufshcd_is_link_active(hba)) @@ -554,6 +574,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) phy_power_on(host->mphy); if (ufshcd_is_link_hibern8(hba)) { + ufs_mtk_vreg_set_lpm(hba, false); err = ufs_mtk_link_set_hpm(hba); if (err) { err = ufshcd_link_recovery(hba); From patchwork Mon Jun 1 10:46:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11581867 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D07E360D for ; Mon, 1 Jun 2020 10:47:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0BC22077D for ; Mon, 1 Jun 2020 10:47:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="rsZ05fmH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726778AbgFAKq7 (ORCPT ); Mon, 1 Jun 2020 06:46:59 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54511 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726101AbgFAKqx (ORCPT ); Mon, 1 Jun 2020 06:46:53 -0400 X-UUID: 2e67097a6b7d4e9490bd6c6466c1ce67-20200601 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ffvmQC8t/hn3+jnrp17+5Ooh5VVEaAxae4PFdHA2xRE=; b=rsZ05fmHpOwcDjggbiz5R/eIbtWkvbp43DuOvfeO8r7e2TBpeVrUCvtlrAxyDDTEqmiBO6H26xHvQbGEJ+OhvayASzTC0OjVBMxOtrKGgtVZubFp3mta2HniCezqzu7sXXEF3pgtO9/EIQ4J1iC3mPlPwlwpaSsjzdrjUMtL5Hk=; X-UUID: 2e67097a6b7d4e9490bd6c6466c1ce67-20200601 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 940390874; Mon, 01 Jun 2020 18:46:49 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 1 Jun 2020 18:46:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 1 Jun 2020 18:46:46 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v3 4/5] scsi: ufs-mediatek: Fix unbalanced clock on/off Date: Mon, 1 Jun 2020 18:46:45 +0800 Message-ID: <20200601104646.15436-5-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200601104646.15436-1-stanley.chu@mediatek.com> References: <20200601104646.15436-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 3B690E7BA8B2E87E504F51C7332648DAE36C3531BDA6C53F261C0676475742F02000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org MediaTek UFS clocks are separated to two parts and controlled by different modules: ufs-mediatek and phy-ufs-mediatek. If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control is not balanced thus unbalanced control also happens to the clocks probed by phy-ufs-mediatek module. Fix this issue by - Promise usage of phy_power_on/off balanced - Remove phy_power_on/off control in suspend/resume vops since both can be handled in setup_clock vops only Signed-off-by: Stanley Chu Reviewed-by: Peter Wang --- drivers/scsi/ufs/ufs-mediatek.c | 60 ++++++++++++++++++++------------- drivers/scsi/ufs/ufs-mediatek.h | 1 + 2 files changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 5f41b7b7db8f..1cc7bea1468b 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -205,6 +205,23 @@ int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, return -ETIMEDOUT; } +static void ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + struct phy *mphy = host->mphy; + + if (!mphy) + return; + + if (on && !host->mphy_powered_on) + phy_power_on(mphy); + else if (!on && host->mphy_powered_on) + phy_power_off(mphy); + else + return; + host->mphy_powered_on = on; +} + /** * ufs_mtk_setup_clocks - enables/disable clocks * @hba: host controller instance @@ -218,6 +235,7 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, { struct ufs_mtk_host *host = ufshcd_get_variant(hba); int ret = 0; + bool clk_pwr_off = false; /* * In case ufs_mtk_init() is not yet done, simply ignore. @@ -228,25 +246,29 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, return 0; if (!on && status == PRE_CHANGE) { - if (!ufshcd_is_link_active(hba)) { - ufs_mtk_setup_ref_clk(hba, on); - ret = phy_power_off(host->mphy); - } else { + if (ufshcd_is_link_off(hba)) { + clk_pwr_off = true; + } else if (ufshcd_is_link_hibern8(hba) || + (!ufshcd_can_hibern8_during_gating(hba) && + ufshcd_is_auto_hibern8_enabled(hba))) { /* - * Gate ref-clk if link state is in Hibern8 - * triggered by Auto-Hibern8. + * Gate ref-clk and poweroff mphy if link state is in + * OFF or Hibern8 by either Auto-Hibern8 or + * ufshcd_link_state_transition(). */ - if (!ufshcd_can_hibern8_during_gating(hba) && - ufshcd_is_auto_hibern8_enabled(hba)) { - ret = ufs_mtk_wait_link_state(hba, - VS_LINK_HIBERN8, - 15); - if (!ret) - ufs_mtk_setup_ref_clk(hba, on); - } + ret = ufs_mtk_wait_link_state(hba, + VS_LINK_HIBERN8, + 15); + if (!ret) + clk_pwr_off = true; + } + + if (clk_pwr_off) { + ufs_mtk_setup_ref_clk(hba, on); + ufs_mtk_mphy_power_on(hba, on); } } else if (on && status == POST_CHANGE) { - ret = phy_power_on(host->mphy); + ufs_mtk_mphy_power_on(hba, on); ufs_mtk_setup_ref_clk(hba, on); } @@ -538,7 +560,6 @@ static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm) static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { int err; - struct ufs_mtk_host *host = ufshcd_get_variant(hba); if (ufshcd_is_link_hibern8(hba)) { err = ufs_mtk_link_set_lpm(hba); @@ -559,20 +580,13 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) ufs_mtk_vreg_set_lpm(hba, true); } - if (!ufshcd_is_link_active(hba)) - phy_power_off(host->mphy); - return 0; } static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) { - struct ufs_mtk_host *host = ufshcd_get_variant(hba); int err; - if (!ufshcd_is_link_active(hba)) - phy_power_on(host->mphy); - if (ufshcd_is_link_hibern8(hba)) { ufs_mtk_vreg_set_lpm(hba, false); err = ufs_mtk_link_set_hpm(hba); diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index fc42dcbfd800..6052ec105aba 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -91,6 +91,7 @@ enum { struct ufs_mtk_host { struct ufs_hba *hba; struct phy *mphy; + bool mphy_powered_on; bool unipro_lpm; bool ref_clk_enabled; u16 ref_clk_ungating_wait_us; From patchwork Mon Jun 1 10:46:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11581857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74385913 for ; Mon, 1 Jun 2020 10:47:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B519207FB for ; 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Mon, 01 Jun 2020 18:46:48 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 1 Jun 2020 18:46:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 1 Jun 2020 18:46:46 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v3 5/5] scsi: ufs-mediatek: Allow unbound mphy Date: Mon, 1 Jun 2020 18:46:46 +0800 Message-ID: <20200601104646.15436-6-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200601104646.15436-1-stanley.chu@mediatek.com> References: <20200601104646.15436-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Allow unbound MPHY module since not every MediaTek UFS platform needs specific MPHY control. Signed-off-by: Stanley Chu Reviewed-by: Peter Wang --- drivers/scsi/ufs/ufs-mediatek.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 1cc7bea1468b..9a4432c9f7dc 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -113,6 +113,12 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba) if (err) host->mphy = NULL; + /* + * Allow unbound mphy because not every platform needs specific + * mphy control. + */ + if (err == -ENODEV) + err = 0; return err; }