From patchwork Tue Jun 2 08:14:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neal Liu X-Patchwork-Id: 11583363 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B32A912 for ; Tue, 2 Jun 2020 08:15:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 330D72077D for ; Tue, 2 Jun 2020 08:15:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Ayp5EPbz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725811AbgFBIPD (ORCPT ); Tue, 2 Jun 2020 04:15:03 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:32303 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725969AbgFBIPD (ORCPT ); Tue, 2 Jun 2020 04:15:03 -0400 X-UUID: ff0a8006aa3c4cccaa61a2de3c5c5dcf-20200602 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MbF+LRzExa+XY/pBtDs6ophTBP7J5P1UhRlTOBIVSUM=; b=Ayp5EPbzHxXWe0W59NethZ6tLIRxQN/3dsP7Nb2bZAh2nImDno9/5J5HztFRF+h0TExeyoUYposQKC2BSFJwk4ysdKl6XOnN7HrB42bLkDYjRzwsikDDq9Ip4OJhaARjUpSslGVFK/QE2XYnenLDO8sKGRhUmQHCfMydCxGV99o=; X-UUID: ff0a8006aa3c4cccaa61a2de3c5c5dcf-20200602 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 587594661; Tue, 02 Jun 2020 16:15:00 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Jun 2020 16:14:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Jun 2020 16:14:58 +0800 From: Neal Liu To: Matt Mackall , Herbert Xu , Rob Herring , Matthias Brugger , Sean Wang , Arnd Bergmann , Greg Kroah-Hartman CC: Neal Liu , , , , , lkml , , Crystal Guo Subject: [PATCH v6 1/2] dt-bindings: rng: add bindings for sec-rng Date: Tue, 2 Jun 2020 16:14:37 +0800 Message-ID: <1591085678-22764-2-git-send-email-neal.liu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1591085678-22764-1-git-send-email-neal.liu@mediatek.com> References: <1591085678-22764-1-git-send-email-neal.liu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add bindings for ARM TrustZone based Security Random Number Generator. Signed-off-by: Neal Liu --- Documentation/devicetree/bindings/rng/sec-rng.yaml | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/rng/sec-rng.yaml diff --git a/Documentation/devicetree/bindings/rng/sec-rng.yaml b/Documentation/devicetree/bindings/rng/sec-rng.yaml new file mode 100644 index 0000000..7f4ae50 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/sec-rng.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# # Copyright 2020 MediaTek Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/rng/sec-rng.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Security Random Number Generator + +description: | + sec-rng is a security random number generator which provides a generic + interface to get hardware rnd from Secure state. The Secure state can be + Arm Trusted Firmware(ATF), Trusted Execution Environment(TEE), or even + EL2 hypervisor. + +maintainer: + - Neal Liu + +properties: + compatible: + enum: + - arm,sec-rng + + method: + description: The method of calling to Secure state + enum: + - smc + - hvc + + method-fid: + description: The function number within the SMC and HVC function identifier + maxItems: 1 + + quality: + description: Estimation of true entropy in RNG's bitstream per 1024 bits + maxItems: 1 + +required: + - compatible + - methods + - method-fid + - quality + +additionalProperties: false + +examples: + - | + hwrng: hwrng { + compatible = "arm,sec-rng"; + method = "smc"; + method-fid = /bits/ 16 <0x26a>; + quality = /bits/ 16 <900>; + }; From patchwork Tue Jun 2 08:14:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neal Liu X-Patchwork-Id: 11583369 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 755AE1391 for ; Tue, 2 Jun 2020 08:15:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5634F207D0 for ; Tue, 2 Jun 2020 08:15:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="kK/IlOt+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726267AbgFBIPM (ORCPT ); Tue, 2 Jun 2020 04:15:12 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:26864 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726185AbgFBIPJ (ORCPT ); Tue, 2 Jun 2020 04:15:09 -0400 X-UUID: 41f700aa76014982907c2e4dcb054db8-20200602 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=L04bYCk8wivAACUMFnflEPSxZwU86UwuPofSNkaCMCU=; b=kK/IlOt+LmAuxs+qhSF4osH/4xMPI0ZIGCblJ1ptxihKEa55ui80wayDtP2Qm4r9TYCmY6fx4S9A4re0x8XZyBuYBBguZOwtNMeiutEo6e+0CBEjJ66dxCH06vEmALJHFOfr1vyL5mBPw7uh1kfJcM0Zd6gv59VP1S6zP+stwMM=; X-UUID: 41f700aa76014982907c2e4dcb054db8-20200602 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1379994272; Tue, 02 Jun 2020 16:15:00 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Jun 2020 16:14:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Jun 2020 16:14:58 +0800 From: Neal Liu To: Matt Mackall , Herbert Xu , Rob Herring , Matthias Brugger , Sean Wang , Arnd Bergmann , Greg Kroah-Hartman CC: Neal Liu , , , , , lkml , , Crystal Guo Subject: [PATCH v6 2/2] hwrng: add sec-rng driver Date: Tue, 2 Jun 2020 16:14:38 +0800 Message-ID: <1591085678-22764-3-git-send-email-neal.liu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1591085678-22764-1-git-send-email-neal.liu@mediatek.com> References: <1591085678-22764-1-git-send-email-neal.liu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 909ABA3B6E64AD00041CC4B3A9BF7D20E656DA2E14FD0DBC349B80906CF174CA2000:8 X-MTK: N Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org For security awareness SoCs on ARMv8 with TrustZone enabled, peripherals like entropy sources is not accessible from normal world (linux) and rather accessible from secure world (HYP/ATF/TEE) only. This driver aims to provide a generic interface to Arm Trusted Firmware or Hypervisor rng service. Signed-off-by: Neal Liu --- drivers/char/hw_random/Kconfig | 13 ++++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/sec-rng.c | 155 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) create mode 100644 drivers/char/hw_random/sec-rng.c diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 9bc46da..cb9c8a9 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -474,6 +474,19 @@ config HW_RANDOM_KEYSTONE help This option enables Keystone's hardware random generator. +config HW_RANDOM_SECURE + tristate "Arm Security Random Number Generator support" + depends on HAVE_ARM_SMCCC || COMPILE_TEST + default HW_RANDOM + help + This driver provides kernel-side support for the Arm Security + Random Number Generator. + + To compile this driver as a module, choose M here. the + module will be called sec-rng. + + If unsure, say Y. + endif # HW_RANDOM config UML_RANDOM diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index a7801b4..04533d1 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -41,3 +41,4 @@ obj-$(CONFIG_HW_RANDOM_S390) += s390-trng.o obj-$(CONFIG_HW_RANDOM_KEYSTONE) += ks-sa-rng.o obj-$(CONFIG_HW_RANDOM_OPTEE) += optee-rng.o obj-$(CONFIG_HW_RANDOM_NPCM) += npcm-rng.o +obj-$(CONFIG_HW_RANDOM_SECURE) += sec-rng.o diff --git a/drivers/char/hw_random/sec-rng.c b/drivers/char/hw_random/sec-rng.c new file mode 100644 index 0000000..c6d3872 --- /dev/null +++ b/drivers/char/hw_random/sec-rng.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + */ + +#include +#include +#include +#include +#include + +#define SMC_RET_NUM 4 +#define SEC_RND_SIZE (sizeof(u32) * SMC_RET_NUM) + +#define HWRNG_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define to_sec_rng(p) container_of(p, struct sec_rng_priv, rng) + +typedef void (sec_rng_fn)(unsigned long, unsigned long, unsigned long, + unsigned long, unsigned long, unsigned long, + unsigned long, unsigned long, + struct arm_smccc_res *); + +struct sec_rng_priv { + u16 func_num; + sec_rng_fn *rng_fn; + struct hwrng rng; +}; + +/* Simple wrapper functions to be able to use a function pointer */ +static void sec_rng_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res) +{ + arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); +} + +static void sec_rng_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res) +{ + arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res); +} + +static bool __sec_get_rnd(struct sec_rng_priv *priv, uint32_t *val) +{ + struct arm_smccc_res res; + + priv->rng_fn(HWRNG_SMC_FAST_CALL_VAL(priv->func_num), + 0, 0, 0, 0, 0, 0, 0, &res); + + if (!res.a0 && !res.a1 && !res.a2 && !res.a3) + return false; + + val[0] = res.a0; + val[1] = res.a1; + val[2] = res.a2; + val[3] = res.a3; + + return true; +} + +static int sec_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) +{ + struct sec_rng_priv *priv = to_sec_rng(rng); + u32 val[4] = {0}; + int retval = 0; + int i; + + while (max >= SEC_RND_SIZE) { + if (!__sec_get_rnd(priv, val)) + return retval; + + for (i = 0; i < SMC_RET_NUM; i++) { + *(u32 *)buf = val[i]; + buf += sizeof(u32); + } + + retval += SEC_RND_SIZE; + max -= SEC_RND_SIZE; + } + + return retval; +} + +static int sec_rng_probe(struct platform_device *pdev) +{ + struct sec_rng_priv *priv; + const char *method; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + if (of_property_read_string(pdev->dev.of_node, "method", &method)) + return -ENXIO; + + if (!strncmp("smc", method, strlen("smc"))) + priv->rng_fn = sec_rng_smc; + else if (!strncmp("hvc", method, strlen("hvc"))) + priv->rng_fn = sec_rng_hvc; + + if (IS_ERR(priv->rng_fn)) { + dev_err(&pdev->dev, "method %s is not supported\n", method); + return -EINVAL; + } + + if (of_property_read_u16(pdev->dev.of_node, "method-fid", + &priv->func_num)) + return -ENXIO; + + if (of_property_read_u16(pdev->dev.of_node, "quality", + &priv->rng.quality)) + return -ENXIO; + + priv->rng.name = pdev->name; + priv->rng.read = sec_rng_read; + priv->rng.priv = (unsigned long)&pdev->dev; + + ret = devm_hwrng_register(&pdev->dev, &priv->rng); + if (ret) { + dev_err(&pdev->dev, "failed to register rng device: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id sec_rng_match[] = { + { .compatible = "arm,sec-rng", }, + {} +}; +MODULE_DEVICE_TABLE(of, sec_rng_match); + +static struct platform_driver sec_rng_driver = { + .probe = sec_rng_probe, + .driver = { + .name = KBUILD_MODNAME, + .owner = THIS_MODULE, + .of_match_table = sec_rng_match, + }, +}; + +module_platform_driver(sec_rng_driver); + +MODULE_DESCRIPTION("Security Random Number Generator Driver"); +MODULE_AUTHOR("Neal Liu "); +MODULE_LICENSE("GPL");