From patchwork Tue Jun 2 11:53:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32AF91392 for ; Tue, 2 Jun 2020 11:55:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A7B5207ED for ; Tue, 2 Jun 2020 11:55:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rPaW7gDQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727026AbgFBLy0 (ORCPT ); Tue, 2 Jun 2020 07:54:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726267AbgFBLyX (ORCPT ); Tue, 2 Jun 2020 07:54:23 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03A47C061A0E; Tue, 2 Jun 2020 04:54:23 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id l10so3082595wrr.10; Tue, 02 Jun 2020 04:54:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2wtQFXbmzC4/d8oVsOGWU0M31JIOAZfPwOO9JlNgV6A=; b=rPaW7gDQP90eaYUWfocrZarTDq3foj9NBI2+vdBuQtKeJ8kaLi9E57oxNIcWynULgJ DTK2xwiglZZ62JPy3WayfYStIGIH7XqJtVpUq6BYu/j58La3U8Lmty5vRdZKVXglrBIR 1yVqxjD35wsNWZ4ihE1Kk7yeCjv26bepc3JcTWTaBkERpJMOqV5QJZSTbAArI7OaF7M+ 5NzlaWwVJe2MJ2MktUEVtBx0XMvvu4B0wddNtVeWRKzt7at4/Kjj8SKNXQGRox1tNm25 3cIb77wFxldAGH1AOLF5Nn0PvE9C1XO2pRmEuq/Q8ynLtbdc7FylSeVxpypJkikHWz6x uT0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2wtQFXbmzC4/d8oVsOGWU0M31JIOAZfPwOO9JlNgV6A=; b=d94DqipOuC7GSs2iBhwxJJZya/4BDeY5KCdSQnBp3xbNUKnWG2zNWLaYQYvZktJaY3 srLErSSUQKbYEBM4h20dQunfyFSnhNLShNUwS+xIa5nMzVjLrgaifzOBkKe4LxGgQXWy zMpoQP1Utnv7s2/HBE4XBxXlzKRYZ1QJ3DzB3SoMTjUcECwaI0+QJfwrC28HwKmgbv36 QNt4TTBRqimd14aQfiEKdcDUMkW6BFPjIWPHyVVbNZiY0hkXT8SlsLiVTyfEE2zGfwYC Lez/KBn9Y+5YesG0YpKnAsk6Rjz7Do9QZM1XS93JPJYppwCRZ7LWCnU1GpKyP8Gd5fFj BG0A== X-Gm-Message-State: AOAM532mE3El+mC4On3mlNf90/Kc0fHf0Wv9lVYCYw1jjTlPaCurJZ3I S4Cg4SCOLaIwqO2TQx96UIA= X-Google-Smtp-Source: ABdhPJyOdDG9ZJJFvykD+EoExCrvxVZTm1q7+KjEbm5cg4u0HptGlA9r8y73NrghpR5k7s5CMUPquQ== X-Received: by 2002:a5d:4ec3:: with SMTP id s3mr28049104wrv.103.1591098861685; Tue, 02 Jun 2020 04:54:21 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:21 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Sham Muthayyan , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 01/11] PCI: qcom: Add missing ipq806x clocks in PCIe driver Date: Tue, 2 Jun 2020 13:53:42 +0200 Message-Id: <20200602115353.20143-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Aux and Ref clk are missing in PCIe qcom driver. Add support for this optional clks for ipq8064/apq8064 SoC. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5ea527a6bd9f..4bf93ab8c7a7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; struct clk *phy_clk; + struct clk *aux_clk; + struct clk *ref_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_clk)) return PTR_ERR(res->phy_clk); + res->aux_clk = devm_clk_get_optional(dev, "aux"); + if (IS_ERR(res->aux_clk)) + return PTR_ERR(res->aux_clk); + + res->ref_clk = devm_clk_get_optional(dev, "ref"); + if (IS_ERR(res->ref_clk)) + return PTR_ERR(res->ref_clk); + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) return PTR_ERR(res->pci_reset); @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); + clk_disable_unprepare(res->aux_clk); + clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->core_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable core clock\n"); + goto err_clk_core; + } + ret = clk_prepare_enable(res->phy_clk); if (ret) { dev_err(dev, "cannot prepare/enable phy clock\n"); goto err_clk_phy; } - ret = clk_prepare_enable(res->core_clk); + ret = clk_prepare_enable(res->aux_clk); if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; + dev_err(dev, "cannot prepare/enable aux clock\n"); + goto err_clk_aux; + } + + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_clk_ref; } ret = reset_control_deassert(res->ahb_reset); @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; err_deassert_ahb: - clk_disable_unprepare(res->core_clk); -err_clk_core: + clk_disable_unprepare(res->ref_clk); +err_clk_ref: + clk_disable_unprepare(res->aux_clk); +err_clk_aux: clk_disable_unprepare(res->phy_clk); err_clk_phy: + clk_disable_unprepare(res->core_clk); +err_clk_core: clk_disable_unprepare(res->iface_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); From patchwork Tue Jun 2 11:53:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA09C1392 for ; Tue, 2 Jun 2020 11:55:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE08E2074B for ; Tue, 2 Jun 2020 11:55:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="H5iPQh7P" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726450AbgFBLyc (ORCPT ); Tue, 2 Jun 2020 07:54:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLy0 (ORCPT ); Tue, 2 Jun 2020 07:54:26 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B607C061A0E; Tue, 2 Jun 2020 04:54:26 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id c71so2622066wmd.5; Tue, 02 Jun 2020 04:54:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m/L0NRU1j/c6I13faHhGrI6qUdNFYftXq3aP75qQONs=; b=H5iPQh7P5hbp3kjJ/ZsGNjlnY9VHbU2mRjDwUmIDxFc943pGU5IpOfFXdQUReTCFL5 Q3v/lJt9hhNAgpSqw6Nb8nnhV8lz8i61rAHRBK9FLVWui7IaCM6W1ccn+X/Nds70uvhQ PxpSa8lty0pnFoIo+4HA6JZK9ZyuM/cA1Wgulrz+ncMC+dIBToCoFh83blqsNstcjRde R8a/sOW8L2bsDnqurBRISTK+dLhLC7+ttQArO15xrzp1dszvdF0T6E141u7XaxV5O+SO ZLisW3l94GHdRrgmSCap3uzygJKTAKvBN1GYAe//R9Pff3seY6cVh/qpb/1c2zoPlN9O 9Ynw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m/L0NRU1j/c6I13faHhGrI6qUdNFYftXq3aP75qQONs=; b=g+IvGfnS8LjWQm0O+QjX0o0+RYUpeyp0FJVyy51ZOUzmfjwICnMd62q9+mRZXnvDRp 3uke//dq/LAEC9atyIBpkYXC09++005tWwu//NvzzezXDRXW388MrGnR4Q/Na8tnxfdE WIV0YBWit53/sLu/GvKRrru4La9n0xw1lWGAwUwSqiY8uiEy3iWGXBU4Zkr4pAriAsED 3+cXmA0Vu70LA2d3dymAmnsT2n12B/Aw5WZIMcKMqy02pNGID2ipAA1NHcb1rFUylaNR Bs3RbNRwWXTf0MiN1NqGyMTVxy+ZhhePHUi8htGj6aEE4xyJemfsIYM1KHDjIzNmbOFr RGLA== X-Gm-Message-State: AOAM532Hz+4Ntnp3YT1czsF2dKJfp5q0VtpkNAMa0XBCbvLlPXzo2ZZv D0fxDJb38SMKwlE/QKwaYng= X-Google-Smtp-Source: ABdhPJxQZlzTjxZlSO06cWa2BcZm5j8JiMMqRfavfmoJaaQ99uKt+xUFJroxOnoTFPx+OfwUVCXHSA== X-Received: by 2002:a05:600c:4410:: with SMTP id u16mr3788930wmn.88.1591098865243; Tue, 02 Jun 2020 04:54:25 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:24 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/11] dt-bindings: PCI: qcom: Add missing clks Date: Tue, 2 Jun 2020 13:53:43 +0200 Message-Id: <20200602115353.20143-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document missing clks used in ipq8064 SoC. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Tue Jun 2 11:53:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583683 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43EFE1392 for ; Tue, 2 Jun 2020 11:54:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 24204207D8 for ; Tue, 2 Jun 2020 11:54:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IF8EoKhE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727788AbgFBLyb (ORCPT ); Tue, 2 Jun 2020 07:54:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726267AbgFBLy3 (ORCPT ); Tue, 2 Jun 2020 07:54:29 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0220C061A0E; Tue, 2 Jun 2020 04:54:29 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id g10so2627251wmh.4; Tue, 02 Jun 2020 04:54:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s9klwDUAQHUdrbunE/kS0tb+TnD6OrjCFpNB//xZIAs=; b=IF8EoKhEoV6G2tqq6uLVNzyik+LsxddjgENfK5q27xfR6rvBQ0AWqO0R51+rqquoh5 6UTt1ketVQz1Dy+lQdPNeyVdAxWo6kHAJdnfr43IP+93VwysWqQSmCsMqOjg/eC15j1y XDOh8aqzswhdiNHEB6/JXb7sBl9QUot8Lf8OpJMk5+PJF4tv8f6uDBAAfiJOyZxiY8T5 fXweBCzhyKpNVXp1zc/uddB3Mmhp9JyGP9P2MNdrfGR7CoXe25s/7dF/w3GqFnWGcYMc PFuZDy/qVlQEIdFOqTOzCjieEpge2RLlRMKDuNCZGIUxFVjQ8RHcR/jLGEJ12NSDSR2U Kozw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s9klwDUAQHUdrbunE/kS0tb+TnD6OrjCFpNB//xZIAs=; b=hnzwkDwa6AyW65W8tw5kAj5TwniC/uATLYRERHmBTX5R5C9AaaweyTMjHRs1mEudJv BncuR5D15F3J8TLojol9GBIih2CucilruXhz7+JEfIACFl6tqgr7MQBBNxy8K1QKiNem Yz6e7GuWvyZ1NtXa+/L8ndg7g3C9gJaXFANqzOfrFyHtiwGNq0wzq1R8kZLcXzGyoi+D vp59O7ATGMUkSpxgptVL++Uwiocey91O14afp9Z9Q7amf2rkHt0f5gTwm1uvctJ7nHC2 LRcVX9i1oYt+tljV0Xou0SD7s2eeUJ7tE8QqARpKDqV+GJ/ddB08VIrBNrsY0dAKYc2N T2xw== X-Gm-Message-State: AOAM531rTtBCY2G7CeyzXDS2T4m2POg33SeXyM+b3O+8H7UfAQoiq22J TdB9LP8J3SkK9IzVjUsahLs= X-Google-Smtp-Source: ABdhPJznN0h7KwcJtw/jowMO0Vfn2BJVS4GYS2C93zi1okD4NPM2j9RfwMPJWBRUshgfb1Yo9mNZYA== X-Received: by 2002:a7b:c0d9:: with SMTP id s25mr4037720wmh.175.1591098868301; Tue, 02 Jun 2020 04:54:28 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:27 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Abhishek Sahu , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 03/11] PCI: qcom: Change duplicate PCI reset to phy reset Date: Tue, 2 Jun 2020 13:53:44 +0200 Message-Id: <20200602115353.20143-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhishek Sahu The deinit issues reset_control_assert for PCI twice and does not contain phy reset. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4bf93ab8c7a7..4512c2c5f61c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); + reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); @@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Tue Jun 2 11:53:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583715 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EEBF9739 for ; Tue, 2 Jun 2020 11:55:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6A0F2074B for ; Tue, 2 Jun 2020 11:55:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EpGEXjAV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728234AbgFBLzK (ORCPT ); Tue, 2 Jun 2020 07:55:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727818AbgFBLyc (ORCPT ); Tue, 2 Jun 2020 07:54:32 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6E1BC061A0E; Tue, 2 Jun 2020 04:54:32 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id f5so2816091wmh.2; Tue, 02 Jun 2020 04:54:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0T+25FzC3m+ZCfSnTnyTsPpwm0TEOUYS6HI+FaVLFf0=; b=EpGEXjAVbgpT2SQTvfPorH9Jt3XX4IeCDlZVxZe+PQESUTeCi+9NJVgEq634nwPMrx YSOlpYHLH/he0+MC/MOR8WRTorq4lau2zj5+TealPjfnt1kDxk++GJoLGFX5trMfp6qL 5QJwy2Yfz6rxx2lzwHjFpKnbk01SJvfyqcfGX5c04rnuftniD5s74ZzEKiNLA/fZnh/H qNz641jfimWPrZcslMTjTppHhi8tqsfEdCHCUp7U3OqAHNLmjW7UvAAONT5J5ZFdJVbo P+HvUONWn5gPydgMw+2wM9HS/PuGcRoCDs4i90kjBS7IG/H+fYBaeguJZBdi40Q9nidU 3O6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0T+25FzC3m+ZCfSnTnyTsPpwm0TEOUYS6HI+FaVLFf0=; b=nJzcifOCSmmV4ODP+lnpIUmw9vYlhX+a4hSL4n7O4WByuj9wBCXIwZOk5nnaidpwP0 DVGUcxf+kF4CMFKgym7FhoUMcLroM1hSpydnjYYc+iGq7YnKa5ADi4VIDyuqE4kNOhdJ aoxUQM3QHoctPuHDGKOhVqpscpACTmKkvqS6itjIMdw5IlIuFAoRgKHLu9gas9NoTWlC 6CulqWpuwKQNn7WrRoJBx8qQoVLIzFcARl/Fu8lUAVyfFmjt9hNLkFoIkdoFkXOzxCwG InKh2iZ+xd5U9VmwvZz/ccJKqsYsHoQH73SxExiMId161oAz9XI1v9E0RhWgFTuSoqzS 7bZQ== X-Gm-Message-State: AOAM532IkXlDIFVNn3ChMtHIGkV3ftlarkEW6Ycz99XzIOezM2c7IcdU tAtdl6Kgh2ECMtZUXsD4GLc= X-Google-Smtp-Source: ABdhPJyrLJafVl3fMd4w2rhOS1xKBiSk9UehJodvGQ+/mZWt012vRSkIi5Oupuo+3wj83gvwrLca+g== X-Received: by 2002:a1c:dfd7:: with SMTP id w206mr3723154wmg.130.1591098871366; Tue, 02 Jun 2020 04:54:31 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:30 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Sham Muthayyan , stable@vger.kernel.org, Rob Herring , Philipp Zabel , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 04/11] PCI: qcom: Add missing reset for ipq806x Date: Tue, 2 Jun 2020 13:53:45 +0200 Message-Id: <20200602115353.20143-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ Reviewed-by: Rob Herring Reviewed-by: Philipp Zabel --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4512c2c5f61c..4dab5ef630cc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot deassert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); From patchwork Tue Jun 2 11:53:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583711 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 561A41392 for ; Tue, 2 Jun 2020 11:55:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3CFB820772 for ; Tue, 2 Jun 2020 11:55:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OPGilbj7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728080AbgFBLyh (ORCPT ); Tue, 2 Jun 2020 07:54:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLyg (ORCPT ); Tue, 2 Jun 2020 07:54:36 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 190CEC061A0E; Tue, 2 Jun 2020 04:54:36 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id x6so3056986wrm.13; Tue, 02 Jun 2020 04:54:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ioo9tN1eVsbgycuXVtXW3j/mdJh9pHsUFw60B6xaAJg=; b=OPGilbj7UjSYk9ZchqbkyFuPkLvGV2w71w6eB3yzbzyhyzclPQ6a+w1TnzeVAX8FEd DOgv6gdm72XTP6dUvVblAlud4o6+I7AN/J3h65S3yNZXcuaQNSXJvhIhsGjHVv8BGCI3 690nYPxqXv4aPnkxF8lfjnJwkruYOkCEGMZ7jOKpdC+CMrY1kLZ9ZgbCgNM1frYrxOqu Cf2KkUccSmBBw0BHUe7Pc1M2lNkXGAeIAXPEXoo3pZpsYi3IIMBvDTs709pU7BaR4xn0 s6Di564UkLwo3zbedA3SlEkJD5KaLcQElFO96G5P1sVAU0OxTuFucb6jz+Oi+efzHxNX 3lhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ioo9tN1eVsbgycuXVtXW3j/mdJh9pHsUFw60B6xaAJg=; b=q6DKXQFWAuB7B4cOnW/Hl9h11gJ7O0RbTo9uxUnMlK+PU5JMw0zPvVYxnTU/gyx4tm rkefGlqolE1y00IjnonaPaATx5z1YE08c51EKKQVks+fynKaEgV0ljLd7/2bp10bbzWF zaKEcG6xphBSUjemgcLE5Rvdt5ECvrmXCAugeEokSWyLw559G3kOFuhCJU9hSDoMM4kc Ig12VJqAHXgZJfMl5XAjpMfL6vWOm5rz6MrwswEqhb0sbbj1mtLOjwj2f3Z85YGaQoYm fqjjdrqV4KTUsOOYdDlEfIMAV04e0mbtRkasy9gB/w8DoFOTqfaiWbPf/mYEapWXip9+ 3H5A== X-Gm-Message-State: AOAM530buXqNc19f153JRqLj6ccbUQy0zu9cbGRX8OGZnYVhWyXw1y4B LCn4Qu/gS/DxHKkJ+n6Cy/E= X-Google-Smtp-Source: ABdhPJxWvG6gP1xb6MNdtvpUdYbBOn0bBHaTVxTJUwCJtK+32mQrYuenIXkSvpxLIpAmxnmu1V9dpQ== X-Received: by 2002:a5d:4484:: with SMTP id j4mr25594162wrq.325.1591098874758; Tue, 02 Jun 2020 04:54:34 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:34 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 05/11] dt-bindings: PCI: qcom: Add ext reset Date: Tue, 2 Jun 2020 13:53:46 +0200 Message-Id: <20200602115353.20143-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document ext reset used in ipq8064 SoC by qcom PCIe driver. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Tue Jun 2 11:53:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583709 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D8AA739 for ; Tue, 2 Jun 2020 11:55:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00E2A20772 for ; Tue, 2 Jun 2020 11:55:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tn6vtT1B" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728188AbgFBLyk (ORCPT ); Tue, 2 Jun 2020 07:54:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLyj (ORCPT ); Tue, 2 Jun 2020 07:54:39 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AD24C061A0E; Tue, 2 Jun 2020 04:54:39 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id c71so2622662wmd.5; Tue, 02 Jun 2020 04:54:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zEaDqgFgLdCp9SI9RIDjLkOE1A27X8Da9cpu+tesTho=; b=tn6vtT1BOg1c5dw6odRQ7kq4VYwnfzeoWA+Xgb7N6wc7TQZjrFxpWeqUjtVExiVqYD s/S5vL3Y+jRn54+ShGhRfQgYkvnHc6yFWXFk24IcVIKsQFGkjn63zP5LYlJ0vDeyTrrw bho8dEKPy57r/XZO1Yj3PcV0QXgXV2IVLQLbAIJB6Qk9wAvEsvaZWY0FzXnu8AG03tZo xjYBhfKCemJy7zsIokCslHeHoTiCOOKyCsJDc25gY825we/L7qNRoNviLReo9J3wFa+i EgZR6tDg6OP9DPu9RY3XqWpSI+rY/xC3PDC5fG3yKbKsR9rpYLc0Vb4gEMutcA6g47Sw g3vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zEaDqgFgLdCp9SI9RIDjLkOE1A27X8Da9cpu+tesTho=; b=YY7mEQnSf6J8musl3lxHaRhsdKINfCwjvv0oQ3ZURyQo204/KBPqemYlmG17TKxfdM 9YwhkGe5evvCwAQZazXX2W9F/At5/MZeOGTmu0M/BzAdmaNRRXN6MCYBjWtZjCBUMcG2 8mvOsXrF2lLCabxobwyT8pnpwY1V4D2rOwRb9wVwQKRtziIC4bHLRtomXjZd2t1arohr bmpMMJjWoUUQ1mu1NDygaNwykIuKJPbFaUbUqm+phePeov2wBfbDv86+GJueq8CWV94S skLEV5RXbmNVgegz77nCPNOarF0uV6z5vFY6qPHclnzyuPC87qP/b1WxoWLFF0nscq+T sFzg== X-Gm-Message-State: AOAM533faDDTh524WaXP8thn5U/RcYkMRrBeQRJJg5g1iL2J5/84IQh6 NcMSIff8WMfBevnkwQGiotU= X-Google-Smtp-Source: ABdhPJzJFCcEKjVMBGzIsz5GSsptq1V5VMDiGI+i6jJcooX6TziGa/laJm73FlWQ3NpKvjhXp/I1EQ== X-Received: by 2002:a1c:b385:: with SMTP id c127mr3632722wmf.132.1591098878210; Tue, 02 Jun 2020 04:54:38 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:37 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 06/11] PCI: qcom: Use bulk clk api and assert on error Date: Tue, 2 Jun 2020 13:53:47 +0200 Message-Id: <20200602115353.20143-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework 2.1.0 revision to use bulk clk api and fix missing assert on reset_control_deassert error. Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 131 +++++++++---------------- 1 file changed, 46 insertions(+), 85 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4dab5ef630cc..f2ea1ab6f584 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -84,12 +84,9 @@ #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; - struct clk *core_clk; - struct clk *phy_clk; - struct clk *aux_clk; - struct clk *ref_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (ret) return ret; - res->iface_clk = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface_clk)) - return PTR_ERR(res->iface_clk); - - res->core_clk = devm_clk_get(dev, "core"); - if (IS_ERR(res->core_clk)) - return PTR_ERR(res->core_clk); - - res->phy_clk = devm_clk_get(dev, "phy"); - if (IS_ERR(res->phy_clk)) - return PTR_ERR(res->phy_clk); + res->clks[0].id = "iface"; + res->clks[1].id = "core"; + res->clks[2].id = "phy"; + res->clks[3].id = "aux"; + res->clks[4].id = "ref"; - res->aux_clk = devm_clk_get_optional(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + /* iface, core, phy are required */ + ret = devm_clk_bulk_get(dev, 3, res->clks); + if (ret < 0) + return ret; - res->ref_clk = devm_clk_get_optional(dev, "ref"); - if (IS_ERR(res->ref_clk)) - return PTR_ERR(res->ref_clk); + /* aux, ref are optional */ + ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); + if (ret < 0) + return ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) @@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - clk_disable_unprepare(res->phy_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->aux_clk); - clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->iface_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->core_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; - } - - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; - } - - ret = clk_prepare_enable(res->ref_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ref clock\n"); - goto err_clk_ref; - } - ret = reset_control_deassert(res->ahb_reset); if (ret) { dev_err(dev, "cannot deassert ahb reset\n"); @@ -352,48 +311,46 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) ret = reset_control_deassert(res->ext_reset); if (ret) { dev_err(dev, "cannot deassert ext reset\n"); - goto err_deassert_ahb; + goto err_deassert_ext; } - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - - /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); - ret = reset_control_deassert(res->phy_reset); if (ret) { dev_err(dev, "cannot deassert phy reset\n"); - return ret; + goto err_deassert_phy; } ret = reset_control_deassert(res->pci_reset); if (ret) { dev_err(dev, "cannot deassert pci reset\n"); - return ret; + goto err_deassert_pci; } ret = reset_control_deassert(res->por_reset); if (ret) { dev_err(dev, "cannot deassert por reset\n"); - return ret; + goto err_deassert_por; } ret = reset_control_deassert(res->axi_reset); if (ret) { dev_err(dev, "cannot deassert axi reset\n"); - return ret; + goto err_deassert_axi; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_deassert_ahb; - } + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret) + goto err_clks; + + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~BIT(0); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + + /* enable external reference clock */ + val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); + val |= BIT(16); + writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; +err_clks: + reset_control_assert(res->axi_reset); +err_deassert_axi: + reset_control_assert(res->por_reset); +err_deassert_por: + reset_control_assert(res->pci_reset); +err_deassert_pci: + reset_control_assert(res->phy_reset); +err_deassert_phy: + reset_control_assert(res->ext_reset); +err_deassert_ext: + reset_control_assert(res->ahb_reset); err_deassert_ahb: - clk_disable_unprepare(res->ref_clk); -err_clk_ref: - clk_disable_unprepare(res->aux_clk); -err_clk_aux: - clk_disable_unprepare(res->core_clk); -err_clk_core: - clk_disable_unprepare(res->iface_clk); -err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); return ret; From patchwork Tue Jun 2 11:53:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583689 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C94F9739 for ; Tue, 2 Jun 2020 11:54:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0F97207ED for ; Tue, 2 Jun 2020 11:54:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YpNtAv4G" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728381AbgFBLyo (ORCPT ); Tue, 2 Jun 2020 07:54:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLyn (ORCPT ); Tue, 2 Jun 2020 07:54:43 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE1EDC061A0E; Tue, 2 Jun 2020 04:54:42 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id j198so2090265wmj.0; Tue, 02 Jun 2020 04:54:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bzzvhyMzVv3Z/fV4OGF2FsiFFhxIni2+nKg6tj7GTUk=; b=YpNtAv4G1J9EhIQAuvAxQKxZUjgDyaIVEKJka1yRu2puEw14PMLlqrRYCp3Grg+q8d cOcnlnxU9wNAsbiDG0ychniBjwGE44wowKoOXH5FmDnghzHSIkPW93KX2KogrL1fkgk0 IRGaCivEJKhMcGzsnxQQ4nCL8Y5XokFhzEm/sr2nrnJKDWntLpfOrqZyprwSZWhU+WYZ 1G38fuKvFJ2XGqbG2v4nqjdP+ezaN47WHUeupKNd97du8c/f1WCzYpuJdAFsK3jQKsU8 gEJeuSyscKEpRj8SpWgWTk03gG0vn/nWAIG8Gk102VLEHMc1j+KPp0RYjhsVTemhEydF OzWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bzzvhyMzVv3Z/fV4OGF2FsiFFhxIni2+nKg6tj7GTUk=; b=uMj/G7Gas7xMsNIAsdDgyRHLsqK33Z+lPjCEmg9z96poYBcGwZsar8Demz/vNa8AXg Rsip69idfDIfCDViORhetyzPKkz0vdB16hvd8AID+AvfaVvj9QnEGwy7TRnbkXFQL1Gj 2sIPGkAEatUP7GHaTl6jEQx2Zi6hpKJtCQ1XvA+wgRmLnb1CCM9t30apMUQ0xul1D/nQ vsh0n00/nJob9/6lxLLGkg8w+tnroC0AszeZcHOFk4zp/tQSGk/O13hxNbMwir+t7aLe qN3/yrC3SfKhBnwO/g+h9WTTxmEKQCue5TJzej9eg0Q8XhlzB04B84JLC7nLLvYerjrG G1gw== X-Gm-Message-State: AOAM533z0ZezUJDg7VfU24Fmcz226HwXSKx9xIbYGTYA4QoZXF+y7/VU st8dhKZRVXo4vrENXjPEpOc= X-Google-Smtp-Source: ABdhPJxqAqkvZJ2uNToTjmLSaK+Xexa4SVvEuSg9juTmHudR/Ir4Ow/eSAfYI6Rb4xJAn0viuw0Sfg== X-Received: by 2002:a7b:c204:: with SMTP id x4mr3762230wmi.22.1591098881483; Tue, 02 Jun 2020 04:54:41 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:40 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , stable@vger.kernel.org, Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC Date: Tue, 2 Jun 2020 13:53:48 +0200 Message-Id: <20200602115353.20143-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization needed on some ipq8064 based device (Netgear R7800 for example). Without this the system locks on kernel load. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f2ea1ab6f584..f5398b0d270c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -46,6 +46,9 @@ #define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C +#define PHY_REFCLK_SSP_EN BIT(16) +#define PHY_REFCLK_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -77,6 +80,18 @@ #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) ((x) << 24) #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + struct device_node *node = dev->of_node; u32 val; int ret; @@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(120) | + PCS_SWING_TX_SWING_LOW(120), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); + } + /* enable external reference clock */ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); val |= BIT(16); From patchwork Tue Jun 2 11:53:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583707 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2640114F6 for ; Tue, 2 Jun 2020 11:55:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0EB4C208C9 for ; Tue, 2 Jun 2020 11:55:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DbXaFmpO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728397AbgFBLyr (ORCPT ); Tue, 2 Jun 2020 07:54:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLyq (ORCPT ); Tue, 2 Jun 2020 07:54:46 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5B02C061A0E; Tue, 2 Jun 2020 04:54:45 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id x14so3129578wrp.2; Tue, 02 Jun 2020 04:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z+l2SJlxwdbSAeCvbGCXrANrMH1wFyQWwIwcm1pjtOc=; b=DbXaFmpOXaej68wvKy6x7avnN34Acp0tItjNhciOy2gXjpPK/BsXdfZLGIuxK1zqMT xdokpN7xBSVhM1CTECVDQyNH9ibiyHvdbPPE8tekOxUyhj5AL4gn1fqd3jmYCZGmtngP 1GJjf95ohwo27YTjHfvBRqD0haQY1TEtYJvwamzcAoRx28sdSZ8YUL/tARjw0TOLfXvE KuzMPTGtH0ZdkXXDaLR3SDFxGY/913jVo8ViS+Kdb8DVqmqUuKkMEQWTivoV3I3Xt46y 2qn8iv31U1Qc2NVxfRvg7mlLR+InYxwytfSXJH2eyoEi6SUT28xh1LsRALk+sJx0o578 wTqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z+l2SJlxwdbSAeCvbGCXrANrMH1wFyQWwIwcm1pjtOc=; b=X23IR+MolW2vttpsuyOMcvfD7zmzzDs++ZjU19w7aznpa/v0JrVmTqh94s0QHTvRr4 0SuhNsA2FhHfZH1MrI3Tp0E0/fxvqWoKrwsr07HxM/lUfznGLkTED6qC2Z8rByQ4GvqZ 7FBD64zikyDPGhjdVx8a5iuhKth7gPAdFfeNoOk2KDjj5lxoa2eXaAr5dZYxe/fs0ztX PwcPizHBurk2kMyTsE1XyN8I8n/kk5ql9M0EBj+D1idpIPeeyNjRvAeheI/Ijy+tgQ8d s+k6O2sxOpYctVMEnlsRMaYEJzmbdfdNHOBYkO9VzHlmr9RARcXP9MJIc2StceeDSfVK ANNw== X-Gm-Message-State: AOAM5336j+AmVFCXz/Wlp/2hvW2V/EJWYAZw38eCEZRfdxBZ5R6ymc7Z 1yPAPQEXcPeJAEAGn3EZZZ4= X-Google-Smtp-Source: ABdhPJxP9xFEYNyePNazFXlEVaWP1HSQ84aDSR/HnYH3YOSvCQMEtWfyCzfyqtGx14wv2IxeIriI8Q== X-Received: by 2002:a5d:54c7:: with SMTP id x7mr22768920wrv.162.1591098884594; Tue, 02 Jun 2020 04:54:44 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:44 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Sham Muthayyan , stable@vger.kernel.org, Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 08/11] PCI: qcom: Add support for tx term offset for rev 2.1.0 Date: Tue, 2 Jun 2020 13:53:49 +0200 Message-Id: <20200602115353.20143-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add tx term offset support to pcie qcom driver need in some revision of the ipq806x SoC. Ipq8064 needs tx term offset set to 7. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ --- drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f5398b0d270c..2cd6d1456210 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -45,6 +45,9 @@ #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 #define PCIE20_PARF_PHY_CTRL 0x40 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) + #define PCIE20_PARF_PHY_REFCLK 0x4C #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) @@ -374,9 +377,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); } + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + /* set TX termination offset */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; + val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + } + /* enable external reference clock */ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); + val &= ~PHY_REFCLK_USE_PAD; + val |= PHY_REFCLK_SSP_EN; writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); /* wait for clock acquisition */ From patchwork Tue Jun 2 11:53:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583693 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 601A41392 for ; Tue, 2 Jun 2020 11:54:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47DFE20835 for ; Tue, 2 Jun 2020 11:54:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ea6DeRGE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728422AbgFBLyt (ORCPT ); Tue, 2 Jun 2020 07:54:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLyt (ORCPT ); Tue, 2 Jun 2020 07:54:49 -0400 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AEC3C061A0E; Tue, 2 Jun 2020 04:54:49 -0700 (PDT) Received: by mail-wm1-x343.google.com with SMTP id f5so2816902wmh.2; Tue, 02 Jun 2020 04:54:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qi0pxCVqozd5V1/C140EBqHG2/fFl/8biYimGdOF39g=; b=Ea6DeRGE2KT1Qqmq3jiwAFlEKfxaL6cvAKSsaHQe0qJQJKriCeT6ufldt/bZNNjQfJ yQ/nFOzxOSkLPtd7MeLQbasnO/Ck/x3m0jqSQPJgn5EHOOh0qKKPtbC3utC5WizyuhT7 80TdFRe//3FOefXmdyUuSNvzt+Hm1sOd4bwyWNJ70Pm/qRLu9qiiJvGgiJUapWS5K4NU tawisumfIJXZVQHThtq/lsh1u/Ws/Hgj9dapHg7keed/rX80KuhSl9X29JTO7Lo1hbVA X8pH6Oh2uajXysk7IF6raUA7/HmmPBKC8Invr9dvqy4Ii2cbxs6kRLVHs7CfxYqmJZF+ BDYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qi0pxCVqozd5V1/C140EBqHG2/fFl/8biYimGdOF39g=; b=L2P1lyKZysXUFrtYDi+l6apNVJe/BRjCJXHgBOMuAazokwQqx81Pq5xe7R/SIKqZF2 u8DYgod2f+a1HKy6PtHdiVMZfRtd4N1uODEO/Sfszo0atUPe/iDw4upYqMC6uHYnSSR7 Ect8CGxq5uPoW7ppNzmd2TXaGg+BgxZUtr0rdnqGxIZ/rNv4nVGswWfmM+Ylt9bimwTl ZNAWCiXrnGxkLvcpuFNDO05mgq5trAgQlduMgzEufvBrR3QDdfIes8eslE3dMHGy7Uat 0VcK4oWepwCGC7lIQsEfGE1mFdD+Qv0Ur0KVtoOotE915Jpc9N7sYRO2c5+CFCQZefl8 Jkhg== X-Gm-Message-State: AOAM533a6jbmYkEPsXu34/U7Ggst6T6P/UKu8CmM8AhgsZNlDKlSBOBc FMiKEF5r2GsSfMFSDzt5n+g= X-Google-Smtp-Source: ABdhPJyTwZiSryX5MIZpidIgIJi9LcUpN/z/chFF+oGj5J6XeYxB7Tv7kw9xlUyI/1o1pG1R/x/zJQ== X-Received: by 2002:a05:600c:287:: with SMTP id 7mr2871659wmk.91.1591098887652; Tue, 02 Jun 2020 04:54:47 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:46 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/11] PCI: qcom: Add ipq8064 rev2 variant Date: Tue, 2 Jun 2020 13:53:50 +0200 Message-Id: <20200602115353.20143-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit different offset based on the revision. Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2cd6d1456210..259b627bf890 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -366,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || + of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), @@ -1464,6 +1465,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, From patchwork Tue Jun 2 11:53:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB2D41392 for ; Tue, 2 Jun 2020 11:54:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A063E2074B for ; Tue, 2 Jun 2020 11:54:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rrhDAFlw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728444AbgFBLyx (ORCPT ); Tue, 2 Jun 2020 07:54:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLyw (ORCPT ); Tue, 2 Jun 2020 07:54:52 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E85AC061A0E; Tue, 2 Jun 2020 04:54:52 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id r9so2634367wmh.2; Tue, 02 Jun 2020 04:54:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZIcmPOVlQLoKdIP9dCKqwaemztdzBXHNcMiHg1REgA4=; b=rrhDAFlwRPU2Hsv2t+7LvyG/zgJmK6lK9gOB+dHLw5rq9qVS466XSatL6Tb9i9EZTo wHLRmXaQgsGrwlPf8/6CDpUHFKjnYdGzMmvdQGuMaMqHXOTVY7iMFsaXOPmyCk93JPTB j5FcNqKUVah++Xw3+SmnWjaKl22I30IIUUAcfDWDx3u3qbB5jlFVf+H6TJAzftFFN0LE ru4fNnw5GNbXEofHf3pOKAT/u+9vnCMlml6NhuhEU5IYhU4JLhUIelfnHjQQWNp5yvAC u7S1t6nhhoILxPa3kCSB5VqEGMzRJ+PHnU4vELxfitvwrPGNu3QU2WDNdSueEiA8IIoJ zUEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZIcmPOVlQLoKdIP9dCKqwaemztdzBXHNcMiHg1REgA4=; b=DTFFiNI6+oitusK7dL0KMuhjOWQfHFNuESSGxpdwJAT/BgwzNQFhSPr/m7+TVwhKmD aEHwRfnK6XkJ8ZAf24B2apJ8+J+fdfGkfWCsUXUXbP4YPTFPK6CSHegP6F/xq29Icmoa kbbFrVcTbI8nz8jv1kIUzRQw+VXrlHEZEWFxBFtOR78DmUmeudh/6fuI2B34du83OxyG ReS4TxbHa8giSJT/BgpvAR0gmN/0Fsqp3OhnXzrx8wOBwhFXZzIUnsdO7jt+AHNu8T+j Egr2smgZkVBCngdJ1ceiSXCm8+MOfKB9Zafepm6eLWjpIXrOPAgsvuN0busKySGV0Ide zTdQ== X-Gm-Message-State: AOAM5300Z83UzwwkujHhIxCOEy1QAIEtutnNpVq9DoTQ78ykkH3TXxr0 XcAt7dyia4FDnL49zEAjcEg= X-Google-Smtp-Source: ABdhPJzY2wnE8+8cukerL3Mxa1QbxixDeB9Tr3wcjXgPg4xTwNkPmFRgx5XwFjsvWf0VVkNQDjO19w== X-Received: by 2002:a1c:3dd6:: with SMTP id k205mr3784197wma.87.1591098890897; Tue, 02 Jun 2020 04:54:50 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:50 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 10/11] dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant Date: Tue, 2 Jun 2020 13:53:51 +0200 Message-Id: <20200602115353.20143-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset. In ipq8064 phy_tx0_term_offset is 7. In ipq8064 v2 other SoC it's set to 0 by default. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..02bc81bb8b2d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -5,6 +5,7 @@ Value type: Definition: Value should contain - "qcom,pcie-ipq8064" for ipq8064 + - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - "qcom,pcie-apq8064" for apq8064 - "qcom,pcie-apq8084" for apq8084 - "qcom,pcie-msm8996" for msm8996 or apq8096 From patchwork Tue Jun 2 11:53:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11583699 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D7251739 for ; Tue, 2 Jun 2020 11:55:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9A2D207ED for ; Tue, 2 Jun 2020 11:55:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MABAl+mE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728459AbgFBLy5 (ORCPT ); Tue, 2 Jun 2020 07:54:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgFBLy4 (ORCPT ); Tue, 2 Jun 2020 07:54:56 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58405C061A0E; Tue, 2 Jun 2020 04:54:55 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id j10so3089533wrw.8; Tue, 02 Jun 2020 04:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7M0pgcCpgKIyPa/msmRAjsWPWr7rOEx9Iq4gL/Ihm/M=; b=MABAl+mEplCv5avjexorM4MeCMlpqiWsDvbKgPGJa8TCuGMSFtIOLMF9a3HPXQcuQs qzzFlsMc1kcTv1VBaZ5qUbMdmwUtJCqdq0GHpDJxFJFgUhv1U5Sl34NiNdoLcLEnME8+ 5RmYc/ysWbT4k5xpaoTKWrizTrQTaRIz5xVrO0lbV56z0WypNdFcfyQtai+EU7wX7hiM qe1utxf0Ua6i7W0a4Cy/CV1Nxjgo6iScq+l1FErSp5xVYwK57oijSK08oS1pDMCM3Z8Q +E/y6R913frD++QMrhszSRFy0I3Vwi6aiSwXoV5tIjYV3o3tR1XAxsNraF1BY/ddPKJP 1ehw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7M0pgcCpgKIyPa/msmRAjsWPWr7rOEx9Iq4gL/Ihm/M=; b=dAjcndXn+ck8S0L6kSwJF0B5ZnSyWE4GnOEDKOjaMFvzxKBu3SeXxtKYbJh0+2i+ED 8Tp8PY80kCD8Nyig+T3zTAP6eHKrI9HxCxamj73LVtFbXFJdi2xWd8jpxGDRBNZoc3Aa TvT2fKnEdW7d3h31EuUjuioweKKQdhQNJJfVeaq/OQwo5dgWl3B5nb4Ym0xYEZ9H0dgb Oo+Yo3hQR2CjeElH2O6T/YdsIHO5irijBh8QM2Aut4tqGnOHhbMmy0LiRJ0Z+qohMKtH aEsuyJ2SNfWk05MLdK+C4xqHMCdd3wTnEmVPNgiMK/F7fpiC2fu0+gucCys2Ve3622ay +drg== X-Gm-Message-State: AOAM532DDj9qkiSf8mnzrYwvBukak2AyiZHxnRfApTOI6A9cwBFJdhg2 SB4yEZ52zJSAGv7ELoDKScYA3kRAtBGjow== X-Google-Smtp-Source: ABdhPJypOIwgcVbOKZfGKseAXLeB7agS7aD0IDuLQSIbdUKttZtsgODYJZ3f2BbVpqx6ZtbHjdU+Ew== X-Received: by 2002:adf:c391:: with SMTP id p17mr24817566wrf.243.1591098893955; Tue, 02 Jun 2020 04:54:53 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host9-254-dynamic.3-87-r.retail.telecomitalia.it. [87.3.254.9]) by smtp.googlemail.com with ESMTPSA id b18sm3273777wrn.88.2020.06.02.04.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 04:54:53 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Sham Muthayyan , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 11/11] PCI: qcom: Add Force GEN1 support Date: Tue, 2 Jun 2020 13:53:52 +0200 Message-Id: <20200602115353.20143-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com> References: <20200602115353.20143-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq8064 board that needs to limit some PCIe line to gen1 for some hardware limitation. This is set by the max-link-speed binding and needed by some soc based on ipq8064. (for example Netgear R7800 router) Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 259b627bf890..0ce15d53c46e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -27,6 +27,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE20_PARF_SYS_CTRL 0x00 @@ -99,6 +100,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -195,6 +198,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + int gen; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->gen == 1) { + val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + val |= 1; + writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node); + if (pcie->gen < 0) + pcie->gen = 2; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) {