From patchwork Wed Jun 3 19:43:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11586213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99D0F90 for ; Wed, 3 Jun 2020 19:41:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 811BE20678 for ; Wed, 3 Jun 2020 19:41:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 811BE20678 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5E7289AF3; Wed, 3 Jun 2020 19:41:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D2AD89AF3 for ; Wed, 3 Jun 2020 19:41:53 +0000 (UTC) IronPort-SDR: Q55A+ee1z3Se+oQW5NQlyP+r4QUpr5HJr+cwngNdtaOkd8cFa/NsjjXYRdXhPK25w2h8iqN1Mu ZLbHT9/MqPWQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2020 12:41:52 -0700 IronPort-SDR: Il3tR9PyIf3m52Jy3O7F0VwoFCmbqP6c+p0zHWn3cjRXS8QF1oOmx7qRe9kmTCDNG6mx7DkCJB PesLoBc7jcQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,469,1583222400"; d="scan'208";a="294083537" Received: from psethi-desk2.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.254.182.158]) by fmsmga004.fm.intel.com with ESMTP; 03 Jun 2020 12:41:52 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 3 Jun 2020 12:43:06 -0700 Message-Id: <20200603194308.78622-1-jose.souza@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/3] drm/i915/bios: Parse HOBL parameter X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" HOBL means hours of battery life, it is a power-saving feature were supported motherboards can use a special voltage swing table that uses less power. So here parsing the VBT to check if this feature is supported. While at it already added the VRR parameter too. BSpec: 20150 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_bios.c | 3 +++ drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 839124647202..b3c453aa7623 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -722,6 +722,9 @@ parse_power_conservation_features(struct drm_i915_private *dev_priv, */ if (!(power->drrs & BIT(panel_type))) dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; + + if (bdb->version >= 232) + dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type); } static void diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index aef7fe932d1a..65f552f57e06 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -820,6 +820,8 @@ struct bdb_lfp_power { u16 adb; u16 lace_enabled_status; struct agressiveness_profile_entry aggressivenes[16]; + u16 hobl; /* 232+ */ + u16 vrr; /* 233+ */ } __packed; /* diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e99255e17eb7..2336c9231eef 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -690,6 +690,7 @@ struct intel_vbt_data { bool initialized; int bpp; struct edp_power_seq pps; + bool hobl; } edp; struct { From patchwork Wed Jun 3 19:43:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11586217 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2A50F90 for ; Wed, 3 Jun 2020 19:42:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 123A820678 for ; Wed, 3 Jun 2020 19:42:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 123A820678 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E5A4389B00; Wed, 3 Jun 2020 19:41:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id C705789B00 for ; Wed, 3 Jun 2020 19:41:53 +0000 (UTC) IronPort-SDR: yp8ZYzUlhl67y0goI1CJSxak6yBC9Xidy86Iqb2QW81JBBbdiWGiRW8rePEm5lHGbVBrfyrnd0 4TSUNBbw2xfw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2020 12:41:52 -0700 IronPort-SDR: CVkhfDu4kiOOU/EDYJ4oPpXK/lw1CVPAEKf6uB6ZzUivOJGPUH/XXidIOJNz7csbH2g2pUdWLE pxYwoh7bipyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,469,1583222400"; d="scan'208";a="294083540" Received: from psethi-desk2.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.254.182.158]) by fmsmga004.fm.intel.com with ESMTP; 03 Jun 2020 12:41:52 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 3 Jun 2020 12:43:07 -0700 Message-Id: <20200603194308.78622-2-jose.souza@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200603194308.78622-1-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915/display: Implement HOBL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hours Of Battery Life is a new GEN12+ power-saving feature that allows supported motherboards to use a special voltage swing table for eDP panels that uses less power. So here if supported by HW, OEM will set it in VBT and i915 will try to train link with HOBL vswing table if link training fails it fall back to the original table. Just not sure if DP compliance should also use this new voltage swing table too, cced some folks that worked in DP compliance. BSpec: 49291 BSpec: 49399 Cc: Ville Syrjälä Cc: Animesh Manna Cc: Manasi Navare Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++-- .../drm/i915/display/intel_display_types.h | 2 + .../drm/i915/display/intel_dp_link_training.c | 20 +++++++- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 2 + 5 files changed, 69 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 236f3762b6f9..57174a111976 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { + { 0x6, 0x7F, 0x3F, 0x00, 0x00 } +}; + static const struct ddi_buf_trans * bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) { @@ -2301,14 +2305,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); } +/* + * If supported return HOBL vswing table and set registers to enable HOBL + * otherwise returns NULL and unset registers to enable HOBL. + */ +static const struct cnl_ddi_buf_trans * +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv, + struct intel_encoder *encoder, int type, int rate, + u32 level, int *n_entries) +{ + const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct intel_dp *intel_dp; + + if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP) + return NULL; + + intel_dp = enc_to_intel_dp(encoder); + if (!intel_dp->try_hobl || rate > 540000) { + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0); + return NULL; + } + + drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy)); + drm_WARN_ON_ONCE(&dev_priv->drm, level > 0); + + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en); + /* Same table applies to TGL, RKL and DG1 */ + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; +} + static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, - u32 level, enum phy phy, int type, - int rate) + struct intel_encoder *encoder, + u32 level, enum phy phy, int type, + int rate) { const struct cnl_ddi_buf_trans *ddi_translations = NULL; u32 n_entries, val; int ln; + ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type, + rate, level, &n_entries); + if (ddi_translations) + goto hobl_found; + if (INTEL_GEN(dev_priv) >= 12) ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, &n_entries); @@ -2321,6 +2362,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, if (!ddi_translations) return; +hobl_found: if (level >= n_entries) { drm_dbg_kms(&dev_priv->drm, "DDI translation not found for level %d. Using %d instead.", @@ -2428,7 +2470,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); + icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate); /* 6. Set training enable to trigger update */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..f8943b67819d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1375,6 +1375,8 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; + + bool try_hobl; }; enum lspcon_vendor { diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index b9e4ee2dbddc..88f366bb28d7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -52,12 +52,24 @@ static u8 dp_voltage_max(u8 preemph) void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const u8 link_status[DP_LINK_STATUS_SIZE]) { + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 v = 0; u8 p = 0; int lane; u8 voltage_max; u8 preemph_max; + if (intel_dp->try_hobl) { + /* + * Do not adjust, try now with the regular table using VSwing 0 + * and pre-emp 0 + */ + intel_dp->try_hobl = false; + drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link " + "training, switching back to regular table\n"); + return; + } + for (lane = 0; lane < intel_dp->lane_count; lane++) { v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); @@ -103,9 +115,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, } static bool -intel_dp_reset_link_train(struct intel_dp *intel_dp, - u8 dp_train_pat) +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) { + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) + intel_dp->try_hobl = true; + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp_set_signal_levels(intel_dp); return intel_dp_set_link_train(intel_dp, dp_train_pat); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2336c9231eef..c7e7df17eef2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1687,6 +1687,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12) + static inline bool intel_vtd_active(void) { #ifdef CONFIG_INTEL_IOMMU diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 578cfe11cbb9..d4611171f075 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define PWR_DOWN_LN_3_1_0 (0xb << 4) #define PWR_DOWN_LN_MASK (0xf << 4) #define PWR_DOWN_LN_SHIFT 4 +#define EDP4K2K_MODE_OVRD_EN (1 << 3) +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) #define ICL_LANE_ENABLE_AUX (1 << 0) From patchwork Wed Jun 3 19:43:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11586215 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CBFE7913 for ; Wed, 3 Jun 2020 19:41:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3A2920678 for ; Wed, 3 Jun 2020 19:41:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B3A2920678 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2313789B98; Wed, 3 Jun 2020 19:41:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 06D7789AF3 for ; Wed, 3 Jun 2020 19:41:53 +0000 (UTC) IronPort-SDR: m6kYP3KOLbMPdyQepqPIRQJySyvtr+0KLAFnmsLDlblth8N5r9xnsQF8J/Mzhs67ylB+WBftuA aXbqAiAifY6g== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2020 12:41:52 -0700 IronPort-SDR: Ye5QUz4g8fmEXae+OahUo+/OZBlSqwNjovxqX382xTmGpCgM2f4XanMsPC4FYShzaefDoy9NnD DN7hmt7/s9Sw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,469,1583222400"; d="scan'208";a="294083543" Received: from psethi-desk2.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.254.182.158]) by fmsmga004.fm.intel.com with ESMTP; 03 Jun 2020 12:41:52 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 3 Jun 2020 12:43:08 -0700 Message-Id: <20200603194308.78622-3-jose.souza@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200603194308.78622-1-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Enable HOBL regardless the VBT value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" HOBL worked in my TGL RVP even without the necessary HW support, also it worked in more than half of the TGL machines in CI so it is worthy to enable it by default. Even if link training fails with this new vswing table it will only cause one additional link training, that is worthy the try to get the additional power-savings. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 88f366bb28d7..13f7bc0a4bc0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -119,7 +119,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) + if (HAS_HOBL(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->try_hobl = true; memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));