From patchwork Sat Jun 6 04:25:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11590947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6E9392A for ; Sat, 6 Jun 2020 04:26:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE718206DC for ; Sat, 6 Jun 2020 04:26:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="WC90LgNR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726317AbgFFE0S (ORCPT ); Sat, 6 Jun 2020 00:26:18 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:58130 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726045AbgFFE0R (ORCPT ); Sat, 6 Jun 2020 00:26:17 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1591417577; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=I8DTy0+J0lw/p2a0JP3pdcvQksGaqfQghz8FqkcM+Z0=; b=WC90LgNR0QC8Hsu6N4zFp0fekYR4azSz5abTCiiKkLF29P1hniI7hET0fZJfo3T0XNkH9fWU udKHpoVdkFbdLnePoWaVwqyt3ndcnQNsZ84/zgGZsmPYRHuyaocXwvzVgZ91qsO8h7UlYqpW uIq+SaESuwb6JLMPXi+OrdlB1Rs= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n09.prod.us-east-1.postgun.com with SMTP id 5edb1ae25d0a90552410bfb6 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sat, 06 Jun 2020 04:26:10 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 1A78FC4339C; Sat, 6 Jun 2020 04:26:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id C133DC433CA; Sat, 6 Jun 2020 04:26:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C133DC433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, robdclark@gmail.com, Sharat Masetty Subject: [PATCH v3 1/6] dt-bindings: drm/msm/gpu: Document gpu opp table Date: Sat, 6 Jun 2020 09:55:46 +0530 Message-Id: <1591417551-38051-2-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> References: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update documentation to list the gpu opp table bindings including the newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling. Signed-off-by: Sharat Masetty Acked-by: Rob Herring --- .../devicetree/bindings/display/msm/gpu.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 70025cb..48bd4ab 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -79,6 +79,34 @@ Example a6xx (with GMU): interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-peak-kBps = <5412000>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + opp-peak-kBps = <1804000>; + }; + }; + qcom,gmu = <&gmu>; zap-shader { From patchwork Sat Jun 6 04:25:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11590951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 54F9760D for ; Sat, 6 Jun 2020 04:26:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3576A208B6 for ; Sat, 6 Jun 2020 04:26:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="V9rCoEYH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726323AbgFFE0S (ORCPT ); Sat, 6 Jun 2020 00:26:18 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:45500 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726304AbgFFE0R (ORCPT ); Sat, 6 Jun 2020 00:26:17 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1591417576; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=I4fnmfnJPxudfrFyDfVNjCnnHZMLEo/q0KIlFZhVNMo=; b=V9rCoEYHOvnJ/cbp0g4XHfQfa0V2lk2b2h3LgqG2MNapEyLkP/0DjaFAgr6ZA3K+GFbXSAKu PCiLJZHbJlEdCM573GSW1StH13/jh0oqlRwZDUGUd/n6zMuT8l+VA9+y8WpL3D4qbB8pDolW g8mAOIlBMcnGkV7DHrz4NNSaRak= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n14.prod.us-east-1.postgun.com with SMTP id 5edb1ae75ba9f3e9453d3209 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sat, 06 Jun 2020 04:26:15 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id CDA26C433AD; Sat, 6 Jun 2020 04:26:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 278F7C433A1; Sat, 6 Jun 2020 04:26:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 278F7C433A1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, robdclark@gmail.com, Sharat Masetty Subject: [PATCH v3 2/6] drm: msm: a6xx: send opp instead of a frequency Date: Sat, 6 Jun 2020 09:55:47 +0530 Message-Id: <1591417551-38051-3-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> References: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 62 +++++++++++++++++++---------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 3 +- drivers/gpu/drm/msm/msm_gpu.h | 3 +- 4 files changed, 38 insertions(+), 32 deletions(-) -- 2.7.4 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 748cd37..2d8124b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -100,17 +100,30 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); } -static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) +void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) { - struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); - struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; - struct msm_gpu *gpu = &adreno_gpu->base; - int ret; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + u32 perf_index; + unsigned long gpu_freq; + int ret = 0; + + gpu_freq = dev_pm_opp_get_freq(opp); + + if (gpu_freq == gmu->freq) + return; + + for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) + if (gpu_freq == gmu->gpu_freqs[perf_index]) + break; + + gmu->current_perf_index = perf_index; gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, - ((3 & 0xf) << 28) | index); + ((3 & 0xf) << 28) | perf_index); /* * Send an invalid index as a vote for the bus bandwidth and let the @@ -126,7 +139,7 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) if (ret) dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); - gmu->freq = gmu->gpu_freqs[index]; + gmu->freq = gmu->gpu_freqs[perf_index]; /* * Eventually we will want to scale the path vote with the frequency but @@ -135,25 +148,6 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); } -void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) -{ - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - struct a6xx_gmu *gmu = &a6xx_gpu->gmu; - u32 perf_index = 0; - - if (freq == gmu->freq) - return; - - for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) - if (freq == gmu->gpu_freqs[perf_index]) - break; - - gmu->current_perf_index = perf_index; - - __a6xx_gmu_set_freq(gmu, perf_index); -} - unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -708,6 +702,19 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) a6xx_gmu_rpmh_off(gmu); } +static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) +{ + struct dev_pm_opp *gpu_opp; + unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; + + gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); + if (IS_ERR_OR_NULL(gpu_opp)) + return; + + a6xx_gmu_set_freq(gpu, gpu_opp); + dev_pm_opp_put(gpu_opp); +} + int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -759,8 +766,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); enable_irq(gmu->hfi_irq); - /* Set the GPU to the current freq */ - __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); + a6xx_gmu_set_initial_freq(gpu, gmu); /* * "enable" the GX power domain which won't actually do anything but it diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 7239b8b..03ba60d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -63,7 +63,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq); +void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp); unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 615c5cd..82c3068 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -13,7 +13,6 @@ #include #include -#include #include #include #include @@ -34,7 +33,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, return PTR_ERR(opp); if (gpu->funcs->gpu_set_freq) - gpu->funcs->gpu_set_freq(gpu, (u64)*freq); + gpu->funcs->gpu_set_freq(gpu, opp); else clk_set_rate(gpu->core_clk, *freq); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index ab8f0f9c..cf0dc6d 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -9,6 +9,7 @@ #include #include +#include #include #include "msm_drv.h" @@ -63,7 +64,7 @@ struct msm_gpu_funcs { struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); int (*gpu_state_put)(struct msm_gpu_state *state); unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); - void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); + void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp); }; struct msm_gpu { From patchwork Sat Jun 6 04:25:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11590949 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E87A913B1 for ; Sat, 6 Jun 2020 04:26:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE36E206DC for ; Sat, 6 Jun 2020 04:26:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="xepyvnsr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726466AbgFFE0V (ORCPT ); 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Sat, 06 Jun 2020 04:26:19 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id AE1C4C433C6; Sat, 6 Jun 2020 04:26:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=ham autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 81465C433CA; Sat, 6 Jun 2020 04:26:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 81465C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, robdclark@gmail.com, Sharat Masetty Subject: [PATCH v3 3/6] drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR Date: Sat, 6 Jun 2020 09:55:48 +0530 Message-Id: <1591417551-38051-4-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> References: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patches replaces the previously used static DDR vote and uses dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling GPU frequency. Also since the icc path voting is handled completely in the opp driver, remove the icc_path handle and its usage in the drm driver. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 23 ++++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 -------- drivers/gpu/drm/msm/msm_gpu.h | 2 -- 3 files changed, 16 insertions(+), 17 deletions(-) -- 2.7.4 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 2d8124b..1dd8fc5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) gmu->freq = gmu->gpu_freqs[perf_index]; - /* - * Eventually we will want to scale the path vote with the frequency but - * for now leave it at max so that the performance is nominal. - */ - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + dev_pm_opp_set_bw(&gpu->pdev->dev, opp); } unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) @@ -715,6 +711,19 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) dev_pm_opp_put(gpu_opp); } +static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) +{ + struct dev_pm_opp *gpu_opp; + unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; + + gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); + if (IS_ERR_OR_NULL(gpu_opp)) + return; + + dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp); + dev_pm_opp_put(gpu_opp); +} + int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -739,7 +748,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) } /* Set the bus quota to a reasonable value for boot */ - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); + a6xx_gmu_set_initial_bw(gpu, gmu); /* Enable the GMU interrupt */ gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); @@ -907,7 +916,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) a6xx_gmu_shutdown(gmu); /* Remove the bus vote */ - icc_set_bw(gpu->icc_path, 0, 0); + dev_pm_opp_set_bw(&gpu->pdev->dev, NULL); /* * Make sure the GX domain is off before turning off the GMU (CX) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 2d13694..718c705 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -913,11 +913,6 @@ static int adreno_get_pwrlevels(struct device *dev, DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); - /* Check for an interconnect path for the bus */ - gpu->icc_path = of_icc_get(dev, NULL); - if (IS_ERR(gpu->icc_path)) - gpu->icc_path = NULL; - return 0; } @@ -958,13 +953,10 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) { - struct msm_gpu *gpu = &adreno_gpu->base; unsigned int i; for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) release_firmware(adreno_gpu->fw[i]); - icc_put(gpu->icc_path); - msm_gpu_cleanup(&adreno_gpu->base); } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index cf0dc6d..c7d74a9 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -112,8 +112,6 @@ struct msm_gpu { struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; uint32_t fast_rate; - struct icc_path *icc_path; - /* Hang and Inactivity Detection: */ #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ From patchwork Sat Jun 6 04:25:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11590955 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B67192A for ; Sat, 6 Jun 2020 04:26:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 800AA206DC for ; Sat, 6 Jun 2020 04:26:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="VZ/x3ian" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726880AbgFFE01 (ORCPT ); Sat, 6 Jun 2020 00:26:27 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:45500 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726605AbgFFE0Z (ORCPT ); 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Sat, 6 Jun 2020 04:26:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DDB9BC4339C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, robdclark@gmail.com, Sharat Masetty Subject: [PATCH v3 4/6] arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling Date: Sat, 6 Jun 2020 09:55:49 +0530 Message-Id: <1591417551-38051-5-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> References: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 11fc3f24..6ea6f54 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3240,6 +3240,8 @@ qcom,gmu = <&gmu>; + interconnects = <&mem_noc MASTER_GFX3D &mem_noc SLAVE_EBI1>; + zap_shader: zap-shader { memory-region = <&gpu_mem>; }; @@ -3250,36 +3252,43 @@ opp-710000000 { opp-hz = /bits/ 64 <710000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-596000000 { opp-hz = /bits/ 64 <596000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-520000000 { opp-hz = /bits/ 64 <520000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = ; + opp-peak-kBps = <4068000>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = ; + opp-peak-kBps = <2724000>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; + opp-peak-kBps = <1648000>; }; }; }; From patchwork Sat Jun 6 04:25:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11590959 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64E6A60D for ; Sat, 6 Jun 2020 04:26:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C04A20814 for ; Sat, 6 Jun 2020 04:26:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="SNpySpgF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727910AbgFFE0e (ORCPT ); Sat, 6 Jun 2020 00:26:34 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:27863 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728027AbgFFE0e (ORCPT ); Sat, 6 Jun 2020 00:26:34 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1591417593; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=1I4ZO0g+cZgUJhZXpWRg+9zaHY5dR8+6XUJA4A3etwM=; b=SNpySpgFYRJxId6P9Y5odFjosj/oRQqK2ETbMQtB1S91Wf4HLtWHKdX98UH1pT2dzcfY2Z20 wdGfZcnIglHEt+/6Tcuh7lrkjbIKaIc7C7Q4bHY92CSGF9ZBhvc/3lCRqOPjpCblXXd2rZL0 a99y37PSRwiTZFkzYykUsr6Do+I= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n06.prod.us-east-1.postgun.com with SMTP id 5edb1af68047ca28b6a99c4b (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sat, 06 Jun 2020 04:26:30 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 185E0C433B1; Sat, 6 Jun 2020 04:26:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5E0D0C433A1; Sat, 6 Jun 2020 04:26:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5E0D0C433A1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, robdclark@gmail.com, Sharat Masetty Subject: [PATCH v3 5/6] arm64: dts: qcom: sc7180: Add interconnects property for GPU Date: Sat, 6 Jun 2020 09:55:50 +0530 Message-Id: <1591417551-38051-6-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> References: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index eaede5e..34004ad 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1497,6 +1497,8 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From patchwork Sat Jun 6 04:25:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11590969 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3568192A for ; Sat, 6 Jun 2020 04:26:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CBD2206DC for ; Sat, 6 Jun 2020 04:26:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="gqQMTSX6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728566AbgFFE0z (ORCPT ); Sat, 6 Jun 2020 00:26:55 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:55641 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728549AbgFFE0z (ORCPT ); Sat, 6 Jun 2020 00:26:55 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1591417614; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=3Tbq314xTu2mZgk8XZHCKH3g0sEpANHcL/rn9MNYhE0=; b=gqQMTSX6TtTZVjnHErw2jfxaGjGrOvYIKTVsE/PdHc6I9vu3iQzrs5RrDRa5128NTldbaINt NIcM3DnOMYr6gZimpSStCaTJzVO9vM80e4Y0RHUkcEhMJTcFjFXLq820w8MvBB5GXLc48jZ2 Xh0Cmuvj8azuZ6GDgFzS6BuX3oM= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 5edb1afc583b2d42d5f18334 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sat, 06 Jun 2020 04:26:36 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 25785C433B2; Sat, 6 Jun 2020 04:26:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from hyd-lnxbld559.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 11E84C433C6; Sat, 6 Jun 2020 04:26:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 11E84C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, mka@chromium.org, sibis@codeaurora.org, saravanak@google.com, viresh.kumar@linaro.org, robdclark@gmail.com, Sharat Masetty Subject: [PATCH v3 6/6] arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp Date: Sat, 6 Jun 2020 09:55:51 +0530 Message-Id: <1591417551-38051-7-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> References: <1591417551-38051-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 34004ad..7bef42b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1505,36 +1505,43 @@ opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-level = ; + opp-peak-kBps = <8532000>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-565000000 { opp-hz = /bits/ 64 <565000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-355000000 { opp-hz = /bits/ 64 <355000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; opp-level = ; + opp-peak-kBps = <1804000>; }; }; };