From patchwork Mon Jun 8 11:40:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leif Lindholm X-Patchwork-Id: 11593171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45BDD90 for ; Mon, 8 Jun 2020 11:42:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B32D2076A for ; Mon, 8 Jun 2020 11:42:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nuviainc-com.20150623.gappssmtp.com header.i=@nuviainc-com.20150623.gappssmtp.com header.b="XFg1V4fZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B32D2076A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=nuviainc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:34580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jiGAG-0001nL-2g for patchwork-qemu-devel@patchwork.kernel.org; Mon, 08 Jun 2020 07:42:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jiG8p-00087y-2g for qemu-devel@nongnu.org; Mon, 08 Jun 2020 07:40:35 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:34099) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jiG8n-0003ch-2E for qemu-devel@nongnu.org; Mon, 08 Jun 2020 07:40:34 -0400 Received: by mail-wr1-x441.google.com with SMTP id r7so17042793wro.1 for ; Mon, 08 Jun 2020 04:40:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V2TSsHVRZv5n6nm4rd17wgB0vrMj5AgJjY7Tq8D4v7E=; b=XFg1V4fZYjjfguvr9MNLuyck1yG+0Hb7wzfa14c2/wyF9unIy2e0ghtwAIqhRhXXU2 43YKuKn+AcYawMqkdofiH/ykZYphdHN6Z4ZuRGdbVvQSIG5Y+Pdl34P0DODLQhn1tUSf pGk2hgUsHSmns/0lNL8jQXbbc0j2fUZXpTwZPhkjidrRCwjWZsrMcvuiB2sEGxH3/TQN reExKqBEptWPHiAOOcmgFYAnLHPOEU/d4kBDh/pSRoPL0ZTrtByNfzhwm1pxW4Omwc+o P6tXdS6v4k7yI8+7t/aRHiKdjamuNrvSaYy2d4o3BzYPwzu5fkAqDqB+kd732h8R4H53 RRVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V2TSsHVRZv5n6nm4rd17wgB0vrMj5AgJjY7Tq8D4v7E=; b=TBYxXL0GQ89pX14qhRrUqOFmU7/PbWsTQzkX/rUw1vo9LofaY5kHyTsXDfM/nc1KSm fNEAKg08OAMNftgdPpdgoGb6XLFm/QrV3IqV/qxEyG3uLIxeD8P/bL9/UCyTLdfB0uei a1sshvwBhA6SaBTNIzgQll70RgqVU8fOwqZ3hAM3zrXP4fG4ZNSjLBoEATQymbhBwwJs kRdMM1A873De1AJmqT2hfRcbBzLOroxf/CyCuOmQMW4PnHUE46/G2kFAe1Kf2w8TP0ur zaXHU+tHPKsFSB2RGwB2UBbhzarbcpAXrdyBdKHnpANpLu14igcVxAUOo5wweJcpuW+Q raFA== X-Gm-Message-State: AOAM531bIgXmr3KHqJDUa8/0Itlz40t5CyquLgzO5aFmi9M9Optljyer ACES4cmJeWLK4Ri64K3pfjrUB1+KGoichuQcUqPc9BolbUOy3cvltf2ihGbQcdSfWUs1Dv9EPaP WTDv8RHBDwEVauEhUnsdqJ7aMwHRC8aLex9hYFs7Ee9qvmMiQwF5YlgAaTBqXyOLq X-Google-Smtp-Source: ABdhPJymsjJm917aEJtm9K5EcUiGiikvasFd5PKmpW40SN+naA031/zpsLD4uQI0LPb82odE+IPXFg== X-Received: by 2002:adf:de84:: with SMTP id w4mr23496358wrl.54.1591616431157; Mon, 08 Jun 2020 04:40:31 -0700 (PDT) Received: from vanye.hemma.eciton.net (cpc92302-cmbg19-2-0-cust304.5-4.cable.virginm.net. [82.1.209.49]) by smtp.gmail.com with ESMTPSA id y5sm24225932wrs.63.2020.06.08.04.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 04:40:30 -0700 (PDT) From: Leif Lindholm To: QEMU Developers Subject: [RFC PATCH 1/3] target/arm: commonalize aarch64 cpu init Date: Mon, 8 Jun 2020 12:40:26 +0100 Message-Id: <20200608114028.25345-2-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608114028.25345-1-leif@nuviainc.com> References: <20200608114028.25345-1-leif@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=leif@nuviainc.com; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Some basic options will be set by all aarch64 platforms. Break those out into a separate aarch64_cpu_common_init function, which also takes implementer, partnum, variant, and revision as arguments to set up MIDR. Invoke this to remove duplication between a57/a53/a72 init. Signed-off-by: Leif Lindholm --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu64.c | 46 ++++++++++++++++++++++++-------------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 56395b87f6..48f6303308 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -44,6 +44,9 @@ typedef struct ARMCPUInfo { void arm_cpu_register(const ARMCPUInfo *info); void aarch64_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_common_init(Object *obj, uint8_t impl, uint16_t part, + uint8_t var, uint8_t rev); + /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index cbc5c3868f..79786e034f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,8 @@ #include "kvm_arm.h" #include "qapi/visitor.h" +#define MIDR_IMPLEMENTER_ARM 0x41 + #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -86,11 +88,19 @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { REGINFO_SENTINEL }; -static void aarch64_a57_initfn(Object *obj) +void aarch64_cpu_common_init(Object *obj, uint8_t impl, uint16_t part, + uint8_t var, uint8_t rev) { ARMCPU *cpu = ARM_CPU(obj); + uint64_t t; + + t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, impl); + t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t = FIELD_DP64(t, MIDR_EL1, PARTNUM, part); + t = FIELD_DP64(t, MIDR_EL1, VARIANT, var); + t = FIELD_DP64(t, MIDR_EL1, REVISION, rev); + cpu->midr = t; - cpu->dtb_compatible = "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -99,8 +109,16 @@ static void aarch64_a57_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); +} + +static void aarch64_a57_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd07, 1, 0); + + cpu->dtb_compatible = "arm,cortex-a57"; cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; - cpu->midr = 0x411fd070; cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; cpu->isar.mvfr0 = 0x10110222; @@ -143,17 +161,10 @@ static void aarch64_a53_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd03, 0, 4); + cpu->dtb_compatible = "arm,cortex-a53"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; - cpu->midr = 0x410fd034; cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; cpu->isar.mvfr0 = 0x10110222; @@ -196,16 +207,9 @@ static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd08, 0, 3); + cpu->dtb_compatible = "arm,cortex-a72"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr = 0x410fd083; cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034080; cpu->isar.mvfr0 = 0x10110222; From patchwork Mon Jun 8 11:40:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leif Lindholm X-Patchwork-Id: 11593165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E28A3739 for ; Mon, 8 Jun 2020 11:41:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B85F62076A for ; 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[82.1.209.49]) by smtp.gmail.com with ESMTPSA id y5sm24225932wrs.63.2020.06.08.04.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 04:40:31 -0700 (PDT) From: Leif Lindholm To: QEMU Developers Subject: [RFC PATCH 2/3] target/arm: move cpu64 cortex processor common init settings to function Date: Mon, 8 Jun 2020 12:40:27 +0100 Message-Id: <20200608114028.25345-3-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608114028.25345-1-leif@nuviainc.com> References: <20200608114028.25345-1-leif@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=leif@nuviainc.com; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Move the id register initializations identical between the platforms in this file into a standalone helper function, and change the cpu-specific The value of mmfr0 set for a57 and a53 violates the ARM architecture reference manual, but matches the values set in actual hardware r1p0 a57 and r0p4 a53. The function sets the architectually correct value, and the a57/a53 init functions override it after the fact. Signed-off-by: Leif Lindholm --- target/arm/cpu64.c | 107 ++++++++++++++------------------------------- 1 file changed, 34 insertions(+), 73 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 79786e034f..9927c1f75d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -88,6 +88,35 @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { REGINFO_SENTINEL }; +static void cortex_a72_a57_a53_common_init(ARMCPU *cpu) +{ + cpu->revidr = 0x00000000; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x12111111; + cpu->isar.mvfr2 = 0x00000043; + cpu->reset_sctlr = 0x00c50838; + cpu->id_pfr0 = 0x00000131; + cpu->id_pfr1 = 0x00011011; + cpu->isar.id_dfr0 = 0x03010066; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01260000; + cpu->isar.id_mmfr3 = 0x02102211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x00011121; + cpu->isar.id_isar6 = 0; + cpu->isar.id_aa64pfr0 = 0x00002222; + cpu->isar.id_aa64dfr0 = 0x10305106; + cpu->isar.id_aa64isar0 = 0x00011120; + cpu->isar.id_aa64mmfr0 = 0x00001124; + cpu->isar.dbgdidr = 0x3516d000; +} + void aarch64_cpu_common_init(Object *obj, uint8_t impl, uint16_t part, uint8_t var, uint8_t rev) { @@ -116,36 +145,13 @@ static void aarch64_a57_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd07, 1, 0); + cortex_a72_a57_a53_common_init(cpu); cpu->dtb_compatible = "arm,cortex-a57"; cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; - cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; - cpu->isar.mvfr0 = 0x10110222; - cpu->isar.mvfr1 = 0x12111111; - cpu->isar.mvfr2 = 0x00000043; cpu->ctr = 0x8444c004; - cpu->reset_sctlr = 0x00c50838; - cpu->id_pfr0 = 0x00000131; - cpu->id_pfr1 = 0x00011011; - cpu->isar.id_dfr0 = 0x03010066; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10101105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; - cpu->isar.id_isar0 = 0x02101110; - cpu->isar.id_isar1 = 0x13112111; - cpu->isar.id_isar2 = 0x21232042; - cpu->isar.id_isar3 = 0x01112131; - cpu->isar.id_isar4 = 0x00011142; - cpu->isar.id_isar5 = 0x00011121; - cpu->isar.id_isar6 = 0; - cpu->isar.id_aa64pfr0 = 0x00002222; - cpu->isar.id_aa64dfr0 = 0x10305106; - cpu->isar.id_aa64isar0 = 0x00011120; - cpu->isar.id_aa64mmfr0 = 0x00001124; - cpu->isar.dbgdidr = 0x3516d000; + cpu->isar.id_mmfr0 = 0x10101105; /* Match documented value for r1p0 */ cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ @@ -162,36 +168,14 @@ static void aarch64_a53_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd03, 0, 4); + cortex_a72_a57_a53_common_init(cpu); cpu->dtb_compatible = "arm,cortex-a53"; cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; - cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; - cpu->isar.mvfr0 = 0x10110222; - cpu->isar.mvfr1 = 0x12111111; - cpu->isar.mvfr2 = 0x00000043; cpu->ctr = 0x84448004; /* L1Ip = VIPT */ - cpu->reset_sctlr = 0x00c50838; - cpu->id_pfr0 = 0x00000131; - cpu->id_pfr1 = 0x00011011; - cpu->isar.id_dfr0 = 0x03010066; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10101105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; - cpu->isar.id_isar0 = 0x02101110; - cpu->isar.id_isar1 = 0x13112111; - cpu->isar.id_isar2 = 0x21232042; - cpu->isar.id_isar3 = 0x01112131; - cpu->isar.id_isar4 = 0x00011142; - cpu->isar.id_isar5 = 0x00011121; - cpu->isar.id_isar6 = 0; - cpu->isar.id_aa64pfr0 = 0x00002222; - cpu->isar.id_aa64dfr0 = 0x10305106; - cpu->isar.id_aa64isar0 = 0x00011120; + cpu->isar.id_mmfr0 = 0x10101105; /* Match documented value for r0p4 */ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ - cpu->isar.dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ @@ -208,34 +192,11 @@ static void aarch64_a72_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); aarch64_cpu_common_init(obj, MIDR_IMPLEMENTER_ARM, 0xd08, 0, 3); + cortex_a72_a57_a53_common_init(cpu); cpu->dtb_compatible = "arm,cortex-a72"; - cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034080; - cpu->isar.mvfr0 = 0x10110222; - cpu->isar.mvfr1 = 0x12111111; - cpu->isar.mvfr2 = 0x00000043; cpu->ctr = 0x8444c004; - cpu->reset_sctlr = 0x00c50838; - cpu->id_pfr0 = 0x00000131; - cpu->id_pfr1 = 0x00011011; - cpu->isar.id_dfr0 = 0x03010066; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; - cpu->isar.id_isar0 = 0x02101110; - cpu->isar.id_isar1 = 0x13112111; - cpu->isar.id_isar2 = 0x21232042; - cpu->isar.id_isar3 = 0x01112131; - cpu->isar.id_isar4 = 0x00011142; - cpu->isar.id_isar5 = 0x00011121; - cpu->isar.id_aa64pfr0 = 0x00002222; - cpu->isar.id_aa64dfr0 = 0x10305106; - cpu->isar.id_aa64isar0 = 0x00011120; - cpu->isar.id_aa64mmfr0 = 0x00001124; - cpu->isar.dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ From patchwork Mon Jun 8 11:40:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leif Lindholm X-Patchwork-Id: 11593179 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5831E90 for ; Mon, 8 Jun 2020 11:43:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2DF5C2074B for ; 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[82.1.209.49]) by smtp.gmail.com with ESMTPSA id y5sm24225932wrs.63.2020.06.08.04.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 04:40:32 -0700 (PDT) From: Leif Lindholm To: QEMU Developers Subject: [RFC PATCH 3/3] target/arm: use cortex...common_init for cpu64 max Date: Mon, 8 Jun 2020 12:40:28 +0100 Message-Id: <20200608114028.25345-4-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608114028.25345-1-leif@nuviainc.com> References: <20200608114028.25345-1-leif@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=leif@nuviainc.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Drop the call to aarch64_a57_initfn from aarch64_max_initfn, replacing it with calls to aarch64_cpu_common_init and cortex_a72_a57_a53_common_init. Cache and GIC configuration is now set directly, using aarch64_a72_initfn as a template. Set cpu->dtb_compatible to "qemu,aarch64-max". This has the following effects apart from the ones mentioned above: - kvm_target will no longer be explicitly initialized for cpu max in tcg mode. - id_mmfr0 will now be set to an architecturally permitted value. - define_arm_cp_regs() is no longer called, since those registers are implementation defined and specific to the supported cortex-a processors. Signed-off-by: Leif Lindholm --- target/arm/cpu64.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9927c1f75d..452efe78bf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -561,26 +561,20 @@ static void aarch64_max_initfn(Object *obj) } else { uint64_t t; uint32_t u; - aarch64_a57_initfn(obj); + cpu->dtb_compatible = "qemu,aarch64-max"; /* * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real * one and try to apply errata workarounds or use impdef features we * don't provide. * An IMPLEMENTER field of 0 means "reserved for software use"; - * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers - * to see which features are present"; * the VARIANT, PARTNUM and REVISION fields are all implementation * defined and we choose to define PARTNUM just in case guest * code needs to distinguish this QEMU CPU from other software * implementations, though this shouldn't be needed. */ - t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); - t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); - t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); - t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); - t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); - cpu->midr = t; + aarch64_cpu_common_init(obj, 0, 'Q', 0, 0); + cortex_a72_a57_a53_common_init(cpu); t = cpu->isar.id_aa64isar0; t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ @@ -680,12 +674,24 @@ static void aarch64_max_initfn(Object *obj) * and enabling SVE in system mode is more useful in the short term. */ + cpu->reset_fpsid = 0x41034080; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + #ifdef CONFIG_USER_ONLY /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. */ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ +#else + cpu->ctr = 0x8444c004; + cpu->dcz_blocksize = 4; /* 64 bytes */ #endif }