From patchwork Wed Jun 10 16:06:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598257 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B11414E3 for ; Wed, 10 Jun 2020 16:08:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FC5A2072E for ; Wed, 10 Jun 2020 16:08:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dv1+MAQe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730472AbgFJQHN (ORCPT ); Wed, 10 Jun 2020 12:07:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727813AbgFJQHM (ORCPT ); Wed, 10 Jun 2020 12:07:12 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3460C03E96B; Wed, 10 Jun 2020 09:07:10 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id e12so1807923eds.2; Wed, 10 Jun 2020 09:07:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2wtQFXbmzC4/d8oVsOGWU0M31JIOAZfPwOO9JlNgV6A=; b=dv1+MAQei2yu8tc9NiXHkLyBVWamgfvo5hf7Ahs8ZyjcGI1rRUQJyLb4KhMwIbl3Ky r8uYILKaDzbyCLJ7Qn5R7XQ3LBHXGFqtB9LvSEHpJLhHJwsPADJnlaFrhY3Y9zwE5RGP V26rH3jLZ08D8pXWgVrxAL7ChENSwZ9OEIZVgl7EU5jcszt2vr4/3JeUyW+VNmXAW6kp Eio2wgiGor/5R75FCRaYGzyD3/9Lv1nuYlT/e+ctC/D66UO9owkDHsyd9XpIFewBWhVe UdVCAVH51oslV23eZDhRpiOcYRLlA1Ydq70ow0FDnUy3O/DhpaJmNIkWhg7QNEYCwnUu l5+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2wtQFXbmzC4/d8oVsOGWU0M31JIOAZfPwOO9JlNgV6A=; b=phQe8i4dZkdDubvzAIPTZgmL4BIn01BbEH5F9Dm2fDjKSozq+gyr0QMRPflL8W1EtQ N2LBp/dwWVz2c4dtXwlXhIBfwwVtulLLxgMftgqkIBGM+pXFM/43IibIKuxcqrIw0Eq1 T9XZ4RhPBScRa1cDoyMpcRjLp1ySpnX6Pns5kEovxX5XMR3QmgNEPEnHt/4MMEgX4egc 35KxesmdNzLbTgZLGAm6aVBRvo5Vm0RwOQI0VybE0ZrVi31tK2Z0vkFFAY3PBneSyeLc Ex+XonG5yyXSSjWjC+KGOUrTnj67no0eBYISyde4U1At2xv86fVl7OjvxqNSg6uqWu4S R2Hw== X-Gm-Message-State: AOAM531SwGCJJNYgf2U+nw/3neJpJml0oKFGcgEKMbeSE3rTl0V+CWm7 74+xUgM4fBNacrl2W3+IvLc= X-Google-Smtp-Source: ABdhPJypmstF+84GTqUN05fLQyZM319vjxm1J2mVMRgUv3VAZi9aErb6Dn+C+VwbxhOeL3iQpyzoyQ== X-Received: by 2002:a50:d556:: with SMTP id f22mr3178103edj.307.1591805229333; Wed, 10 Jun 2020 09:07:09 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:08 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Sham Muthayyan , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 01/12] PCI: qcom: Add missing ipq806x clocks in PCIe driver Date: Wed, 10 Jun 2020 18:06:43 +0200 Message-Id: <20200610160655.27799-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Aux and Ref clk are missing in PCIe qcom driver. Add support for this optional clks for ipq8064/apq8064 SoC. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5ea527a6bd9f..4bf93ab8c7a7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; struct clk *phy_clk; + struct clk *aux_clk; + struct clk *ref_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_clk)) return PTR_ERR(res->phy_clk); + res->aux_clk = devm_clk_get_optional(dev, "aux"); + if (IS_ERR(res->aux_clk)) + return PTR_ERR(res->aux_clk); + + res->ref_clk = devm_clk_get_optional(dev, "ref"); + if (IS_ERR(res->ref_clk)) + return PTR_ERR(res->ref_clk); + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) return PTR_ERR(res->pci_reset); @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); + clk_disable_unprepare(res->aux_clk); + clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->core_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable core clock\n"); + goto err_clk_core; + } + ret = clk_prepare_enable(res->phy_clk); if (ret) { dev_err(dev, "cannot prepare/enable phy clock\n"); goto err_clk_phy; } - ret = clk_prepare_enable(res->core_clk); + ret = clk_prepare_enable(res->aux_clk); if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; + dev_err(dev, "cannot prepare/enable aux clock\n"); + goto err_clk_aux; + } + + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_clk_ref; } ret = reset_control_deassert(res->ahb_reset); @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; err_deassert_ahb: - clk_disable_unprepare(res->core_clk); -err_clk_core: + clk_disable_unprepare(res->ref_clk); +err_clk_ref: + clk_disable_unprepare(res->aux_clk); +err_clk_aux: clk_disable_unprepare(res->phy_clk); err_clk_phy: + clk_disable_unprepare(res->core_clk); +err_clk_core: clk_disable_unprepare(res->iface_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); From patchwork Wed Jun 10 16:06:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598255 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4769C1391 for ; Wed, 10 Jun 2020 16:08:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EFFC20812 for ; Wed, 10 Jun 2020 16:08:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="uQy9SEHa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730487AbgFJQHQ (ORCPT ); Wed, 10 Jun 2020 12:07:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730485AbgFJQHP (ORCPT ); Wed, 10 Jun 2020 12:07:15 -0400 Received: from mail-ed1-x541.google.com (mail-ed1-x541.google.com [IPv6:2a00:1450:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E149EC03E96B; Wed, 10 Jun 2020 09:07:14 -0700 (PDT) Received: by mail-ed1-x541.google.com with SMTP id g1so1796284edv.6; Wed, 10 Jun 2020 09:07:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m/L0NRU1j/c6I13faHhGrI6qUdNFYftXq3aP75qQONs=; b=uQy9SEHaGtNMnsvTAeJWKrKMQ+cGjeS3LV6rQlyngG/2j7zOxKRWMoO3r+unHO84th q+2LZ9M/mtIWxOTzoTFlvstdJzxAoy5+ijY43i58WS1MhSZPkvsZoT7Cgjy2I91uJsWw JMrt/xphxDHbIsfDM+xOXvUtGLEoo+jIt22xaCgDhZg07G58YgeAnnwJo/aXMHhPeSnZ Yyd1L1/poEBsgW0Jvth+6c6vm4/kR67klSZN9AO0W0Tywv4ZLBQeFxFdXshr1AxRIRca JwjDyQHDfaXiG8qb/zPRU0WE5rNzHkv5mw21pXgNsMc8iCLKzwlo7UbsyTMsrrCZgm4w RP6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m/L0NRU1j/c6I13faHhGrI6qUdNFYftXq3aP75qQONs=; b=OlRQoP5FBzd2eydJdTHtDWr5IWrJwnkErEQ0GXUrqJLvFgY8u03yL25/VJC5fgclGu 0APT7YJPKBjR4xhGnvj3TeRGQ31favmvKHQaJ9BnWX/Lw4uTxfK1MGH3F/SeQCeNa4Qz /RBpun15rTr/HjhQIY3G0jNufyiTkeRCfPJvvL6ytmyrNIeI/t5BMHeoYEhkMZjp976T v6eVodzhGuRQ6YZBr/JZ5LYsqwwALCI5MA+c1R3xLlS1eHWJIt2qC4KjsJUS1QsoNl28 ENsL142pgLrjiP3fdJX0cmskxJGlPoAOf9L8wtA36HDAg+n1p5LQcgOWPIOrfwSWQnug 4EIw== X-Gm-Message-State: AOAM533Pb3++rsPFMg1gVZXpw83wdzv6X0XXU7BT6dFH7Rb7LYh+bdhm aa8z95Sy65W122lkuaNQhWY= X-Google-Smtp-Source: ABdhPJxKuhR5NvldILEwnAyEs/nq65D+XrwXXqi18nQAkzvhQOAEBt6HvaBSyq30vEtGPB2IrEburg== X-Received: by 2002:aa7:d6d0:: with SMTP id x16mr3191750edr.175.1591805231622; Wed, 10 Jun 2020 09:07:11 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:11 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 02/12] dt-bindings: PCI: qcom: Add missing clks Date: Wed, 10 Jun 2020 18:06:44 +0200 Message-Id: <20200610160655.27799-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document missing clks used in ipq8064 SoC. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Wed Jun 10 16:06:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598253 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A08F14F6 for ; Wed, 10 Jun 2020 16:08:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E6DC52078C for ; Wed, 10 Jun 2020 16:08:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="C+9URlX4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728063AbgFJQIN (ORCPT ); Wed, 10 Jun 2020 12:08:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727813AbgFJQHQ (ORCPT ); Wed, 10 Jun 2020 12:07:16 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA3A6C03E96F; Wed, 10 Jun 2020 09:07:15 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id o15so3160545ejm.12; Wed, 10 Jun 2020 09:07:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s9klwDUAQHUdrbunE/kS0tb+TnD6OrjCFpNB//xZIAs=; b=C+9URlX4DDs1ExBwdqCpKQePPhHXWLqg7VfMAB1p74sOH/oSGm81fKdRIqIQ2lbDNd 13zFYSQEl5Q27eSMuAWbg622Ir+PP06KG201o+vC9CR/dqIYSSht1ZTBD0RQmb/6FIJu a6pofmnLWyIfZuEesX9Dh+Op5q7Xht9R4ZzyROXqps93PelML1K/nElH1DSmSROmxZft cBwqrKxBG+dAXUIhHYjj2Ui4LqixTqk7ziLLyw9JkTynjVbpO/u7BlGnDYkmVvmXovTn vs4jGLtfgH7mYBUKNg5gC+ruzunzRTmCkdHssTFHfyCRBd2g0drKEpZPI6V74Vn2zgt/ 5EPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s9klwDUAQHUdrbunE/kS0tb+TnD6OrjCFpNB//xZIAs=; b=pmk/9FI3PPrQ4NjbkpNuEK9VJViIFu05LXXkRGG1AOp1q8DiVl1jAGBPf9virT/QOC uaooJTpKwovp3DayPOLew/DFolY9a92OMF/15ae587SjpggDovp4yT1d9vWPqqQfkmiU yws0hE28YSTHNgeGEkA1PgeAeR/Aqr3oVTd0FrVMC63nxdvE5lRFTSG3QRZl+dNOFqFt Iuu7Ra6ykjzbsGgFQJEXfZ7HYMwQuXllqyDL3azbZPF3pF5ZNl/e6kKh26vm9LBg+5lu RQ9fRTF0SoLRY5CjeMvTgOL9FLFVozBtgkFesMST2YJFpN02CbubMaYwcpPlxWNi/cCa DYaA== X-Gm-Message-State: AOAM531UvytO6TfLZzaBgsDrvzQNHxGyBGY7Wnd20gylYFXr956e20II KLUHZmQ+/CmYtbko0jPX6cNLfPp18jTsEMgI X-Google-Smtp-Source: ABdhPJz996mO0a7CqiD4hWF2x1UtjKNsu/VbgUDj81kz742RAwI7WZqdB7LHe6rIz1UeYCp3P0+g/A== X-Received: by 2002:a17:906:1d1a:: with SMTP id n26mr3897465ejh.351.1591805234537; Wed, 10 Jun 2020 09:07:14 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:13 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Abhishek Sahu , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 03/12] PCI: qcom: Change duplicate PCI reset to phy reset Date: Wed, 10 Jun 2020 18:06:45 +0200 Message-Id: <20200610160655.27799-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhishek Sahu The deinit issues reset_control_assert for PCI twice and does not contain phy reset. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4bf93ab8c7a7..4512c2c5f61c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); + reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); @@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Wed Jun 10 16:06:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598247 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D32514E3 for ; Wed, 10 Jun 2020 16:08:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75F24207F9 for ; Wed, 10 Jun 2020 16:08:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D5avXRJ0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730496AbgFJQHU (ORCPT ); Wed, 10 Jun 2020 12:07:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730485AbgFJQHT (ORCPT ); Wed, 10 Jun 2020 12:07:19 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 798D2C03E96B; Wed, 10 Jun 2020 09:07:18 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id p18so1794406eds.7; Wed, 10 Jun 2020 09:07:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0T+25FzC3m+ZCfSnTnyTsPpwm0TEOUYS6HI+FaVLFf0=; b=D5avXRJ0CRE/hkpdok7mBnAiikNs9W5NkXT2b9BVl6NYMzgReCYOdrGmGIGvPSBwZl nxl4XzLAKjaPSQjkfVl/HZD8DFloH1qiDSKyADt57D5apRKldzZs7BDidQJFY9wcofhq PXk6APfsy+7jVgM5MFCVkP/zp35AYMbhXk/lubgfOpZ6HG30lT0PCopglonPazmanWmn lhQETTrZ9GrQT4mqGn9tGmsgdrD/yjL0LtKOC7T8FKTYdcIpXV7hsJbYSW6MpLTRJdvX dj5evpQ16e0MVlWqg7hZLVhdSTzZJJhniR6UlmhBd8QrrlwZX6hGWALkN4WP4K9Avh6L 5HUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0T+25FzC3m+ZCfSnTnyTsPpwm0TEOUYS6HI+FaVLFf0=; b=mYQksZxnjadvLEVMaCQSfYst33NRdef4PWSuKaNIVDsCF2DabPGwMJObUdHOdGR2bS wmq58Y3HycRkUzYwKmXPNPBYpF/IaK4PmoIwEhrU/UNZJXeezQ0TbanyUzu2mz2IqiHN PZQfkPDe1FQKzz/FOk+2b4xdDl5hVbMxIXjhjT56EvTlIeP2gXxRk04B3nXu6Np2Tlfs PCCNWORX4TcjCUVJwOuJdk0Vv6DEHI/DLkjJLBSHE9qp3Vw/wCviTF6IGzm6PX+R589e hjM3+MAdYjtoyujXqs/80XuGQ41nPHep4gGqSTMWhik+wxv8FYo3fT4qx0BBHxItjPQq Bn3w== X-Gm-Message-State: AOAM533kzBc4+GNMbposxlQjpGXQCu6gj3Xj5qdnNySO1FKVPNdeCa6h xJwaF+MPWUVuyGfN5Ww73jA= X-Google-Smtp-Source: ABdhPJw+bu9CjVuWWI4xfytkCvENopNDNd4j1yWIK6dWj7rf/Gzq6rA7aX+qYELKxvGHFPBzRi8Tyg== X-Received: by 2002:a50:fd05:: with SMTP id i5mr3022459eds.79.1591805237150; Wed, 10 Jun 2020 09:07:17 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:16 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Sham Muthayyan , stable@vger.kernel.org, Rob Herring , Philipp Zabel , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 04/12] PCI: qcom: Add missing reset for ipq806x Date: Wed, 10 Jun 2020 18:06:46 +0200 Message-Id: <20200610160655.27799-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ Reviewed-by: Rob Herring Reviewed-by: Philipp Zabel --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4512c2c5f61c..4dab5ef630cc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot deassert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); From patchwork Wed Jun 10 16:06:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1A7514E3 for ; Wed, 10 Jun 2020 16:07:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85EF92063A for ; Wed, 10 Jun 2020 16:07:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="k+bF1Whm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730510AbgFJQHZ (ORCPT ); Wed, 10 Jun 2020 12:07:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730506AbgFJQHW (ORCPT ); Wed, 10 Jun 2020 12:07:22 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9D6BC03E96B; Wed, 10 Jun 2020 09:07:20 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id q13so1806876edi.3; Wed, 10 Jun 2020 09:07:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ioo9tN1eVsbgycuXVtXW3j/mdJh9pHsUFw60B6xaAJg=; b=k+bF1WhmemJGb7/rN2yMZ3V5wpG5VUSckwq4ZFRcihddXrKOGEAhX/KLNFKfr8NIT9 2fqahGpki7zSY/17ubctHPUhyiGTOsUHEZsq2uLKwUGb+yrCujYIDO9Kphf5c6ry/iiv xqL0qxh3R/bzrokrJ9jkQmfU6NvjMlnLButsFctB5riWzebSevP83kzuKcvXubwEmsfj WNDQIDe/+/oQDZmsId5O1s8g7fsIaTvcFn/3kaBaIajCjQRXjfc97/Op//y7PlrA7jpH waMtfx3qAe+fVNp7LVQHw3kwwO0DrQPZ1wx3vWZU1pA95/xQd2KMf2lm2NeV1g0bX0ND AwUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ioo9tN1eVsbgycuXVtXW3j/mdJh9pHsUFw60B6xaAJg=; b=WL9Mcv3i4RvmzTst9MfltiF4sd5gT9CufSUnf2VU3JNBOWmdBFYnMXxlLca5PD6ROx RYPFX6ObxL8yFMXmsGOqGjv9ofaylI8Y4EmhbxLWCbj6QOWaoAmh3fXud3hlFSTDs/ji 6QOZdPeCuI27RP3BX0oB35FS4PO/2rfJM7mD0JQAfRjYF4hPb5+JnW8ybTlJJ/b6AUUQ WDYDu1RI5mS9YyWM9hH1vpmA5mJCH0iuDylkk1vsC+w3VO8z2HZ86Yt/7yvcZ/HPhOAT ztSeTBtCRKRRhdEXTCS3u3UXwRRje/L7qfwuf+ILVyJL5s/jAuUfQyfhu0pSmarqD64v dPXA== X-Gm-Message-State: AOAM5331TN3aYyVGZdN9dn6dgh4NLZGGoRxPygw45fgHHh6ILf8dZEIS CEtgDY3qykAyYl0qRd4Ahas= X-Google-Smtp-Source: ABdhPJwrLA8Bu4tlbBnnmWuLupJjY7NMw3oqzJ3tVY/+imD0cNevAFtZT9q8Xo4SuJqEIMy2yjlRNA== X-Received: by 2002:a50:ee08:: with SMTP id g8mr2917329eds.267.1591805239574; Wed, 10 Jun 2020 09:07:19 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:18 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 05/12] dt-bindings: PCI: qcom: Add ext reset Date: Wed, 10 Jun 2020 18:06:47 +0200 Message-Id: <20200610160655.27799-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document ext reset used in ipq8064 SoC by qcom PCIe driver. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Wed Jun 10 16:06:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598237 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF59E1391 for ; Wed, 10 Jun 2020 16:08:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B65BD2072F for ; Wed, 10 Jun 2020 16:08:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Zll90zRH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730579AbgFJQID (ORCPT ); Wed, 10 Jun 2020 12:08:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730485AbgFJQHY (ORCPT ); Wed, 10 Jun 2020 12:07:24 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93A90C03E96F; Wed, 10 Jun 2020 09:07:23 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id l12so3175635ejn.10; Wed, 10 Jun 2020 09:07:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zEaDqgFgLdCp9SI9RIDjLkOE1A27X8Da9cpu+tesTho=; b=Zll90zRHNW3+Bt5d2afTGpZOGjlPghMTJOIjLc5WXM51701EoDYdLAxEy48XjdJ7No iCktVOJKOSr8P3/LFMRQXW8wUR8FQEbvF++XnnU11AU5+0BZsFSiuxBRhFbaftb6/jW9 hWLgk/t6RrTycxkMQuRbE1KrLUYK4rqKG46gZzFLb+syz5IqCXZ7dlUKVdo7fLH9GZRM kxmOmc4OVVD4XTgpt9cpoLmgv9qCHU/mmtJBRUNY+Yyhnf/jje6Z+zKcg3DD5E+iP4l7 bCKWzAq+2cTyLbwPHJx8QpCqDXHF8WAsN8D1qaGNK7BShmd3yyt2Fm/IeYYvfZ+l0Nby ydPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zEaDqgFgLdCp9SI9RIDjLkOE1A27X8Da9cpu+tesTho=; b=Ja08+pNjZ+l1VBh3OAkUCcOogXhKcW4BPO0h8C9AjGO7gaA9mx8V5C/P6tTTXte84L fXt9ilM5USWI4acVdHUKo98xAb/8eMmgF9vdUgvxKzWB8dwyNRSZgvC9Elpl+Pk4m1Bg 7X/VLt/Uk4hl7FTqeB/BiE0AXNq9r56kmWTN7IccP0c+TnTk4CzF95/rP1bUGfMQgCZG B03h9aSvh954pHpUvgp+NhtGAN0YrN65fZ1lKliObd412xdw6w2/Y4kqzjCnTpzAVQns lGJ8uUZSimhGeHobBSpD7co8fYelkemZZeEO29fpe8RHNO6osLKN8ePZElqZUSGaC4f5 /c7g== X-Gm-Message-State: AOAM532YaI2yduEcDO+4we+K0MiRPvSJjNrE8na81ZpU9ppsaLpDV1jf tFooCjsDgs7xkFhVEY1WS00= X-Google-Smtp-Source: ABdhPJzRHaUCCRTimWA52dbg0bDTNzKdEM/XlLrh7hR0uPAsWlXzdLOs94j1yO6OQsYEUPqHHIuD4Q== X-Received: by 2002:a17:906:799:: with SMTP id l25mr3993618ejc.234.1591805242054; Wed, 10 Jun 2020 09:07:22 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:21 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 06/12] PCI: qcom: Use bulk clk api and assert on error Date: Wed, 10 Jun 2020 18:06:48 +0200 Message-Id: <20200610160655.27799-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework 2.1.0 revision to use bulk clk api and fix missing assert on reset_control_deassert error. Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 131 +++++++++---------------- 1 file changed, 46 insertions(+), 85 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4dab5ef630cc..f2ea1ab6f584 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -84,12 +84,9 @@ #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; - struct clk *core_clk; - struct clk *phy_clk; - struct clk *aux_clk; - struct clk *ref_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (ret) return ret; - res->iface_clk = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface_clk)) - return PTR_ERR(res->iface_clk); - - res->core_clk = devm_clk_get(dev, "core"); - if (IS_ERR(res->core_clk)) - return PTR_ERR(res->core_clk); - - res->phy_clk = devm_clk_get(dev, "phy"); - if (IS_ERR(res->phy_clk)) - return PTR_ERR(res->phy_clk); + res->clks[0].id = "iface"; + res->clks[1].id = "core"; + res->clks[2].id = "phy"; + res->clks[3].id = "aux"; + res->clks[4].id = "ref"; - res->aux_clk = devm_clk_get_optional(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + /* iface, core, phy are required */ + ret = devm_clk_bulk_get(dev, 3, res->clks); + if (ret < 0) + return ret; - res->ref_clk = devm_clk_get_optional(dev, "ref"); - if (IS_ERR(res->ref_clk)) - return PTR_ERR(res->ref_clk); + /* aux, ref are optional */ + ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); + if (ret < 0) + return ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) @@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - clk_disable_unprepare(res->phy_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->aux_clk); - clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->iface_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->core_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; - } - - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; - } - - ret = clk_prepare_enable(res->ref_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ref clock\n"); - goto err_clk_ref; - } - ret = reset_control_deassert(res->ahb_reset); if (ret) { dev_err(dev, "cannot deassert ahb reset\n"); @@ -352,48 +311,46 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) ret = reset_control_deassert(res->ext_reset); if (ret) { dev_err(dev, "cannot deassert ext reset\n"); - goto err_deassert_ahb; + goto err_deassert_ext; } - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - - /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); - ret = reset_control_deassert(res->phy_reset); if (ret) { dev_err(dev, "cannot deassert phy reset\n"); - return ret; + goto err_deassert_phy; } ret = reset_control_deassert(res->pci_reset); if (ret) { dev_err(dev, "cannot deassert pci reset\n"); - return ret; + goto err_deassert_pci; } ret = reset_control_deassert(res->por_reset); if (ret) { dev_err(dev, "cannot deassert por reset\n"); - return ret; + goto err_deassert_por; } ret = reset_control_deassert(res->axi_reset); if (ret) { dev_err(dev, "cannot deassert axi reset\n"); - return ret; + goto err_deassert_axi; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_deassert_ahb; - } + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret) + goto err_clks; + + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~BIT(0); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + + /* enable external reference clock */ + val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); + val |= BIT(16); + writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; +err_clks: + reset_control_assert(res->axi_reset); +err_deassert_axi: + reset_control_assert(res->por_reset); +err_deassert_por: + reset_control_assert(res->pci_reset); +err_deassert_pci: + reset_control_assert(res->phy_reset); +err_deassert_phy: + reset_control_assert(res->ext_reset); +err_deassert_ext: + reset_control_assert(res->ahb_reset); err_deassert_ahb: - clk_disable_unprepare(res->ref_clk); -err_clk_ref: - clk_disable_unprepare(res->aux_clk); -err_clk_aux: - clk_disable_unprepare(res->core_clk); -err_clk_core: - clk_disable_unprepare(res->iface_clk); -err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); return ret; From patchwork Wed Jun 10 16:06:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598243 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6FD9C1391 for ; Wed, 10 Jun 2020 16:08:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 560872072F for ; Wed, 10 Jun 2020 16:08:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cavjiXgg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728093AbgFJQIC (ORCPT ); Wed, 10 Jun 2020 12:08:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730516AbgFJQH0 (ORCPT ); Wed, 10 Jun 2020 12:07:26 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 288CDC03E96B; Wed, 10 Jun 2020 09:07:26 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id o15so3161216ejm.12; Wed, 10 Jun 2020 09:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lQYgSDTotq5c/39ynoudMriyL83LIjVkw0hGmAWFKNE=; b=cavjiXggwo0vFzCxAxw+P3TdRlfvsyBHodQC6f7sowYmA+D1x3mGL92MfGpLuyAmR1 xH/zAHfeVVjOsOe76cGqtIFd8o/UJP1qawtdS5Wxbu1PkjA4CdyP1OUWBO4NkcaQ27KA x2vSU5zpbncHz6j5p93XMX/yQdsUZXZq83FrpnbkbFqilyE4mZB8QuQKYLYB3qDX+FV9 1NUNX2t9HlMLS3ovB0arMBFLorAjimDXWjLMn6YWakR3jHLbZN4/E6g4sterY7/kSD7j +FnGqAacrSIIWn83GWhzCxtVh3IBiADhnOggS16d+y8Hb1OklUGCu0PqP143i7vBE6MJ 067w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lQYgSDTotq5c/39ynoudMriyL83LIjVkw0hGmAWFKNE=; b=RbM+XY9Ez1TR+X7rUqrml0vpH/C+OwnlmGcqJF2TavGgbbg8gmShGGEOLVE9Fdfuyv Crxqe9dfU3gvfVHjYoyBgnJJ1u5QP2SpD2Oddg0/gdktE+SjbE6ZKvBr6euYt5UEgdHn fubslMN8xYPmiXKa9dWR2S28yaZ1rrLoJUKMkZYEM7mFoI4e3b84nB2NPNbRT36xA3Is mwbMeVGo6Z4nWueaVBXCz6pXdp+8UiTebauAdEOyWSQy7odVM5C8RB2qotHTJpZZZ2Dt 41BA1l3C8r1yDldM0xRvJmdIlAsVWdbdbnwisvU53Ja0nbuW8b8U3DDpaGBX66Dg7Cvh rNzw== X-Gm-Message-State: AOAM532FnhqFbAIRGqdJxX88e/m4BYim2WuBMpe1jQUvIEZ/A2uRvWdR MAWgi+r1BaUlmR1mw65XIy0= X-Google-Smtp-Source: ABdhPJybsQAvzxQa692WxmMix+SEuqe+73dP+MscVMYrY4v0X3F/kEL+d1AnGnc0Aed6wHQSIVZcmA== X-Received: by 2002:a17:906:3da1:: with SMTP id y1mr3920586ejh.109.1591805244676; Wed, 10 Jun 2020 09:07:24 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:23 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , stable@vger.kernel.org, Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 07/12] PCI: qcom: Define some PARF params needed for ipq8064 SoC Date: Wed, 10 Jun 2020 18:06:49 +0200 Message-Id: <20200610160655.27799-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization needed on some ipq8064 based device (Netgear R7800 for example). Without this the system locks on kernel load. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f2ea1ab6f584..85313493d51b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -77,6 +77,18 @@ #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) ((x) << 24) #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -293,6 +305,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + struct device_node *node = dev->of_node; u32 val; int ret; @@ -347,6 +360,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(120) | + PCS_SWING_TX_SWING_LOW(120), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); + } + /* enable external reference clock */ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); val |= BIT(16); From patchwork Wed Jun 10 16:06:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B4AE14F6 for ; Wed, 10 Jun 2020 16:08:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E78722072F for ; Wed, 10 Jun 2020 16:08:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="f8VFo0Rw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730506AbgFJQHa (ORCPT ); Wed, 10 Jun 2020 12:07:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730520AbgFJQH3 (ORCPT ); Wed, 10 Jun 2020 12:07:29 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A62A3C03E96F; Wed, 10 Jun 2020 09:07:28 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id t21so1779923edr.12; Wed, 10 Jun 2020 09:07:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jXtz99iuv/ovCkSGf6u5INPEkSX0yyHnlwxRCUFR+S8=; b=f8VFo0RwITPFhS+h5gblSA0oIENLUYtFC6Oex0pL2SmjXwPu4Bs8FyjUc96ACUxTtx 2w4OtgtcEASS9sAWuPSaTyzXTNskP9/MOmbITNlLphWz8osqrYDd+casl3ABNqgpLnzp a+XlYTFXEMVcGTevkIAQ8DxkgykmTAyxr9VOq7WLJ9zuJSi+mm+XfowAzOdVOs7UfYL2 c2kfDVyrlSweRtRYzqunb+YY+fGKRp+4m1dTAC3ycHqpQRdm0JQyGrjgAKNADrp1RViQ HP0GaRIaUP0KDY4RZQHZB6lq5FIGgJwuGqFCYCynP9zaPTwhphGZjbLlRh7OnujW0K/B +kCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jXtz99iuv/ovCkSGf6u5INPEkSX0yyHnlwxRCUFR+S8=; b=gIWrc48449geZvO4VhAKxgfVOezF0c93hS1sd90+Tt6K7BtHHe7guqvmS3BbBU/R1n YY6HDmCVKIxD+cRjPld6RLROJHMSYnus95C0ztQHKITHDWo0aBczui9wZsPh5UAzjKd7 c4sbR1u/v6aZOGUu9Eps3WnXFyRWP52rTnn11ByXUQGhtrWqPcd6MFj85wkCPCd9m1/8 452Nlb5p2hyR3++075UbaKrMX1AvaL2ZVBXMxv7Zkp2uRis60eqXgusyxWQWPXcBbYFR I8uqHOBmxnlpjkrDSzhZ98Jpc3QsLCZGRD6wP1JNOV8khWHzYng4foAEGjqcq20L/2qA TljQ== X-Gm-Message-State: AOAM5325qjEREsSHP1KOgQG64RhH43wz2XHhVeVaKyu98YeAkAYNUKy2 NUhw+EV4tAmaBzZAoQq+y3k= X-Google-Smtp-Source: ABdhPJxNG24XUh5bQCrgMinY31VYsYlwkitpbR8b8nscOm4hE2+AuB+AsLZHKlfWigsidfDlm3KAyA== X-Received: by 2002:aa7:de08:: with SMTP id h8mr2989096edv.164.1591805247304; Wed, 10 Jun 2020 09:07:27 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:26 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Sham Muthayyan , stable@vger.kernel.org, Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 08/12] PCI: qcom: Add support for tx term offset for rev 2.1.0 Date: Wed, 10 Jun 2020 18:06:50 +0200 Message-Id: <20200610160655.27799-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add tx term offset support to pcie qcom driver need in some revision of the ipq806x SoC. Ipq8064 needs tx term offset set to 7. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ --- drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 85313493d51b..2cd6d1456210 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -45,7 +45,13 @@ #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 #define PCIE20_PARF_PHY_CTRL 0x40 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) + #define PCIE20_PARF_PHY_REFCLK 0x4C +#define PHY_REFCLK_SSP_EN BIT(16) +#define PHY_REFCLK_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -371,9 +377,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); } + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + /* set TX termination offset */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; + val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + } + /* enable external reference clock */ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); + val &= ~PHY_REFCLK_USE_PAD; + val |= PHY_REFCLK_SSP_EN; writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); /* wait for clock acquisition */ From patchwork Wed Jun 10 16:06:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598225 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C60C91391 for ; Wed, 10 Jun 2020 16:07:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AAB562083E for ; Wed, 10 Jun 2020 16:07:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OYhJZqxK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730535AbgFJQHi (ORCPT ); Wed, 10 Jun 2020 12:07:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730484AbgFJQHc (ORCPT ); Wed, 10 Jun 2020 12:07:32 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46052C03E96B; Wed, 10 Jun 2020 09:07:31 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id x1so3191278ejd.8; Wed, 10 Jun 2020 09:07:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qi0pxCVqozd5V1/C140EBqHG2/fFl/8biYimGdOF39g=; b=OYhJZqxKYA02dv6FrmtRjRZ5PVMcx69+LOjMfMNO6kvnu9s+9LV2VXORjr1baHlNNF WNkLegfe8tOXHpSiG7q939NUdgv4jU90JqIaSrBOWHBi9WLqdnYjyW6WtDXqG3Lw8hST OYQ+BA2lokhOYpZbKJuqpsdT2poLtJ1BRE4rxM6drdmocKRdTko1UWgWz8qm5oa5ODuO uO4apqF34m0z+oQ1sZ99kBFM8Gk67N10vYtXzVGz9z43piSPYDaOXtwj4qQcw0RSISxR Q4VxuIAlbAOTgOBwxSDdpAQa/Ikbd9zj1W0KE56TDTR1+oWuHHVKJLbyiqPT4Ceu611D +wKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qi0pxCVqozd5V1/C140EBqHG2/fFl/8biYimGdOF39g=; b=imVSph0AKkNFQzOBdgAhzlkYV0XG7RfYJKksx7LMfnZYBeWz7+xhJnqDzsK4+7AxS5 OmYPaw0h+vvj9Hql3YjuwhbzstY6PZUnzDK0mZrTHKgPeQy/A4rpGfGBUSo6V2bv0rmD kR8h3mSSUD/NobQjdbBfDflxhtAneu6Wd4xmKvM/n/yndc6WW0PmPauV/Yf8RuPLzzyH XYIGH0yW2RtayWHXxp5V199P8o9cBa7xbWxqX2/qrc1+AafMd00uGj6qb1yOlFF4lAld n+RafhahEK7c1S6dH51wegVon+y1/Eka37+PPu2AOR/k4Iz6eESthxIetEgexS3dO5Zv Vmww== X-Gm-Message-State: AOAM532gb0Xvci9OjXNbrxEXxjlTCQm4cboIeop6+IIc75c3BwkA8B6e PcKQiwPM6H2plZA0w/ApRxE= X-Google-Smtp-Source: ABdhPJweC2I3mf2asfrT9CsXI7pjIQzvJIPWLQbk9FTXXsWsuD9GKAhuuni9YKsES2kuEdxtq6EzZA== X-Received: by 2002:a17:906:480f:: with SMTP id w15mr4069195ejq.430.1591805249894; Wed, 10 Jun 2020 09:07:29 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:29 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 09/12] PCI: qcom: Add ipq8064 rev2 variant Date: Wed, 10 Jun 2020 18:06:51 +0200 Message-Id: <20200610160655.27799-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit different offset based on the revision. Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2cd6d1456210..259b627bf890 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -366,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || + of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), @@ -1464,6 +1465,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, From patchwork Wed Jun 10 16:06:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598217 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE86614E3 for ; Wed, 10 Jun 2020 16:07:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6A19207C3 for ; Wed, 10 Jun 2020 16:07:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XZId+kqz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730532AbgFJQHh (ORCPT ); Wed, 10 Jun 2020 12:07:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730528AbgFJQHe (ORCPT ); Wed, 10 Jun 2020 12:07:34 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6084C03E96F; Wed, 10 Jun 2020 09:07:33 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id p20so3163769ejd.13; Wed, 10 Jun 2020 09:07:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZIcmPOVlQLoKdIP9dCKqwaemztdzBXHNcMiHg1REgA4=; b=XZId+kqzhEi16ADYn9UF8ygFXk5SH0ej/H5Fbz/qBQO7EKQTbrA31hza5a9uuwg1qY R2Ta2p/5jXwEbU8NKmjPt9XAKrE2lHnzuimLLZ4bN638YfuSZDLp3Y92yRgz6tEIeuaY pZ327mRywwATOIbKGxpqCfIrhum5FOsNIYUldzEi0FtN7SNXIya9uQu+GKikYJQjSCYZ 2D8as6OSR1mL0nUBW4d0/sGaIwG/YLoVVP2Pvu0M16zqrOyuSRf9+aHUhcswiL0WTgb/ MOFPQdUlfb2J+79XZpujH3pmbCG/Wyi2omUnbltMdXlKzTrhJVXkxnuCAreKpvz+TVem emKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZIcmPOVlQLoKdIP9dCKqwaemztdzBXHNcMiHg1REgA4=; b=lD1TPohP2RrnQuX3w6dL+pXXNVTYNPPn0DmIsEVJqIaOzqbvJrAETle5nw2lGZa/IG z50GCeK2J0GmKQa3R0LPqvhclfcFP+JSpn1ZxbV14dWl3O4lm01CxWm8fpbAlSuy3BBO JXPH8tN62S3fSfdVZ4gonaStX2J6pku8TUANNzyy96i8HBa1TWTl4rkh4W9YAOIE3xyx IRWySMYydNYwJgJDftQmTxhXouALDFCnowgR/yce5znkyKqrsPRX47LfFr+oSfkwdAds HhmgvJ/Xq/GHdfFedaKcwUykuvhcXKhcuf5R07rlXUkW5am9DhEg8nd3Sdy7hKgJJJx9 c2Hw== X-Gm-Message-State: AOAM531ndZ9XIJw3fkks4ZvCOUe5IQO/6J4EkvzdcYhRqba0DSU+RGcF /SMinsaoQ3sMz4oHg0CN+B8= X-Google-Smtp-Source: ABdhPJz/z0uv04oFo6Ksal5X8QjDiPKT0GLx7HBWK77h+M6TKECl0WPlUJd694bF0JH9Cml7V8haAQ== X-Received: by 2002:a17:906:e2d5:: with SMTP id gr21mr3905582ejb.219.1591805252537; Wed, 10 Jun 2020 09:07:32 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:31 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 10/12] dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant Date: Wed, 10 Jun 2020 18:06:52 +0200 Message-Id: <20200610160655.27799-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset. In ipq8064 phy_tx0_term_offset is 7. In ipq8064 v2 other SoC it's set to 0 by default. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..02bc81bb8b2d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -5,6 +5,7 @@ Value type: Definition: Value should contain - "qcom,pcie-ipq8064" for ipq8064 + - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - "qcom,pcie-apq8064" for apq8064 - "qcom,pcie-apq8084" for apq8084 - "qcom,pcie-msm8996" for msm8996 or apq8096 From patchwork Wed Jun 10 16:06:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598229 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F27AC1391 for ; Wed, 10 Jun 2020 16:07:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D1CBC20848 for ; Wed, 10 Jun 2020 16:07:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Gw+n06Xh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730519AbgFJQHy (ORCPT ); Wed, 10 Jun 2020 12:07:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730494AbgFJQHg (ORCPT ); Wed, 10 Jun 2020 12:07:36 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B2EEC03E96B; Wed, 10 Jun 2020 09:07:36 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id q19so3194588eja.7; Wed, 10 Jun 2020 09:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JBawc5k6GxDTKkYoHLQZS2nVPl6YhwGiJUu0dW6sBLY=; b=Gw+n06Xh+9mlnB6Qq6ff5reYXGcVg6OypuPAc0+0amLiFLWO70fTOpvE88LwYtjYkZ qj4398gCR9Azojwj+5EXAw2iNhdVo/DIT9JkKQ0eODsIjmK7bTD5yy/fmd0lvG+1p4Vp zDzubVYds6eTSQVLTeGLqXx0CROZpxuYKDYEamwupuH3sUnJ76gqrX1YgiyFS4ayb7se UN6S60jMRDuI0co55E7l7VbLcHtuwmUsyM/gmavNdIRmGKtpPbhGU1fUcwdT8Eea4Xi5 VLFIYKx7oDGI8eGWqPDxhwD2wd7L+2+JQiJKZi/a68PIObreeL0XiW+GnRo6ihDZ0Y/Z AdGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JBawc5k6GxDTKkYoHLQZS2nVPl6YhwGiJUu0dW6sBLY=; b=ta0Sk4EG4Qavr7m9/PZCL6+liMfaObD8vAS5QLhDog9w3VZ8crYQ44DbWApXVN9nH/ 96PyLXjsZcSaZNgfq5YXJXZL1wZSQ2cIfdPdS3gealKFAscKbwmu1JnOWkZTby89cNFD iESv4C7ATjyEvjExqpdP+B6ixtX78dVSJX6T/uqSkPPepqOWj8bupPqbqi6lS6oFfK7O MDEspLtuTxrpUg3Epg/12PnbS5Xt3OiA1pUJsV+/rcigRXrovWkcfWA6vZoblLYwK3iP exPH0nZ20M+RqCiWweu1KAjAefiED3L2UZdvJrby3fGEoP5PCLDntv5Va+MIjkHCEi0b WHYw== X-Gm-Message-State: AOAM532xr4FKPcb/1KX2p59pfpTfzFZ53+GgcJobAsJiRR4WYj+4FLA4 wWspuhP7wTnroYn3E9TkRkM= X-Google-Smtp-Source: ABdhPJwiYTeGguvYZa0LgBVb566b/fEUL0GY/Kiywrpja0bmnzGWRJkmgPhiqMJdaI6XG2yTlc7VOA== X-Received: by 2002:a17:906:e0cf:: with SMTP id gl15mr4290108ejb.501.1591805255138; Wed, 10 Jun 2020 09:07:35 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:34 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Sham Muthayyan , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 11/12] PCI: qcom: Add Force GEN1 support Date: Wed, 10 Jun 2020 18:06:53 +0200 Message-Id: <20200610160655.27799-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq8064 board that needs to limit some PCIe line to gen1 for some hardware limitation. This is set by the max-link-speed binding and needed by some soc based on ipq8064. (for example Netgear R7800 router) Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 259b627bf890..c40921589122 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -27,6 +27,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE20_PARF_SYS_CTRL 0x00 @@ -99,6 +100,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -195,6 +198,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + int gen; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->gen == 1) { + val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + val |= PCI_EXP_LNKSTA_CLS_2_5GB; + writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node); + if (pcie->gen < 0) + pcie->gen = 2; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) { From patchwork Wed Jun 10 16:06:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11598223 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A22E114F6 for ; Wed, 10 Jun 2020 16:07:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 897B42083E for ; Wed, 10 Jun 2020 16:07:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FEePfPFg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730555AbgFJQHr (ORCPT ); Wed, 10 Jun 2020 12:07:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730538AbgFJQHj (ORCPT ); Wed, 10 Jun 2020 12:07:39 -0400 Received: from mail-ed1-x541.google.com (mail-ed1-x541.google.com [IPv6:2a00:1450:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7C89C03E96F; Wed, 10 Jun 2020 09:07:38 -0700 (PDT) Received: by mail-ed1-x541.google.com with SMTP id o26so1800436edq.0; Wed, 10 Jun 2020 09:07:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dd+Z0yjxtztXOTLMBUJZUOa3hEnZCJ80Y/mxXHp3PO8=; b=FEePfPFgVZZCcpcfMbca3kv5qq8lzcNem0TgiIVvPpHFnrRotBAN9YB5aQmHNhWhKQ aLiTvuCsFYiGd9JQQ9svqpqieWGj3TSHdWevq2KLr3Rr55eiyL/KHbDEUurSZFeObQ62 cGbttj7Yr+7cZYP/G4BEtTokTTNmiKA3cG3yE0sV0Y6UpkohjfW28kTFhfGMnhsn38/z HAIjsgcHlej5FedyfeIojDGj7G3ltRT6chJ5urtbVzVAZsSO2xbdeI5CC5yORrOYLh3C lomqJr0d4/ObImbSj2hjtmPlPkzzODpO7QlGH65ZHXND2ugo+ED/8m/XVMDYshbP/9+f TkCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dd+Z0yjxtztXOTLMBUJZUOa3hEnZCJ80Y/mxXHp3PO8=; b=uGqyTlnme+mZZ29VW53rtyXmQkQxsKKQ0sTxp2ZNPfkrGcV8TBt7uZVA2g+QRB3q8a YNQozaXIHO62QL1yKjeJ8iWndyRz8PK3FlDsg7o1Myv+Tmc3c8tkF65aC7HYVYmWvDwy Lp+sIXvJ/y6aMJSaQcz8FdD52ObicsDroRDqoEciBZSps30/4zWygQ2Tz7Co5whmufxC vFR6KQ1cRWnCsYijuf8qrS2t5iibORLbXJ1ZTMzuFAZogsi+0VU2SN3DGYHT2gzzTXoU mO3tq0zyJtvD4hno8FnNk8mO6obrrphVtSUu9OjAn8A6rQ89WPYDLse4hznxWcREufhw tMmQ== X-Gm-Message-State: AOAM533wb/AYM1ZFt3m8x04KcwqsklbryYB+qBRc/b5K3gSwQsqa70TV HL+MhvRn/x83YJgLlfoR5y0= X-Google-Smtp-Source: ABdhPJy2QXHTerysK0MjqZYcEjsPjCtx7EmQmhU2ZSQ6TRAOctZNgcI5WHuK8Ee76OAhZaUlgdyklA== X-Received: by 2002:aa7:c752:: with SMTP id c18mr3034215eds.55.1591805257335; Wed, 10 Jun 2020 09:07:37 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-79-35-249-242.retail.telecomitalia.it. [79.35.249.242]) by smtp.googlemail.com with ESMTPSA id ce25sm56067edb.45.2020.06.10.09.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 09:07:36 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 12/12] PCI: qcom: Replace define with standard value Date: Wed, 10 Jun 2020 18:06:54 +0200 Message-Id: <20200610160655.27799-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610160655.27799-1-ansuelsmth@gmail.com> References: <20200610160655.27799-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Lots of define are actually already defined in pci_regs.h, directly use the standard defines. Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index c40921589122..a23d3d886479 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -40,11 +40,6 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) -#define PCIE20_COMMAND_STATUS 0x04 -#define CMD_BME_VAL 0x4 -#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 -#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 - #define PCIE20_PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) @@ -73,8 +68,8 @@ #define CFG_BRIDGE_SB_INIT BIT(0) #define PCIE20_CAP 0x70 -#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC) -#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11)) +#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2) +#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + PCI_EXP_LNKCAP) #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F @@ -1095,15 +1090,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) pcie->parf + PCIE20_PARF_SYS_CTRL); writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); - writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); + writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT; + val &= ~PCI_EXP_LNKCAP_ASPMS; writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + PCIE20_DEVICE_CONTROL2_STATUS2); return 0;