From patchwork Thu Jun 11 09:19:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6D39D13B1 for ; Thu, 11 Jun 2020 09:19:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5375F207ED for ; Thu, 11 Jun 2020 09:19:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="CFz5N+Qk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726983AbgFKJTY (ORCPT ); Thu, 11 Jun 2020 05:19:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726831AbgFKJTW (ORCPT ); Thu, 11 Jun 2020 05:19:22 -0400 Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85A80C08C5C2 for ; Thu, 11 Jun 2020 02:19:22 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id e9so2289258pgo.9 for ; Thu, 11 Jun 2020 02:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LW44zHswuAYzMuilY+dT0iFunj9t8FpqpYAnSBU99cI=; b=CFz5N+QkeTGM4yda1nZnVC/ZMFmlXu+582R7ZVaux3GM4qfTIHjpZ6lDIshR9XLmBG vrxjmH2FQaN+MSwnSVQv+Kk/i4JhjLZCtg3A2JwvLJinbI9/xsNgcu59R1rYkfcB9QOU R1BQ3iYxPRKv/rNzpUhWu3KSivFr3KXXWer8w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LW44zHswuAYzMuilY+dT0iFunj9t8FpqpYAnSBU99cI=; b=i9PyOuV8XGbLauy6YLjtBdeKNrD9hV8A2OfjUTMgQ3O/ybJPd14f0X0cMh14xKsqAi 292PKY6Wxi704lcmueIF7vZG3uce2TspHHetWGrBjgkESe0WE3WSzaFOjvLGmhbiZLPf 5up36ZuKEEZsE5MxmnsJbY2bg7N2X55Jua8ydIUc/GeuXbfvxPaa55hSS0ctumUKZVry 6okto2t3G/nt+ml64dpB4uVyw2J1DD3p5PRPfUKh5fnf8R3VPx86ELQuM23mCVQl7p48 jtep1JL6BaaID7y8QusNTeqcqCvf30J36mkxD+UOer499NeaVop9MBXbOyIU+BIOwYVf 9/xg== X-Gm-Message-State: AOAM530wDhN3IjLAiea77I48DijEUqPmkZCRfnhCPvylL0wy8DYDqzHF hthiyyt2B7E4mmWkjur2cYbEtQ== X-Google-Smtp-Source: ABdhPJwPgVX/ocYKCdK6XF7rzt3W9lsXQBrRED0+FZWohspwIYG3N1BAVn1AUhU5q+HbySEnHPQwvA== X-Received: by 2002:a65:614b:: with SMTP id o11mr5971151pgv.443.1591867162069; Thu, 11 Jun 2020 02:19:22 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id 1sm2367852pfx.210.2020.06.11.02.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 02:19:21 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul Subject: [PATCH/RFC 1/8] phy: qcom-qmp: Move phy mode into struct qmp_phy Date: Thu, 11 Jun 2020 02:19:12 -0700 Message-Id: <20200611091919.108018-2-swboyd@chromium.org> X-Mailer: git-send-email 2.27.0.278.ge193c7cf3a9-goog In-Reply-To: <20200611091919.108018-1-swboyd@chromium.org> References: <20200611091919.108018-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The phy mode pertains to the phy itself, i.e. 'struct qmp_phy', not the wrapper, i.e. 'struct qcom_qmp'. Move the phy mode into the phy structure to more accurately reflect what is going on. This also cleans up 'struct qcom_qmp' so that it can eventually be the place where qmp wrapper wide data is located, paving the way for the USB3+DP combo phy. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Signed-off-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index d9d3e2fd4b53..fa8faa2d3d69 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1350,6 +1350,7 @@ struct qmp_phy_cfg { * @index: lane index * @qmp: QMP phy to which this lane belongs * @lane_rst: lane's reset controller + * @mode: current PHY mode */ struct qmp_phy { struct phy *phy; @@ -1363,6 +1364,7 @@ struct qmp_phy { unsigned int index; struct qcom_qmp *qmp; struct reset_control *lane_rst; + enum phy_mode mode; }; /** @@ -1381,7 +1383,6 @@ struct qmp_phy { * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count * @phy_initialized: indicate if PHY has been initialized - * @mode: current PHY mode * @ufs_reset: optional UFS PHY reset handle */ struct qcom_qmp { @@ -1399,7 +1400,6 @@ struct qcom_qmp { struct mutex phy_mutex; int init_count; bool phy_initialized; - enum phy_mode mode; struct reset_control *ufs_reset; }; @@ -2161,9 +2161,8 @@ static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - qmp->mode = mode; + qphy->mode = mode; return 0; } @@ -2176,8 +2175,8 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) void __iomem *pcs_misc = qphy->pcs_misc; u32 intr_mask; - if (qmp->mode == PHY_MODE_USB_HOST_SS || - qmp->mode == PHY_MODE_USB_DEVICE_SS) + if (qphy->mode == PHY_MODE_USB_HOST_SS || + qphy->mode == PHY_MODE_USB_DEVICE_SS) intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; else intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; @@ -2223,7 +2222,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) struct qmp_phy *qphy = qmp->phys[0]; const struct qmp_phy_cfg *cfg = qmp->cfg; - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); /* Supported only for USB3 PHY */ if (cfg->type != PHY_TYPE_USB3) @@ -2249,7 +2248,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) const struct qmp_phy_cfg *cfg = qmp->cfg; int ret = 0; - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); /* Supported only for USB3 PHY */ if (cfg->type != PHY_TYPE_USB3) From patchwork Thu Jun 11 09:19:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EAE61912 for ; Thu, 11 Jun 2020 09:20:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D271C20853 for ; Thu, 11 Jun 2020 09:20:01 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 11 Jun 2020 02:19:22 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul Subject: [PATCH/RFC 2/8] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' Date: Thu, 11 Jun 2020 02:19:13 -0700 Message-Id: <20200611091919.108018-3-swboyd@chromium.org> X-Mailer: git-send-email 2.27.0.278.ge193c7cf3a9-goog In-Reply-To: <20200611091919.108018-1-swboyd@chromium.org> References: <20200611091919.108018-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We already track if any phy inside the qmp wrapper has been initialized by means of the struct qcom_qmp::init_count member. Let's drop the duplicate 'initalized' member to simplify the code a bit. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Signed-off-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index fa8faa2d3d69..f3f0cab99ed0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1382,7 +1382,6 @@ struct qmp_phy { * @phys: array of per-lane phy descriptors * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count - * @phy_initialized: indicate if PHY has been initialized * @ufs_reset: optional UFS PHY reset handle */ struct qcom_qmp { @@ -1399,7 +1398,6 @@ struct qcom_qmp { struct mutex phy_mutex; int init_count; - bool phy_initialized; struct reset_control *ufs_reset; }; @@ -2114,7 +2112,6 @@ static int qcom_qmp_phy_enable(struct phy *phy) dev_err(qmp->dev, "phy initialization timed-out\n"); goto err_pcs_ready; } - qmp->phy_initialized = true; return 0; err_pcs_ready: @@ -2152,8 +2149,6 @@ static int qcom_qmp_phy_disable(struct phy *phy) qcom_qmp_phy_com_exit(qmp); - qmp->phy_initialized = false; - return 0; } @@ -2228,7 +2223,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) if (cfg->type != PHY_TYPE_USB3) return 0; - if (!qmp->phy_initialized) { + if (!qmp->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } @@ -2254,7 +2249,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) if (cfg->type != PHY_TYPE_USB3) return 0; - if (!qmp->phy_initialized) { + if (!qmp->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } From patchwork Thu Jun 11 09:19:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BDE0912 for ; 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Thu, 11 Jun 2020 02:19:24 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id 1sm2367852pfx.210.2020.06.11.02.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 02:19:23 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul Subject: [PATCH/RFC 3/8] phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' Date: Thu, 11 Jun 2020 02:19:14 -0700 Message-Id: <20200611091919.108018-4-swboyd@chromium.org> X-Mailer: git-send-email 2.27.0.278.ge193c7cf3a9-goog In-Reply-To: <20200611091919.108018-1-swboyd@chromium.org> References: <20200611091919.108018-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The serdes I/O region is where the PLL for the phy is controlled. Sometimes the PLL is shared between multiple phys, for example in the PCIe case where there are three phys inside the same wrapper. Other times the PLL is for a single phy, i.e. some USB3 phys. To complete the trifecta we have the USB3+DP combo phy where the USB3 and DP phys each have their own serdes region because they have their own PLL while they both share a common I/O region pertaining to the USB type-c pinout and cable orientation. Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can correlate PLL control to the phy that uses it. This allows us to support the USB3+DP combo phy in this driver. This isn't a problem for the 3-lane/phy PCIe phy because there is a common init function that is the only place the serdes region is programmed. Furthermore, move the configuration data that contains most of the register programming sequences to the qmp phy struct. This data isn't qmp wrapper specific. It is phy specific data used to tune various settings for things like pre-emphasis, bias, etc. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Signed-off-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 113 ++++++++++++++-------------- 1 file changed, 56 insertions(+), 57 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index f3f0cab99ed0..dace2f497c85 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1340,6 +1340,8 @@ struct qmp_phy_cfg { * struct qmp_phy - per-lane phy descriptor * * @phy: generic phy + * @cfg: phy specific configuration + * @serdes: iomapped memory space for phy's serdes (i.e. PLL) * @tx: iomapped memory space for lane's tx * @rx: iomapped memory space for lane's rx * @pcs: iomapped memory space for lane's pcs @@ -1354,6 +1356,8 @@ struct qmp_phy_cfg { */ struct qmp_phy { struct phy *phy; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; void __iomem *tx; void __iomem *rx; void __iomem *pcs; @@ -1371,14 +1375,12 @@ struct qmp_phy { * struct qcom_qmp - structure holding QMP phy block attributes * * @dev: device - * @serdes: iomapped memory space for phy's serdes * @dp_com: iomapped memory space for phy's dp_com control block * * @clks: array of clocks required by phy * @resets: array of resets required by phy * @vregs: regulator supplies bulk data * - * @cfg: phy specific configuration * @phys: array of per-lane phy descriptors * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count @@ -1386,14 +1388,12 @@ struct qmp_phy { */ struct qcom_qmp { struct device *dev; - void __iomem *serdes; void __iomem *dp_com; struct clk_bulk_data *clks; struct reset_control **resets; struct regulator_bulk_data *vregs; - const struct qmp_phy_cfg *cfg; struct qmp_phy **phys; struct mutex phy_mutex; @@ -1853,8 +1853,8 @@ static void qcom_qmp_phy_configure(void __iomem *base, static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; - void __iomem *serdes = qmp->serdes; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; void __iomem *pcs = qphy->pcs; void __iomem *dp_com = qmp->dp_com; int ret, i; @@ -1885,7 +1885,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ret = reset_control_deassert(qmp->resets[i]); if (ret) { dev_err(qmp->dev, "%s reset deassert failed\n", - qmp->cfg->reset_list[i]); + qphy->cfg->reset_list[i]); goto err_rst; } } @@ -1960,10 +1960,11 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) return ret; } -static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) { - const struct qmp_phy_cfg *cfg = qmp->cfg; - void __iomem *serdes = qmp->serdes; + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; int i = cfg->num_resets; mutex_lock(&qmp->phy_mutex); @@ -1998,7 +1999,7 @@ static int qcom_qmp_phy_enable(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *tx = qphy->tx; void __iomem *rx = qphy->rx; void __iomem *pcs = qphy->pcs; @@ -2121,7 +2122,7 @@ static int qcom_qmp_phy_enable(struct phy *phy) if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); err_lane_rst: - qcom_qmp_phy_com_exit(qmp); + qcom_qmp_phy_com_exit(qphy); return ret; } @@ -2129,8 +2130,7 @@ static int qcom_qmp_phy_enable(struct phy *phy) static int qcom_qmp_phy_disable(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; clk_disable_unprepare(qphy->pipe_clk); @@ -2147,7 +2147,7 @@ static int qcom_qmp_phy_disable(struct phy *phy) if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); - qcom_qmp_phy_com_exit(qmp); + qcom_qmp_phy_com_exit(qphy); return 0; } @@ -2164,8 +2164,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy, static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) { - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; void __iomem *pcs_misc = qphy->pcs_misc; u32 intr_mask; @@ -2194,8 +2193,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) { - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; void __iomem *pcs_misc = qphy->pcs_misc; @@ -2215,7 +2213,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); @@ -2240,7 +2238,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; int ret = 0; dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); @@ -2272,10 +2270,10 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) return 0; } -static int qcom_qmp_phy_vreg_init(struct device *dev) +static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); - int num = qmp->cfg->num_vregs; + int num = cfg->num_vregs; int i; qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); @@ -2283,24 +2281,24 @@ static int qcom_qmp_phy_vreg_init(struct device *dev) return -ENOMEM; for (i = 0; i < num; i++) - qmp->vregs[i].supply = qmp->cfg->vreg_list[i]; + qmp->vregs[i].supply = cfg->vreg_list[i]; return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_reset_init(struct device *dev) +static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; - qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets, + qmp->resets = devm_kcalloc(dev, cfg->num_resets, sizeof(*qmp->resets), GFP_KERNEL); if (!qmp->resets) return -ENOMEM; - for (i = 0; i < qmp->cfg->num_resets; i++) { + for (i = 0; i < cfg->num_resets; i++) { struct reset_control *rst; - const char *name = qmp->cfg->reset_list[i]; + const char *name = cfg->reset_list[i]; rst = devm_reset_control_get(dev, name); if (IS_ERR(rst)) { @@ -2313,10 +2311,10 @@ static int qcom_qmp_phy_reset_init(struct device *dev) return 0; } -static int qcom_qmp_phy_clk_init(struct device *dev) +static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); - int num = qmp->cfg->num_clks; + int num = cfg->num_clks; int i; qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); @@ -2324,7 +2322,7 @@ static int qcom_qmp_phy_clk_init(struct device *dev) return -ENOMEM; for (i = 0; i < num; i++) - qmp->clks[i].id = qmp->cfg->clk_list[i]; + qmp->clks[i].id = cfg->clk_list[i]; return devm_clk_bulk_get(dev, num, qmp->clks); } @@ -2358,12 +2356,6 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) struct clk_init_data init = { }; int ret; - if ((qmp->cfg->type != PHY_TYPE_USB3) && - (qmp->cfg->type != PHY_TYPE_PCIE)) { - /* not all phys register pipe clocks, so return success */ - return 0; - } - ret = of_property_read_string(np, "clock-output-names", &init.name); if (ret) { dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); @@ -2414,7 +2406,8 @@ static const struct phy_ops qcom_qmp_pcie_ufs_ops = { }; static -int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) +int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; @@ -2427,6 +2420,8 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) if (!qphy) return -ENOMEM; + qphy->cfg = cfg; + qphy->serdes = serdes; /* * Get memory resources for each phy lane: * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. @@ -2451,7 +2446,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) * back to old legacy behavior of assuming they can be reached at an * offset from the first lane. */ - if (qmp->cfg->is_dual_lane_phy) { + if (cfg->is_dual_lane_phy) { qphy->tx2 = of_iomap(np, 3); qphy->rx2 = of_iomap(np, 4); if (!qphy->tx2 || !qphy->rx2) { @@ -2484,8 +2479,8 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) snprintf(prop_name, sizeof(prop_name), "pipe%d", id); qphy->pipe_clk = of_clk_get_by_name(np, prop_name); if (IS_ERR(qphy->pipe_clk)) { - if (qmp->cfg->type == PHY_TYPE_PCIE || - qmp->cfg->type == PHY_TYPE_USB3) { + if (cfg->type == PHY_TYPE_PCIE || + cfg->type == PHY_TYPE_USB3) { ret = PTR_ERR(qphy->pipe_clk); if (ret != -EPROBE_DEFER) dev_err(dev, @@ -2497,7 +2492,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) } /* Get lane reset, if any */ - if (qmp->cfg->has_lane_rst) { + if (cfg->has_lane_rst) { snprintf(prop_name, sizeof(prop_name), "lane%d", id); qphy->lane_rst = of_reset_control_get(np, prop_name); if (IS_ERR(qphy->lane_rst)) { @@ -2506,7 +2501,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) } } - if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE) + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ops = &qcom_qmp_pcie_ufs_ops; generic_phy = devm_phy_create(dev, np, ops); @@ -2586,6 +2581,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) struct device_node *child; struct phy_provider *phy_provider; void __iomem *base; + void __iomem *serdes; + const struct qmp_phy_cfg *cfg; int num, id; int ret; @@ -2597,8 +2594,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) dev_set_drvdata(dev, qmp); /* Get the specific init parameters of QMP phy */ - qmp->cfg = of_device_get_match_data(dev); - if (!qmp->cfg) + cfg = of_device_get_match_data(dev); + if (!cfg) return -EINVAL; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -2607,10 +2604,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) return PTR_ERR(base); /* per PHY serdes; usually located at base address */ - qmp->serdes = base; + serdes = base; /* per PHY dp_com; if PHY has dp_com control block */ - if (qmp->cfg->has_phy_dp_com_ctrl) { + if (cfg->has_phy_dp_com_ctrl) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp_com"); base = devm_ioremap_resource(dev, res); @@ -2622,15 +2619,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) mutex_init(&qmp->phy_mutex); - ret = qcom_qmp_phy_clk_init(dev); + ret = qcom_qmp_phy_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_reset_init(dev); + ret = qcom_qmp_phy_reset_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_vreg_init(dev); + ret = qcom_qmp_phy_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -2640,7 +2637,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ - if (num > qmp->cfg->nlanes) + if (num > cfg->nlanes) return -EINVAL; qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); @@ -2658,7 +2655,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ - ret = qcom_qmp_phy_create(dev, child, id); + ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -2669,11 +2666,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) * Register the pipe clock provided by phy. * See function description to see details of this pipe clock. */ - ret = phy_pipe_clk_register(qmp, child); - if (ret) { - dev_err(qmp->dev, - "failed to register pipe clock source\n"); - goto err_node_put; + if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; + } } id++; } From patchwork Thu Jun 11 09:19:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A82F60D for ; Thu, 11 Jun 2020 09:19:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F8712083E for ; Thu, 11 Jun 2020 09:19:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="C+z/AWXq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727050AbgFKJT2 (ORCPT ); Thu, 11 Jun 2020 05:19:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727037AbgFKJT0 (ORCPT ); Thu, 11 Jun 2020 05:19:26 -0400 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86CAEC08C5C2 for ; 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Thu, 11 Jun 2020 02:19:25 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id 1sm2367852pfx.210.2020.06.11.02.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 02:19:24 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul Subject: [PATCH/RFC 4/8] phy: qcom-qmp: Get dp_com I/O resource by index Date: Thu, 11 Jun 2020 02:19:15 -0700 Message-Id: <20200611091919.108018-5-swboyd@chromium.org> X-Mailer: git-send-email 2.27.0.278.ge193c7cf3a9-goog In-Reply-To: <20200611091919.108018-1-swboyd@chromium.org> References: <20200611091919.108018-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The dp_com resource is always at index 1 according to the dts files in the kernel. Get this resource by index so that we don't need to make future additions to the DT binding use 'reg-names'. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Signed-off-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index dace2f497c85..9dbc8c422263 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -2608,8 +2608,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) /* per PHY dp_com; if PHY has dp_com control block */ if (cfg->has_phy_dp_com_ctrl) { - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "dp_com"); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) return PTR_ERR(base); From patchwork Thu Jun 11 09:19:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599625 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A60E860D for ; Thu, 11 Jun 2020 09:19:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70FC52083E for ; Thu, 11 Jun 2020 09:19:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="a6epW1Jo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727113AbgFKJTv (ORCPT ); Thu, 11 Jun 2020 05:19:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727038AbgFKJT1 (ORCPT ); Thu, 11 Jun 2020 05:19:27 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBCBDC08C5C3 for ; Thu, 11 Jun 2020 02:19:26 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id 23so2411208pfw.10 for ; Thu, 11 Jun 2020 02:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tWKeN+mJMAUMgIzP4RxSAjXcwJ1YQgNBguLrfBOqU1k=; b=a6epW1JoC17Rg2FHvAm0rxrSyz/wIsDn7JHJaPakFSZPfe766FhrzPymkzoJaeeF7Y drESYPtBLGWBMu13H3dW3VJuVFJnghD+Dqw3pcs/xRPPjtqD8z3Tor3PiVb1X8sFCDoi KcLOM65CJ761Ya/dvjAdp7P1VK+N4FSnTSjyk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tWKeN+mJMAUMgIzP4RxSAjXcwJ1YQgNBguLrfBOqU1k=; b=BVZAitwW8zoxhDGEX0bWsy+jtBpzrMz1GQn/w3HzGoAemEdLH9o1kqjk1LY8cwjYDC CX8dzi1/KbKbJVLj35+7+5Re/DHL7wjGezKy4ViO74Tru5ko9AX55iuQfWF18Vn5d0BS IJ1OgnnJXtrXXvtIoyXhWXmAIdKC/u4NXCBoTEwjKvtM9ce425up4A/MLPg1PisrWOXe KoRbpKPub9cb7XETxgmCGXNq+nF0SOY6M4cKDk3YqnrK350WGvdVKmbvVBr3EpKe7W69 tjHQzf9dc7KVQjLsJlVPtTK0aR40X71Vcc/vM9yJM+y2c6Uwiv9B+SopKptJmCQ1zoYW Mx4w== X-Gm-Message-State: AOAM531gpnEWrgHfVmhEQTKINE8vNuF5kCOWjzQfaMOwwei9osZgaVON C5f05bfAy6gXJo35W7xVfvdgvg== X-Google-Smtp-Source: ABdhPJyz8ODfMHF0hlbtvDVQsCQQBaIjFM1t6naoiFVQSQjlAO6RX+yAicMJmuHqHKblgcsAskBi7Q== X-Received: by 2002:a63:4b4a:: with SMTP id k10mr5892022pgl.135.1591867166206; Thu, 11 Jun 2020 02:19:26 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id 1sm2367852pfx.210.2020.06.11.02.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 02:19:25 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul , Stephen Boyd Subject: [PATCH/RFC 5/8] phy: qcom-qmp: Add support for DP in USB3+DP combo phy Date: Thu, 11 Jun 2020 02:19:16 -0700 Message-Id: <20200611091919.108018-6-swboyd@chromium.org> X-Mailer: git-send-email 2.27.0.278.ge193c7cf3a9-goog In-Reply-To: <20200611091919.108018-1-swboyd@chromium.org> References: <20200611091919.108018-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Stephen Boyd Signed-off-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 924 +++++++++++++++++++++++++--- drivers/phy/qualcomm/phy-qcom-qmp.h | 80 +++ 2 files changed, 920 insertions(+), 84 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 9dbc8c422263..290233becd58 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -837,6 +837,130 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), }; +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +}; + static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), @@ -1336,6 +1460,11 @@ struct qmp_phy_cfg { bool no_pcs_sw_reset; }; +struct qmp_phy_combo_cfg { + const struct qmp_phy_cfg *usb_cfg; + const struct qmp_phy_cfg *dp_cfg; +}; + /** * struct qmp_phy - per-lane phy descriptor * @@ -1369,6 +1498,15 @@ struct qmp_phy { struct qcom_qmp *qmp; struct reset_control *lane_rst; enum phy_mode mode; + unsigned int dp_aux_cfg; + struct phy_configure_opts_dp dp_opts; + struct qmp_phy_dp_clks *dp_clks; +}; + +struct qmp_phy_dp_clks { + struct qmp_phy *qphy; + struct clk_hw dp_link_hw; + struct clk_hw dp_pixel_hw; }; /** @@ -1850,6 +1988,329 @@ static void qcom_qmp_phy_configure(void __iomem *base, } } +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + int ret; + + if (cfg->type == PHY_TYPE_DP) { + switch (dp_opts->link_rate) { + case 1620: + serdes_tbl = qmp_v3_dp_serdes_tbl_rbr; + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr); + break; + case 2700: + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr; + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr); + break; + case 5400: + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr2; + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2); + break; + case 8100: + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr3; + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3); + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + } else { + serdes_tbl = cfg->serdes_tbl; + serdes_tbl_num = cfg->serdes_tbl_num; + } + + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + + if (cfg->has_phy_com_ctrl) { + void __iomem *status; + unsigned int mask, val; + + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], + SERDES_START | PCS_START); + + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; + mask = cfg->mask_com_pcs_ready; + + ret = readl_poll_timeout(status, val, (val & mask), 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, + "phy common block init timed-out\n"); + return ret; + } + } + + return 0; +} + +static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy) +{ + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + /* Turn on BIAS current for PHY/PLL */ + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); + + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + /* Make sure that hardware is done with PSR power down */ + wmb(); + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | + DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + writel(QSERDES_V3_COM_BIAS_EN | + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); + + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0); + writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); + writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3); + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4); + writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5); + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6); + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7); + writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8); + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9); + qphy->dp_aux_cfg = 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); +} + +static const u8 vm_pre_emphasis[4][4] = { + { 0x00, 0x0b, 0x12, 0xff }, /* pe0, 0 db */ + { 0x00, 0x0a, 0x12, 0xff }, /* pe1, 3.5 db */ + { 0x00, 0x0c, 0xff, 0xff }, /* pe2, 6.0 db */ + { 0xff, 0xff, 0xff, 0xff } /* pe3, 9.5 db */ +}; + +/* voltage swing, 0.2v and 1.0v are not support */ +static const u8 vm_voltage_swing[4][4] = { + { 0x07, 0x0f, 0x14, 0xff }, /* sw0, 0.4v */ + { 0x11, 0x1d, 0x1f, 0xff }, /* sw1, 0.6 v */ + { 0x18, 0x1f, 0xff, 0xff }, /* sw1, 0.8 v */ + { 0xff, 0xff, 0xff, 0xff } /* sw1, 1.2 v, optional */ +}; + +static const u8 vm_pre_emphasis_hbr3_hbr2[4][4] = { + { 0x00, 0x0c, 0x15, 0x1a }, + { 0x02, 0x0e, 0x16, 0xff }, + { 0x02, 0x11, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 vm_voltage_swing_hbr3_hbr2[4][4] = { + { 0x02, 0x12, 0x16, 0x1a }, + { 0x09, 0x19, 0x1f, 0xff }, + { 0x10, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 vm_pre_emphasis_hbr_rbr[4][4] = { + { 0x00, 0x0c, 0x14, 0x19 }, + { 0x00, 0x0b, 0x12, 0xff }, + { 0x00, 0x0b, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 vm_voltage_swing_hbr_rbr[4][4] = { + { 0x08, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x19, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy) +{ + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + unsigned int v_level = 0, p_level = 0; + u32 bias_en, drvr_en; + u8 voltage_swing_cfg, pre_emphasis_cfg; + int i; + + for (i = 0; i < dp_opts->lanes; i++) { + v_level = max(v_level, dp_opts->voltage[i]); + p_level = max(p_level, dp_opts->pre[i]); + } + + if (dp_opts->lanes == 1) { + bias_en = 0x3e; + drvr_en = 0x13; + } else { + bias_en = 0x3f; + drvr_en = 0x10; + } + + /* TODO: Pick based on link rate */ + voltage_swing_cfg = vm_voltage_swing_hbr_rbr[v_level][p_level]; + pre_emphasis_cfg = vm_pre_emphasis_hbr_rbr[v_level][p_level]; + + /* TODO: Move check to config check */ + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) + return; + + /* Enable MUX to use Cursor values from these registers */ + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; + + writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); +} + +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + const struct phy_configure_opts_dp *dp_opts = &opts->dp; + struct qmp_phy *qphy = phy_get_drvdata(phy); + + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); + if (qphy->dp_opts.set_voltages) { + qcom_qmp_phy_configure_dp_tx(qphy); + qphy->dp_opts.set_voltages = 0; + } + + return 0; +} + +static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 val, phy_vco_div, status; + unsigned long pixel_freq; + + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; + + /* + if (lane_cnt == 4 || orientation == ORIENTATION_CC2) + val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; + if (lane_cnt == 4 || orientation == ORIENTATION_CC1) + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; + */ + /* + * TODO: Assume orientation is CC1 for now and two lanes, need to + * use type-c connector to understand orientation and lanes + */ + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; + + writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + /* + if (orientation == ORIENTATION_CC2) + writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); + else + */ + /* does this do anything? link_clock_sel_mux isn't set (bit 5) */ + writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); + + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div = 0x1; + pixel_freq = 1620000000UL / 2; + break; + case 2700: + phy_vco_div = 0x1; + pixel_freq = 2700000000UL / 2; + break; + case 5400: + phy_vco_div = 0x2; + pixel_freq = 5400000000UL / 4; + break; + case 8100: + phy_vco_div = 0x0; + pixel_freq = 8100000000UL / 6; + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); + + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); + + writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); + writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + + writel(0x20, qphy->serdes + QSERDES_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + udelay(2000); + writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000); +} + +/* + * We need to calibrate the aux setting here as many times + * as the caller tries + */ +static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; + u8 val; + + qphy->dp_aux_cfg++; + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); + val = cfg1_settings[qphy->dp_aux_cfg]; + + writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); + + return 0; +} + static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; @@ -1904,6 +2365,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + /* Default type-c orientation, i.e CC1 */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); @@ -1911,6 +2375,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); } if (cfg->has_phy_com_ctrl) @@ -1919,36 +2386,10 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) else qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); - /* Serdes configuration */ - qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl, - cfg->serdes_tbl_num); - - if (cfg->has_phy_com_ctrl) { - void __iomem *status; - unsigned int mask, val; - - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; - mask = cfg->mask_com_pcs_ready; - - ret = readl_poll_timeout(status, val, (val & mask), 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, - "phy common block init timed-out\n"); - goto err_com_init; - } - } - mutex_unlock(&qmp->phy_mutex); return 0; -err_com_init: - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); err_rst: while (++i < cfg->num_resets) reset_control_assert(qmp->resets[i]); @@ -1995,20 +2436,12 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_enable(struct phy *phy) +static int qcom_qmp_phy_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *tx = qphy->tx; - void __iomem *rx = qphy->rx; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - void __iomem *dp_com = qmp->dp_com; - void __iomem *status; - unsigned int mask, val, ready; int ret; - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); if (cfg->no_pcs_sw_reset) { @@ -2035,13 +2468,34 @@ static int qcom_qmp_phy_enable(struct phy *phy) ret = reset_control_assert(qmp->ufs_reset); if (ret) - goto err_lane_rst; + return ret; } ret = qcom_qmp_phy_com_init(qphy); if (ret) return ret; + if (cfg->type == PHY_TYPE_DP) + qcom_qmp_phy_dp_aux_init(qphy); + + return 0; +} + +static int qcom_qmp_phy_power_on(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_serdes_init(qphy); + if (cfg->has_lane_rst) { ret = reset_control_deassert(qphy->lane_rst); if (ret) { @@ -2064,12 +2518,22 @@ static int qcom_qmp_phy_enable(struct phy *phy) qcom_qmp_phy_configure(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num); + /* Configure special DP tx tunings */ + if (cfg->type == PHY_TYPE_DP) + qcom_qmp_phy_configure_dp_tx(qphy); + qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); if (cfg->is_dual_lane_phy) qcom_qmp_phy_configure(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); - qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + /* Configure link rate, swing, etc. */ + if (cfg->type == PHY_TYPE_DP) { + qcom_qmp_phy_configure_dp_phy(qphy); + } else { + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + } + ret = reset_control_deassert(qmp->ufs_reset); if (ret) goto err_lane_rst; @@ -2087,62 +2551,70 @@ static int qcom_qmp_phy_enable(struct phy *phy) if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - - if (cfg->has_phy_dp_com_ctrl) - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - - if (cfg->type == PHY_TYPE_UFS) { - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; - mask = PCS_READY; - ready = PCS_READY; - } else { - status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = PHYSTATUS; - ready = 0; - } + if (cfg->type != PHY_TYPE_DP) { + /* Pull PHY out of reset state */ + if (!cfg->no_pcs_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + if (cfg->type == PHY_TYPE_UFS) { + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; + mask = PCS_READY; + ready = PCS_READY; + } else { + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = PHYSTATUS; + ready = 0; + } - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_pcs_ready; + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_pcs_ready; + } } return 0; err_pcs_ready: - reset_control_assert(qmp->ufs_reset); clk_disable_unprepare(qphy->pipe_clk); err_clk_enable: if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); err_lane_rst: - qcom_qmp_phy_com_exit(qphy); - return ret; } -static int qcom_qmp_phy_disable(struct phy *phy) +static int qcom_qmp_phy_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; clk_disable_unprepare(qphy->pipe_clk); - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + if (cfg->type == PHY_TYPE_DP) { + /* Assert DP PHY power down */ + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + } else { + /* PHY reset */ + if (!cfg->no_pcs_sw_reset) + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Put PHY into POWER DOWN state: active low */ - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); + /* Put PHY into POWER DOWN state: active low */ + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); + } + + return 0; +} + +static int qcom_qmp_phy_exit(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); @@ -2152,6 +2624,31 @@ static int qcom_qmp_phy_disable(struct phy *phy) return 0; } +static int qcom_qmp_phy_enable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_init(phy); + if (ret) + return ret; + + ret = qcom_qmp_phy_power_on(phy); + if (ret) + qcom_qmp_phy_exit(phy); + + return ret; +} + +static int qcom_qmp_phy_disable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_power_off(phy); + if (ret) + return ret; + return qcom_qmp_phy_exit(phy); +} + static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { @@ -2217,7 +2714,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); - /* Supported only for USB3 PHY */ + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ if (cfg->type != PHY_TYPE_USB3) return 0; @@ -2243,7 +2740,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); - /* Supported only for USB3 PHY */ + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ if (cfg->type != PHY_TYPE_USB3) return 0; @@ -2327,7 +2824,7 @@ static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *c return devm_clk_bulk_get(dev, num, qmp->clks); } -static void phy_pipe_clk_release_provider(void *res) +static void phy_clk_release_provider(void *res) { of_clk_del_provider(res); } @@ -2384,9 +2881,202 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) * Roll a devm action because the clock provider is the child node, but * the child node is not actually a device. */ - ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np); + ret = devm_add_action(qmp->dev, phy_clk_release_provider, np); if (ret) - phy_pipe_clk_release_provider(np); + phy_clk_release_provider(np); + + return ret; +} + +/* + * Display Port PLL driver block diagram for branch clocks + * + * +------------------------------+ + * | DP_VCO_CLK | + * | | + * | +-------------------+ | + * | | (DP PLL/VCO) | | + * | +---------+---------+ | + * | v | + * | +----------+-----------+ | + * | | hsclk_divsel_clk_src | | + * | +----------+-----------+ | + * +------------------------------+ + * | + * +---------<---------v------------>----------+ + * | | + * +--------v----------------+ | + * | dp_phy_pll_link_clk | | + * | link_clk | | + * +--------+----------------+ | + * | | + * | | + * v v + * Input to DISPCC block | + * for link clk, crypto clk | + * and interface clock | + * | + * | + * +--------<------------+-----------------+---<---+ + * | | | + * +----v---------+ +--------v-----+ +--------v------+ + * | vco_divided | | vco_divided | | vco_divided | + * | _clk_src | | _clk_src | | _clk_src | + * | | | | | | + * |divsel_six | | divsel_two | | divsel_four | + * +-------+------+ +-----+--------+ +--------+------+ + * | | | + * v---->----------v-------------<------v + * | + * +----------+-----------------+ + * | dp_phy_pll_vco_div_clk | + * +---------+------------------+ + * | + * v + * Input to DISPCC block + * for DP pixel clock + * + */ +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 1620000000UL / 2: + case 2700000000UL / 2: + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ + return 0; + default: + return -EINVAL; + } +} + +static unsigned long +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + const struct qmp_phy_dp_clks *dp_clks; + const struct qmp_phy *qphy; + const struct phy_configure_opts_dp *dp_opts; + + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); + qphy = dp_clks->qphy; + dp_opts = &qphy->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + return 1620000000UL / 2; + case 2700: + return 2700000000UL / 2; + case 5400: + return 5400000000UL / 4; + case 8100: + return 8100000000UL / 6; + default: + return 0; + } +} + +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, +}; + +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 162000000: + case 270000000: + case 540000000: + case 810000000: + return 0; + default: + return -EINVAL; + } +} + +static unsigned long +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + const struct qmp_phy_dp_clks *dp_clks; + const struct qmp_phy *qphy; + const struct phy_configure_opts_dp *dp_opts; + + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); + qphy = dp_clks->qphy; + dp_opts = &qphy->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 5400: + case 8100: + return dp_opts->link_rate * 100000; + default: + return 0; + } +} + +static const struct clk_ops qcom_qmp_dp_link_clk_ops = { + .determine_rate = qcom_qmp_dp_link_clk_determine_rate, + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, +}; + +static struct clk_hw * +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) +{ + struct qmp_phy_dp_clks *dp_clks = data; + unsigned int idx = clkspec->args[0]; + + if (idx >= 2) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + if (idx == 0) + return &dp_clks->dp_link_hw; + + return &dp_clks->dp_pixel_hw; +} + +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, + struct device_node *np) +{ + struct clk_init_data init = { }; + struct qmp_phy_dp_clks *dp_clks; + int ret; + + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); + if (!dp_clks) + return -ENOMEM; + + dp_clks->qphy = qphy; + qphy->dp_clks = dp_clks; + + init.ops = &qcom_qmp_dp_link_clk_ops; + init.name = "qmp_dp_phy_pll_link_clk"; + dp_clks->dp_link_hw.init = &init; + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); + if (ret) + return ret; + + init.ops = &qcom_qmp_dp_pixel_clk_ops; + init.name = "qmp_dp_phy_pll_vco_div_clk"; + dp_clks->dp_pixel_hw.init = &init; + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + ret = devm_add_action(qmp->dev, phy_clk_release_provider, np); + if (ret) + phy_clk_release_provider(np); return ret; } @@ -2398,6 +3088,17 @@ static const struct phy_ops qcom_qmp_phy_gen_ops = { .owner = THIS_MODULE, }; +static const struct phy_ops qcom_qmp_phy_dp_ops = { + .init = qcom_qmp_phy_init, + .configure = qcom_qmp_dp_phy_configure, + .power_on = qcom_qmp_phy_power_on, + .calibrate = qcom_qmp_dp_phy_calibrate, + .power_off = qcom_qmp_phy_power_off, + .exit = qcom_qmp_phy_exit, + .set_mode = qcom_qmp_phy_set_mode, + .owner = THIS_MODULE, +}; + static const struct phy_ops qcom_qmp_pcie_ufs_ops = { .power_on = qcom_qmp_phy_enable, .power_off = qcom_qmp_phy_disable, @@ -2412,7 +3113,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - const struct phy_ops *ops = &qcom_qmp_phy_gen_ops; + const struct phy_ops *ops; char prop_name[MAX_PROP_NAME]; int ret; @@ -2503,6 +3204,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ops = &qcom_qmp_pcie_ufs_ops; + else if (cfg->type == PHY_TYPE_DP) + ops = &qcom_qmp_phy_dp_ops; + else + ops = &qcom_qmp_phy_gen_ops; generic_phy = devm_phy_create(dev, np, ops); if (IS_ERR(generic_phy)) { @@ -2568,6 +3273,10 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }; MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { + { } +}; + static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, qcom_qmp_phy_runtime_resume, NULL) @@ -2582,8 +3291,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) struct phy_provider *phy_provider; void __iomem *base; void __iomem *serdes; + void __iomem *usb_serdes; + void __iomem *dp_serdes; + const struct qmp_phy_combo_cfg *combo_cfg = NULL; const struct qmp_phy_cfg *cfg; - int num, id; + const struct qmp_phy_cfg *usb_cfg; + const struct qmp_phy_cfg *dp_cfg; + int num, id, expected_phys; int ret; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -2595,8 +3309,20 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) /* Get the specific init parameters of QMP phy */ cfg = of_device_get_match_data(dev); - if (!cfg) - return -EINVAL; + if (!cfg) { + const struct of_device_id *match; + + match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); + if (!match) + return -EINVAL; + + combo_cfg = match->data; + if (!combo_cfg) + return -EINVAL; + + usb_cfg = combo_cfg->usb_cfg; + cfg = usb_cfg; /* Setup clks and regulators */ + } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); @@ -2605,9 +3331,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) /* per PHY serdes; usually located at base address */ serdes = base; + usb_serdes = base; /* per PHY dp_com; if PHY has dp_com control block */ - if (cfg->has_phy_dp_com_ctrl) { + if (combo_cfg || cfg->has_phy_dp_com_ctrl) { res = platform_get_resource(pdev, IORESOURCE_MEM, 1); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) @@ -2616,6 +3343,20 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) qmp->dp_com = base; } + if (combo_cfg) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* Only two serdes for combo PHY */ + dp_serdes = base; + dp_cfg = combo_cfg->dp_cfg; + expected_phys = 2; + } else { + expected_phys = cfg->nlanes; + } + mutex_init(&qmp->phy_mutex); ret = qcom_qmp_phy_clk_init(dev, cfg); @@ -2636,14 +3377,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ - if (num > cfg->nlanes) + if (num > expected_phys) return -EINVAL; qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); if (!qmp->phys) return -ENOMEM; - id = 0; pm_runtime_set_active(dev); pm_runtime_enable(dev); /* @@ -2652,7 +3392,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) */ pm_runtime_forbid(dev); + id = 0; for_each_available_child_of_node(dev->of_node, child) { + if (of_node_name_eq(child, "dp-phy")) { + cfg = dp_cfg; + serdes = dp_serdes; + } else if (of_node_name_eq(child, "usb3-phy")) { + cfg = usb_cfg; + serdes = usb_serdes; + } + /* Create per-lane phy */ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); if (ret) { @@ -2672,6 +3421,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) "failed to register pipe clock source\n"); goto err_node_put; } + } else if (cfg->type == PHY_TYPE_DP) { + ret = phy_dp_clks_register(qmp, qmp->phys[id], child); + if (ret) { + dev_err(qmp->dev, + "failed to register DP clock source\n"); + goto err_node_put; + } } id++; } diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index dece0e67704b..37c8d9ca4337 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -135,6 +135,9 @@ #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c /* Only for QMP V3 PHY - QSERDES COM registers */ +#define QSERDES_V3_COM_ATB_SEL1 0x000 +#define QSERDES_V3_COM_ATB_SEL2 0x004 +#define QSERDES_V3_COM_FREQ_UPDATE 0x008 #define QSERDES_V3_COM_BG_TIMER 0x00c #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 @@ -144,6 +147,13 @@ #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 +# define QSERDES_V3_COM_BIAS_EN 0x0001 +# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 +# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 +# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 +# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 +# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 +# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 #define QSERDES_V3_COM_CLK_ENABLE1 0x038 #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 @@ -205,12 +215,36 @@ #define QSERDES_V3_COM_CMN_MODE 0x184 /* Only for QMP V3 PHY - TX registers */ +#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c +# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f +# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 + +#define QSERDES_V3_TX_TX_DRV_LVL 0x01c +# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f +# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 + +#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 +#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 + +#define QSERDES_V3_TX_TX_BAND 0x02c +#define QSERDES_V3_TX_SLEW_CNTL 0x030 +#define QSERDES_V3_TX_INTERFACE_SELECT 0x034 +#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c +#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 +#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 +#define QSERDES_V3_TX_TX_POL_INV 0x064 +#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 #define QSERDES_V3_TX_LANE_MODE_1 0x08c #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 +#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 +#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 +#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 /* Only for QMP V3 PHY - RX registers */ #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 @@ -313,6 +347,52 @@ #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 +/* Only for QMP V3 PHY - DP PHY registers */ +#define QSERDES_V3_DP_PHY_REVISION_ID0 0x000 +#define QSERDES_V3_DP_PHY_REVISION_ID1 0x004 +#define QSERDES_V3_DP_PHY_REVISION_ID2 0x008 +#define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c +#define QSERDES_V3_DP_PHY_CFG 0x010 +#define QSERDES_V3_DP_PHY_PD_CTL 0x018 +# define DP_PHY_PD_CTL_PWRDN 0x001 +# define DP_PHY_PD_CTL_PSR_PWRDN 0x002 +# define DP_PHY_PD_CTL_AUX_PWRDN 0x004 +# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 +# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 +# define DP_PHY_PD_CTL_PLL_PWRDN 0x020 +# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 +#define QSERDES_V3_DP_PHY_MODE 0x01c +#define QSERDES_V3_DP_PHY_AUX_CFG0 0x020 +#define QSERDES_V3_DP_PHY_AUX_CFG1 0x024 +#define QSERDES_V3_DP_PHY_AUX_CFG2 0x028 +#define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c +#define QSERDES_V3_DP_PHY_AUX_CFG4 0x030 +#define QSERDES_V3_DP_PHY_AUX_CFG5 0x034 +#define QSERDES_V3_DP_PHY_AUX_CFG6 0x038 +#define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c +#define QSERDES_V3_DP_PHY_AUX_CFG8 0x040 +#define QSERDES_V3_DP_PHY_AUX_CFG9 0x044 + +#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 +# define PHY_AUX_STOP_ERR_MASK 0x01 +# define PHY_AUX_DEC_ERR_MASK 0x02 +# define PHY_AUX_SYNC_ERR_MASK 0x04 +# define PHY_AUX_ALIGN_ERR_MASK 0x08 +# define PHY_AUX_REQ_ERR_MASK 0x10 + +#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c +#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 + +#define QSERDES_V3_DP_PHY_VCO_DIV 0x064 +#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c +#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 + +#define QSERDES_V3_DP_PHY_SPARE0 0x0ac +#define DP_PHY_SPARE0_MASK 0x0f +#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) + +#define QSERDES_V3_DP_PHY_STATUS 0x0c0 + /* Only for QMP V4 PHY - QSERDES COM registers */ #define QSERDES_V4_COM_PLL_IVCO 0x058 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 From patchwork Thu Jun 11 09:19:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26ED41392 for ; Thu, 11 Jun 2020 09:19:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01D5320853 for ; Thu, 11 Jun 2020 09:19:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit 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X-Received: by 2002:a05:6a00:2ae:: with SMTP id q14mr6473844pfs.255.1591867167060; Thu, 11 Jun 2020 02:19:27 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id 1sm2367852pfx.210.2020.06.11.02.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 02:19:26 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul Subject: [PATCH/RFC 6/8] phy: qcom-qmp: Add support for sc7180 DP phy Date: Thu, 11 Jun 2020 02:19:17 -0700 Message-Id: <20200611091919.108018-7-swboyd@chromium.org> X-Mailer: git-send-email 2.27.0.278.ge193c7cf3a9-goog In-Reply-To: <20200611091919.108018-1-swboyd@chromium.org> References: <20200611091919.108018-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the necessary compatible strings and phy data for the sc7180 USB3+DP combo phy. Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Signed-off-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 290233becd58..f6841716d21a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -961,6 +961,24 @@ static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), }; +static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), +}; + static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), @@ -1842,6 +1860,28 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .is_dual_lane_phy = true, }; +static const struct qmp_phy_cfg sc7180_dpphy_cfg = { + .type = PHY_TYPE_DP, + .nlanes = 1, + + .tx_tbl = qmp_v3_dp_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = sc7180_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { + .usb_cfg = &sc7180_usb3phy_cfg, + .dp_cfg = &sc7180_dpphy_cfg, +}; + static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -3247,6 +3287,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sc7180-qmp-usb3-phy", .data = &sc7180_usb3phy_cfg, + }, { + .compatible = "qcom,sc7180-qmp-usb3-dp-phy", + /* It's a combo phy */ }, { .compatible = "qcom,sdm845-qhp-pcie-phy", .data = &sdm845_qhp_pciephy_cfg, @@ -3274,6 +3317,10 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { + { + .compatible = "qcom,sc7180-qmp-usb3-dp-phy", + .data = &sc7180_usb3dpphy_cfg, + }, { } }; From patchwork Thu Jun 11 09:19:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599621 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 653E41392 for ; Thu, 11 Jun 2020 09:19:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47BC820823 for ; Thu, 11 Jun 2020 09:19:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="GYPtcV9+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727089AbgFKJTn (ORCPT ); Thu, 11 Jun 2020 05:19:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727055AbgFKJT2 (ORCPT ); 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b=UpKAn3ekoQ6mC4Bj4l5XsBPvoEgInQXwiHZOl0FRlY6H6b9qVgcFI682flAuLeaCcZ TATF0ubvbVLqm9lTP4TV3F5IUZkkCfARpoCSXZrn4ojBwr2A5RsfXHISs8HwB6z2Xhy3 bilkKrTU7USoanS5R8DtkBN5N9s9ElRnJIAarw2p5mMTLGpzdt5FRYbNeOuo9Nh4xFR1 FDwzJb9fOPXpPPgNDtaZbp4yTUg9lvpoUNsP+vL1UnwN0M2F6zC7GzIpMgv8X/5vbeGR 1/scu78Jz4b9EIs36a1LHWhCcJzrmSl6eAzd91L0m6s0ysUF9E4SqWWqwoAqH92/yky+ Qi+w== X-Gm-Message-State: AOAM5301K3vm1/2ymrRZGXDvIfTtA4+S9KExc8gryROQZVunDR7Monzg w/G+kU1cJpWpUmoohVgQYJ8JiQ== X-Google-Smtp-Source: ABdhPJxyyP8c8/ur/yOtbyoJb7vcLI2mgwS4h7Kvldt0IWVC5/shygbsLSvpCn+82RfazItS7w8Z7w== X-Received: by 2002:a63:497:: with SMTP id 145mr5961513pge.356.1591867167968; Thu, 11 Jun 2020 02:19:27 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id 1sm2367852pfx.210.2020.06.11.02.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 02:19:27 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul , Stephen Boyd Subject: [PATCH/RFC 7/8] clk: qcom: dispcc: Update DP clk ops for phy design Date: Thu, 11 Jun 2020 02:19:18 -0700 Message-Id: <20200611091919.108018-8-swboyd@chromium.org> X-Mailer: git-send-email 2.27.0.278.ge193c7cf3a9-goog In-Reply-To: <20200611091919.108018-1-swboyd@chromium.org> References: <20200611091919.108018-1-swboyd@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk. This function should return the rate that can be achieved by the pixel clk in 'struct clk_rate_request::rate' and match the logic similar to what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead the code merely bubbles the rate request up to the parent of the pixel clk and doesn't try to do a rational approximation of the rate that would be achieved by picking some m/n value for the RCG. Let's change this logic so that we can assume the parent clk frequency is fixed (it is because it's the VCO of the DP PLL that is configured based on the link rate) and so that we can calculate what the m/n value will be and adjust the req->rate appropriately. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Stephen Boyd Signed-off-by: Stephen Boyd --- drivers/clk/qcom/clk-rcg2.c | 19 +++++++++++++------ drivers/clk/qcom/dispcc-sc7180.c | 3 --- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 357159fe85b5..59a5a0f261f3 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1182,14 +1182,21 @@ static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw, static int clk_rcg2_dp_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - struct clk_rate_request parent_req = *req; - int ret; + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + unsigned long num, den; + u64 tmp; - ret = __clk_determine_rate(clk_hw_get_parent(hw), &parent_req); - if (ret) - return ret; + /* Parent rate is a fixed phy link rate */ + rational_best_approximation(req->best_parent_rate, req->rate, + GENMASK(rcg->mnd_width - 1, 0), + GENMASK(rcg->mnd_width - 1, 0), &den, &num); + + if (!num || !den) + return -EINVAL; - req->best_parent_rate = parent_req.rate; + tmp = req->best_parent_rate * num; + do_div(tmp, den); + req->rate = tmp; return 0; } diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 0a5d395bce93..f487515701e3 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -202,7 +202,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, }; @@ -216,7 +215,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, }; @@ -230,7 +228,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, }; From patchwork Thu Jun 11 09:19:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 11599617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A5B060D for ; Thu, 11 Jun 2020 09:19:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F0A6A2078D for ; Thu, 11 Jun 2020 09:19:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="cMlgAgmo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727070AbgFKJTd (ORCPT ); Thu, 11 Jun 2020 05:19:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727059AbgFKJTa (ORCPT ); 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This also removes the PLL code and adds proper includes so things build. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Signed-off-by: Stephen Boyd --- drivers/gpu/drm/msm/Kconfig | 13 - drivers/gpu/drm/msm/Makefile | 4 - drivers/gpu/drm/msm/dp/dp_aux.c | 27 +- drivers/gpu/drm/msm/dp/dp_aux.h | 6 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 247 +-------- drivers/gpu/drm/msm/dp/dp_catalog.h | 11 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 58 +- drivers/gpu/drm/msm/dp/dp_display.c | 50 +- drivers/gpu/drm/msm/dp/dp_display.h | 3 - drivers/gpu/drm/msm/dp/dp_link.c | 2 + drivers/gpu/drm/msm/dp/dp_panel.c | 1 + drivers/gpu/drm/msm/dp/dp_parser.c | 123 +--- drivers/gpu/drm/msm/dp/dp_parser.h | 81 +-- drivers/gpu/drm/msm/dp/dp_power.c | 78 +-- drivers/gpu/drm/msm/dp/dp_power.h | 21 - drivers/gpu/drm/msm/dp/pll/dp_pll.c | 127 ----- drivers/gpu/drm/msm/dp/pll/dp_pll.h | 57 -- drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c | 401 -------------- drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h | 86 --- drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c | 524 ------------------ 20 files changed, 91 insertions(+), 1829 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.c delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.h delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 43544c18b4ee..ea3c4d094d09 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -65,19 +65,6 @@ config DRM_MSM_DP display support is enabled through this config option. It can be primary or secondary display on device. -config DRM_MSM_DP_PLL - bool "Enable DP PLL driver in MSM DRM" - depends on DRM_MSM_DP && COMMON_CLK - help - Choose this option to enable DP PLL driver which provides DP - source clocks under common clock framework. - -config DRM_MSM_DP_10NM_PLL - bool "Enable DP 10nm PLL driver in MSM DRM (used by SDM845)" - depends on DRM_MSM_DP_PLL - help - Choose this option if DP PLL on SDM845 is used on the platform. - config DRM_MSM_DSI bool "Enable DSI support in MSM DRM driver" depends on DRM_MSM diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index a6f68fb013ab..3e078d574aeb 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -139,8 +139,4 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o endif -msm-$(CONFIG_DRM_MSM_DP_PLL)+= dp/pll/dp_pll.o -msm-$(CONFIG_DRM_MSM_DP_10NM_PLL)+= dp/pll/dp_pll_10nm.o \ - dp/pll/dp_pll_10nm_util.o - obj-$(CONFIG_DRM_MSM) += msm.o diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index 73e0388a6b73..f0278d192c09 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -4,6 +4,7 @@ */ #include +#include #include "dp_reg.h" #include "dp_aux.h" @@ -356,8 +357,7 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *drm_aux, if (aux->native) { aux->retry_cnt++; if (!(aux->retry_cnt % retry_count)) - dp_catalog_aux_update_cfg(aux->catalog, - aux->dp_aux.cfg, PHY_AUX_CFG1); + dp_catalog_aux_update_cfg(aux->catalog); dp_catalog_aux_reset(aux->catalog); } goto unlock_exit; @@ -385,14 +385,6 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *drm_aux, return ret; } -static void dp_aux_reset_phy_config_indices(struct dp_aux_cfg *aux_cfg) -{ - int i; - - for (i = 0; i < PHY_AUX_CFG_MAX; i++) - aux_cfg[i].current_index = 0; -} - void dp_aux_isr(struct dp_aux *dp_aux) { struct dp_aux_private *aux; @@ -421,24 +413,21 @@ void dp_aux_reconfig(struct dp_aux *dp_aux) aux = container_of(dp_aux, struct dp_aux_private, dp_aux); - dp_catalog_aux_update_cfg(aux->catalog, - dp_aux->cfg, PHY_AUX_CFG1); + dp_catalog_aux_update_cfg(aux->catalog); dp_catalog_aux_reset(aux->catalog); } -void dp_aux_init(struct dp_aux *dp_aux, struct dp_aux_cfg *aux_cfg) +void dp_aux_init(struct dp_aux *dp_aux) { struct dp_aux_private *aux; - if (!dp_aux || !aux_cfg) { + if (!dp_aux) { DRM_ERROR("invalid input\n"); return; } aux = container_of(dp_aux, struct dp_aux_private, dp_aux); - dp_aux_reset_phy_config_indices(aux_cfg); - dp_catalog_aux_setup(aux->catalog, aux_cfg); dp_catalog_aux_reset(aux->catalog); dp_catalog_aux_enable(aux->catalog, true); aux->retry_cnt = 0; @@ -487,13 +476,12 @@ void dp_aux_unregister(struct dp_aux *dp_aux) drm_dp_aux_unregister(&aux->drm_aux); } -struct dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, - struct dp_aux_cfg *aux_cfg) +struct dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog) { struct dp_aux_private *aux; struct dp_aux *dp_aux; - if (!catalog || !aux_cfg) { + if (!catalog) { DRM_ERROR("invalid input\n"); return ERR_PTR(-ENODEV); } @@ -509,7 +497,6 @@ struct dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, aux->dev = dev; aux->catalog = catalog; - aux->dp_aux.cfg = aux_cfg; dp_aux = &aux->dp_aux; aux->retry_cnt = 0; diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h index 18f560b1d29a..3b93c8a3252b 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -18,18 +18,16 @@ struct dp_aux { struct drm_dp_aux *drm_aux; - struct dp_aux_cfg *cfg; }; int dp_aux_register(struct dp_aux *aux); void dp_aux_unregister(struct dp_aux *aux); void dp_aux_isr(struct dp_aux *aux); -void dp_aux_init(struct dp_aux *aux, struct dp_aux_cfg *aux_cfg); +void dp_aux_init(struct dp_aux *aux); void dp_aux_deinit(struct dp_aux *aux); void dp_aux_reconfig(struct dp_aux *aux); -struct dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, - struct dp_aux_cfg *aux_cfg); +struct dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog); void dp_aux_put(struct dp_aux *aux); #endif /*__DP_AUX_H_*/ diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 7987eb3947a1..f7058d1c587d 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -8,7 +8,10 @@ #include #include #include +#include +#include #include +#include #include "dp_catalog.h" #include "dp_reg.h" @@ -121,76 +124,6 @@ static inline void dp_write_ahb(struct dp_catalog_private *catalog, writel(data, catalog->io->dp_ahb.base + offset); } -static inline void dp_write_phy(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - /* - * To make sure phy reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, catalog->io->phy_io.base + offset); -} - -static inline u32 dp_read_phy(struct dp_catalog_private *catalog, - u32 offset) -{ - /* - * To make sure phy reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - return readl_relaxed(catalog->io->phy_io.base + offset); -} - -static inline void dp_write_pll(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - writel_relaxed(data, catalog->io->dp_pll_io.base + offset); -} - -static inline void dp_write_ln_tx0(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - writel_relaxed(data, catalog->io->ln_tx0_io.base + offset); -} - -static inline void dp_write_ln_tx1(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - writel_relaxed(data, catalog->io->ln_tx1_io.base + offset); -} - -static inline u32 dp_read_ln_tx0(struct dp_catalog_private *catalog, - u32 offset) -{ - return readl_relaxed(catalog->io->ln_tx0_io.base + offset); -} - -static inline u32 dp_read_ln_tx1(struct dp_catalog_private *catalog, - u32 offset) -{ - return readl_relaxed(catalog->io->ln_tx1_io.base + offset); -} - -static inline void dp_write_usb_cm(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - /* - * To make sure usb reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, catalog->io->usb3_dp_com.base + offset); -} - -static inline u32 dp_read_usb_cm(struct dp_catalog_private *catalog, - u32 offset) -{ - /* - * To make sure usb reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - return readl_relaxed(catalog->io->usb3_dp_com.base + offset); -} - static inline void dp_write_p0(struct dp_catalog_private *catalog, u32 offset, u32 data) { @@ -304,27 +237,14 @@ void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable) dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); } -void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog, - struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type) +void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - u32 new_index = 0, current_index = 0; + struct dp_io *dp_io = catalog->io; + struct phy *phy = dp_io->phy; - if (type >= PHY_AUX_CFG_MAX) { - DRM_ERROR("invalid input\n"); - return; - } - - current_index = cfg[type].current_index; - new_index = (current_index + 1) % cfg[type].cfg_cnt; - DRM_DEBUG_DP("Updating %s from 0x%08x to 0x%08x\n", - dp_phy_aux_config_type_to_string(type), - cfg[type].lut[current_index], cfg[type].lut[new_index]); - - dp_write_phy(catalog, cfg[type].offset, - cfg[type].lut[new_index]); - cfg[type].current_index = new_index; + phy_calibrate(phy); } void dump_regs(void * __iomem *base, int len) @@ -360,65 +280,6 @@ void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) pr_info("P0CLK regs\n"); dump_regs(catalog->io->dp_p0.base, catalog->io->dp_p0.len); - - pr_info("USB3 DP COM regs\n"); - dump_regs(catalog->io->usb3_dp_com.base, catalog->io->usb3_dp_com.len); - - pr_info("LN TX0 regs\n"); - dump_regs(catalog->io->ln_tx0_io.base, catalog->io->ln_tx0_io.len); - - pr_info("LN TX1 regs\n"); - dump_regs(catalog->io->ln_tx1_io.base, catalog->io->ln_tx1_io.len); - - pr_info("DP PHY regs\n"); - dump_regs(catalog->io->phy_io.base, catalog->io->phy_io.len); -} - -void dp_catalog_aux_setup(struct dp_catalog *dp_catalog, - struct dp_aux_cfg *cfg) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - int i = 0; - - dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN | - DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | - DP_PHY_PD_CTL_DP_CLAMP_EN); - - /* Turn on BIAS current for PHY/PLL */ - dp_write_pll(catalog, - QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN | - QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_L_EN | - QSERDES_COM_EN_SYSCLK_TX_SEL); - - dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PSR_PWRDN); - - /* Make sure that hardware is done with PSR power down */ - wmb(); - dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN | - DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN - | DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN - | DP_PHY_PD_CTL_DP_CLAMP_EN); - - dp_write_pll(catalog, - QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN | - QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_R_EN | - QSERDES_COM_CLKBUF_L_EN | QSERDES_COM_EN_SYSCLK_TX_SEL | - QSERDES_COM_CLKBUF_RX_DRIVE_L); - - /* DP AUX CFG register programming */ - for (i = 0; i < PHY_AUX_CFG_MAX; i++) { - DRM_DEBUG_DP("%s: offset=0x%08x, value=0x%08x\n", - dp_phy_aux_config_type_to_string(i), - cfg[i].offset, cfg[i].lut[cfg[i].current_index]); - dp_write_phy(catalog, cfg[i].offset, - cfg[i].lut[cfg[i].current_index]); - } - - dp_write_phy(catalog, REG_DP_PHY_AUX_INTERRUPT_MASK, - PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | - PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | - PHY_AUX_REQ_ERR_MASK); } int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) @@ -537,7 +398,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, bool fixed_nvid) { u32 pixel_m, pixel_n; - u32 mvid, nvid, div, pixel_div = 0, dispcc_input_rate; + u32 mvid, nvid, pixel_div = 0, dispcc_input_rate; u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE; u32 const link_rate_hbr2 = 540000; u32 const link_rate_hbr3 = 810000; @@ -546,14 +407,11 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - div = dp_read_phy(catalog, REG_DP_PHY_VCO_DIV); - div &= 0x03; - - if (div == 0) + if (rate == link_rate_hbr3) pixel_div = 6; - else if (div == 1) + else if (rate == 1620000 || rate == 270000) pixel_div = 2; - else if (div == 2) + else if (rate == link_rate_hbr2) pixel_div = 4; else DRM_ERROR("Invalid pixel mux divider\n"); @@ -619,36 +477,6 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, return 0; } -void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - u32 typec_ctrl; - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL, - USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET_MUX | - USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET_MUX); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_PHY_MODE_CTRL, - USB3_DP_COM_PHY_MODE_DP); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET, - USB3_DP_COM_SW_RESET_SET); - - /* Default configuration i.e CC1 */ - typec_ctrl = USB3_DP_COM_TYPEC_CTRL_PORTSEL_MUX; - if (flip) - typec_ctrl |= USB3_DP_COM_TYPEC_CTRL_PORTSEL; - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_TYPEC_CTRL, typec_ctrl); - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_SWI_CTRL, 0x00); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET, 0x00); - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_POWER_DOWN_CTRL, - USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL, 0x00); - -} - void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog) { u32 sw_reset; @@ -776,59 +604,26 @@ void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog) struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - dp_write_ahb(catalog, REG_DP_PHY_CTRL, - DP_PHY_CTRL_SW_RESET_PLL | DP_PHY_CTRL_SW_RESET); + dp_write_ahb(catalog, REG_DP_PHY_CTRL, DP_PHY_CTRL_SW_RESET_PLL); usleep_range(1000, 1100); /* h/w recommended delay */ dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); } -void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, - bool flipped, u8 ln_cnt) -{ - u32 info; - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - u8 orientation = BIT(!!flipped); - - info = ln_cnt & DP_PHY_SPARE0_MASK; - info |= (orientation & DP_PHY_SPARE0_MASK) - << DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT; - DRM_DEBUG_DP("Shared Info = 0x%x\n", info); - - dp_write_phy(catalog, REG_DP_PHY_SPARE0, info); -} - int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level, u8 p_level) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - u8 voltage_swing_cfg, pre_emphasis_cfg; - - DRM_DEBUG_DP("hw: v=%d p=%d\n", v_level, p_level); - - voltage_swing_cfg = vm_voltage_swing_hbr_rbr[v_level][p_level]; - pre_emphasis_cfg = vm_pre_emphasis_hbr_rbr[v_level][p_level]; - - if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) { - DRM_ERROR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n", - v_level, voltage_swing_cfg, p_level, pre_emphasis_cfg); - return -EINVAL; - } + struct dp_io *dp_io = catalog->io; + struct phy *phy = dp_io->phy; + struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; - /* Enable MUX to use Cursor values from these registers */ - voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; - pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; - - /* Configure host and panel only if both values are allowed */ - dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg); - dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg); - dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, - pre_emphasis_cfg); - dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, - pre_emphasis_cfg); - DRM_DEBUG_DP("hw: vx_value=0x%x px_value=0x%x\n", - voltage_swing_cfg, pre_emphasis_cfg); + /* TODO: Update for all lanes instead of just first one */ + opts_dp->voltage[0] = v_level; + opts_dp->pre[0] = p_level; + opts_dp->set_voltages = 1; + phy_configure(phy, &dp_io->phy_opts); + opts_dp->set_voltages = 0; return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 23d1cec7a517..61361da6b4c7 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -6,6 +6,8 @@ #ifndef _DP_CATALOG_H_ #define _DP_CATALOG_H_ +#include + #include "dp_parser.h" /* interrupts */ @@ -40,11 +42,8 @@ int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog); int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read); void dp_catalog_aux_reset(struct dp_catalog *dp_catalog); void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable); -void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog, - struct dp_aux_cfg *cfg, - enum dp_phy_aux_config_type type); -void dp_catalog_aux_setup(struct dp_catalog *dp_catalog, - struct dp_aux_cfg *aux_cfg); +void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog); +void dp_catalog_aux_setup(struct dp_catalog *dp_catalog); int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); /* DP Controller APIs */ @@ -65,8 +64,6 @@ void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog); u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); -void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, bool flipped, - u8 lane_cnt); int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level, u8 p_level); int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index fa15d65c8d7a..15cd2b2e3364 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -8,8 +8,11 @@ #include #include #include +#include +#include #include #include +#include #include "dp_reg.h" #include "dp_ctrl.h" @@ -1283,7 +1286,7 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, bool train) } static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, - char *name, u32 rate) + char *name, unsigned long rate) { u32 num = ctrl->parser->mp[DP_CTRL_PM].num_clk; struct dss_clk *cfg = ctrl->parser->mp[DP_CTRL_PM].clk_config; @@ -1293,38 +1296,45 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, cfg++; } - DRM_DEBUG_DP("setting rate=%d on clk=%s\n", rate, name); + DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name); if (num) cfg->rate = rate; else - DRM_ERROR("%s clock doesn't exit to set rate %d\n", + DRM_ERROR("%s clock doesn't exit to set rate %lu\n", name, rate); } static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) { - int ret = 0; - - dp_power_set_link_clk_parent(ctrl->power); - dp_power_set_pixel_clk_parent(ctrl->power); + struct dp_io *dp_io = &ctrl->parser->io; + struct phy *phy = dp_io->phy; + struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; + int ret; + opts_dp->lanes = ctrl->link->link_params.num_lanes; + opts_dp->link_rate = ctrl->link->link_params.rate / 100; dp_ctrl_set_clock_rate(ctrl, "ctrl_link_clk", - ctrl->link->link_params.rate); + ctrl->link->link_params.rate * 1000); dp_ctrl_set_clock_rate(ctrl, "ctrl_pixel_clk", - ctrl->dp_ctrl.pixel_rate); + ctrl->dp_ctrl.pixel_rate * 1000); + + phy_configure(phy, &dp_io->phy_opts); + phy_power_on(phy); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); if (ret) DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); - return ret; + return 0; } int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) { struct dp_ctrl_private *ctrl; + struct dp_io *dp_io; + struct phy *phy; if (!dp_ctrl) { DRM_ERROR("Invalid input data\n"); @@ -1332,10 +1342,12 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) } ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dp_io = &ctrl->parser->io; + phy = dp_io->phy; ctrl->dp_ctrl.orientation = flip; - dp_catalog_ctrl_usb_reset(ctrl->catalog, flip); + phy_init(phy); dp_catalog_ctrl_phy_reset(ctrl->catalog); dp_catalog_ctrl_enable_irq(ctrl->catalog, true); @@ -1374,7 +1386,7 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) * whenever connected to a VGA dongle downstream. */ if (drm_dp_is_branch(dpcd)) - return (drm_dp_has_quirk(&ctrl->panel->desc, + return (drm_dp_has_quirk(&ctrl->panel->desc, 0, DP_DPCD_QUIRK_CONSTANT_N)); return false; @@ -1383,10 +1395,13 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) { int ret = 0; + struct dp_io *dp_io = &ctrl->parser->io; + struct phy *phy = dp_io->phy; + struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); - dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog, - ctrl->dp_ctrl.orientation, ctrl->link->link_params.num_lanes); + opts_dp->lanes = ctrl->link->link_params.num_lanes; + phy_configure(phy, &dp_io->phy_opts); /* * Disable and re-enable the mainlink clock since the * link clock might have been adjusted as part of the @@ -1397,6 +1412,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); return ret; } + phy_power_off(phy); /* hw recommended delay before re-enabling clocks */ msleep(20); @@ -1584,10 +1600,6 @@ int dp_ctrl_on(struct dp_ctrl *dp_ctrl) ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); - dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog, - ctrl->dp_ctrl.orientation, - ctrl->link->link_params.num_lanes); - rc = dp_ctrl_enable_mainlink_clocks(ctrl); if (rc) return rc; @@ -1616,20 +1628,20 @@ int dp_ctrl_on(struct dp_ctrl *dp_ctrl) int dp_ctrl_off(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; + struct dp_io *dp_io; + struct phy *phy; int ret = 0; if (!dp_ctrl) return -EINVAL; ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dp_io = &ctrl->parser->io; + phy = dp_io->phy; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); dp_catalog_ctrl_reset(ctrl->catalog); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); - if (ret) { - DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); - return ret; - } + phy_power_off(phy); DRM_DEBUG_DP("DP off done\n"); return ret; diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 0cc94ca88f20..4e9b2d1de6f3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -63,46 +63,6 @@ static const struct of_device_id dp_dt_match[] = { {} }; -static int dp_get_pll(struct dp_display_private *dp_priv) -{ - struct platform_device *pdev = NULL; - struct platform_device *pll_pdev; - struct device_node *pll_node; - struct dp_parser *dp_parser = NULL; - - pdev = dp_priv->pdev; - dp_parser = dp_priv->parser; - - if (!dp_parser) { - DRM_DEV_ERROR(&pdev->dev, "%s: Parser not initialized\n", - __func__); - return -EINVAL; - } - - pll_node = of_parse_phandle(pdev->dev.of_node, "pll-node", 0); - if (!pll_node) { - DRM_DEV_ERROR(&pdev->dev, "%s: cannot find pll device\n", - __func__); - return -ENXIO; - } - - pll_pdev = of_find_device_by_node(pll_node); - if (pll_pdev) - dp_parser->pll = platform_get_drvdata(pll_pdev); - - of_node_put(pll_node); - - if (!pll_pdev || !dp_parser->pll) { - DRM_DEV_ERROR(&pdev->dev, "%s: pll driver is not ready\n", - __func__); - return -EPROBE_DEFER; - } - - dp_parser->pll_dev = get_device(&pll_pdev->dev); - - return 0; -} - static irqreturn_t dp_display_irq(int irq, void *dev_id) { struct dp_display_private *dp = dev_id; @@ -200,10 +160,6 @@ static int dp_display_bind(struct device *dev, struct device *master, goto end; } - rc = dp_get_pll(dp); - if (rc) - goto end; - rc = dp_aux_register(dp->aux); if (rc) { DRM_ERROR("DRM DP AUX register failed\n"); @@ -357,7 +313,7 @@ static void dp_display_host_init(struct dp_display_private *dp) dp_power_init(dp->power, flip); dp_ctrl_host_init(dp->ctrl, flip); - dp_aux_init(dp->aux, dp->parser->aux_cfg); + dp_aux_init(dp->aux); dp->core_initialized = true; } @@ -553,7 +509,7 @@ static int dp_init_sub_modules(struct dp_display_private *dp) goto error; } - dp->aux = dp_aux_get(dev, dp->catalog, dp->parser->aux_cfg); + dp->aux = dp_aux_get(dev, dp->catalog); if (IS_ERR(dp->aux)) { rc = PTR_ERR(dp->aux); DRM_ERROR("failed to initialize aux, rc = %d\n", rc); @@ -867,7 +823,6 @@ int __init msm_dp_register(void) { int ret; - msm_dp_pll_driver_register(); ret = platform_driver_register(&dp_display_driver); if (ret) DRM_ERROR("Dp display driver register failed"); @@ -877,7 +832,6 @@ int __init msm_dp_register(void) void __exit msm_dp_unregister(void) { - msm_dp_pll_driver_unregister(); platform_driver_unregister(&dp_display_driver); } diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 4c53ed55d1cc..dad8610685a6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -25,7 +25,4 @@ int dp_display_request_irq(struct msm_dp *dp_display); bool dp_display_check_video_test(struct msm_dp *dp_display); int dp_display_get_test_bpp(struct msm_dp *dp_display); -void __init msm_dp_pll_driver_register(void); -void __exit msm_dp_pll_driver_unregister(void); - #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c index b7869dbb1ed0..0a0e62732b74 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -5,6 +5,8 @@ #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ +#include + #include "dp_link.h" #include "dp_panel.h" diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index a129924aff27..327ae38af5d7 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -7,6 +7,7 @@ #include #include +#include #define DP_MAX_DS_PORT_COUNT 1 diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 08c1abeaf1d3..8763a43318bd 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -4,6 +4,9 @@ */ #include +#include + +#include #include "dp_parser.h" @@ -55,11 +58,6 @@ static void dp_parser_unmap_io_resources(struct dp_parser *parser) msm_dss_iounmap(&io->dp_aux); msm_dss_iounmap(&io->dp_link); msm_dss_iounmap(&io->dp_p0); - msm_dss_iounmap(&io->phy_io); - msm_dss_iounmap(&io->ln_tx0_io); - msm_dss_iounmap(&io->ln_tx0_io); - msm_dss_iounmap(&io->dp_pll_io); - msm_dss_iounmap(&io->usb3_dp_com); msm_dss_iounmap(&io->qfprom_io); } @@ -101,118 +99,21 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) goto err; } - rc = msm_dss_ioremap_byname(pdev, &io->phy_io, "dp_phy"); - if (rc) { - DRM_ERROR("unable to remap dp PHY resources, rc=%d\n", rc); - goto err; - } - - rc = msm_dss_ioremap_byname(pdev, &io->ln_tx0_io, "dp_ln_tx0"); - if (rc) { - DRM_ERROR("unable to remap dp TX0 resources, rc=%d\n", rc); - goto err; - } - - rc = msm_dss_ioremap_byname(pdev, &io->ln_tx1_io, "dp_ln_tx1"); - if (rc) { - DRM_ERROR("unable to remap dp TX1 resources, rc=%d\n", rc); - goto err; - } - - rc = msm_dss_ioremap_byname(pdev, &io->dp_pll_io, "dp_pll"); - if (rc) { - DRM_ERROR("unable to remap DP PLL resources, rc=%d\n", rc); - goto err; - } + if (msm_dss_ioremap_byname(pdev, &io->qfprom_io, "qfprom_physical")) + pr_warn("unable to remap dp qfprom resources\n"); - rc = msm_dss_ioremap_byname(pdev, &io->usb3_dp_com, "usb3_dp_com"); - if (rc) { - DRM_ERROR("unable to remap USB3 DP com resources, rc=%d\n", rc); + io->phy = devm_phy_get(&pdev->dev, "dp"); + if (IS_ERR(io->phy)) { + rc = PTR_ERR(io->phy); goto err; } - if (msm_dss_ioremap_byname(pdev, &io->qfprom_io, "qfprom_physical")) - pr_warn("unable to remap dp qfprom resources\n"); - return 0; err: dp_parser_unmap_io_resources(parser); return rc; } -static const char *dp_get_phy_aux_config_property(u32 cfg_type) -{ - switch (cfg_type) { - case PHY_AUX_CFG0: - return "aux-cfg0-settings"; - case PHY_AUX_CFG1: - return "aux-cfg1-settings"; - case PHY_AUX_CFG2: - return "aux-cfg2-settings"; - case PHY_AUX_CFG3: - return "aux-cfg3-settings"; - case PHY_AUX_CFG4: - return "aux-cfg4-settings"; - case PHY_AUX_CFG5: - return "aux-cfg5-settings"; - case PHY_AUX_CFG6: - return "aux-cfg6-settings"; - case PHY_AUX_CFG7: - return "aux-cfg7-settings"; - case PHY_AUX_CFG8: - return "aux-cfg8-settings"; - case PHY_AUX_CFG9: - return "aux-cfg9-settings"; - default: - return "unknown"; - } -} - -static int dp_parser_aux(struct dp_parser *parser) -{ - struct device_node *of_node = parser->pdev->dev.of_node; - int len = 0, i = 0, j = 0, config_count = 0; - const char *data; - - for (i = 0; i < PHY_AUX_CFG_MAX; i++) { - const char *property = dp_get_phy_aux_config_property(i); - - data = of_get_property(of_node, property, &len); - if (!data) { - DRM_ERROR("Unable to read %s\n", property); - goto error; - } - - config_count = len - 1; - if (config_count < 1 || /* minimum config count = 1 */ - config_count > DP_AUX_CFG_MAX_VALUE_CNT) { - DRM_ERROR("Invalid config count (%d) configs for %s\n", - config_count, property); - goto error; - } - - parser->aux_cfg[i].offset = data[0]; - parser->aux_cfg[i].cfg_cnt = config_count; - DRM_DEBUG_DP("%s offset=0x%x, cfg_cnt=%d\n", - property, - parser->aux_cfg[i].offset, - parser->aux_cfg[i].cfg_cnt); - for (j = 1; j < len; j++) { - parser->aux_cfg[i].lut[j - 1] = data[j]; - DRM_DEBUG_DP("%s lut[%d]=0x%x\n", - property, - i, - parser->aux_cfg[i].lut[j - 1]); - } - } - return 0; - -error: - memset(parser->aux_cfg, 0, sizeof(parser->aux_cfg)); - - return -EINVAL; -} - static int dp_parser_misc(struct dp_parser *parser) { u32 rc; @@ -257,7 +158,7 @@ static int dp_parser_pinctrl(struct dp_parser *parser) pinctrl->state_active = pinctrl_lookup_state(pinctrl->pin, "mdss_dp_active"); if (IS_ERR(pinctrl->state_active)) { - DRM_ERROR("failed to get pinctrl active state, %d\n", + DRM_ERROR("failed to get pinctrl active state, %ld\n", PTR_ERR(pinctrl->state_active)); return -EINVAL; } @@ -265,7 +166,7 @@ static int dp_parser_pinctrl(struct dp_parser *parser) pinctrl->state_suspend = pinctrl_lookup_state(pinctrl->pin, "mdss_dp_sleep"); if (IS_ERR(pinctrl->state_suspend)) { - DRM_ERROR("failed to get pinctrl suspend state, %d\n", + DRM_ERROR("failed to get pinctrl suspend state, %ld\n", PTR_ERR(pinctrl->state_suspend)); return -EINVAL; } @@ -451,10 +352,6 @@ static int dp_parser_parse(struct dp_parser *parser) if (rc) return rc; - rc = dp_parser_aux(parser); - if (rc) - return rc; - rc = dp_parser_misc(parser); if (rc) return rc; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index f9c572e8fd90..e1972ad48c45 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -6,7 +6,10 @@ #ifndef _DP_PARSER_H_ #define _DP_PARSER_H_ -#include "pll/dp_pll.h" +#include +#include + +#include "dpu_io_util.h" #define DP_LABEL "MDSS DP DISPLAY" #define AUX_CFG_LEN 10 @@ -59,12 +62,7 @@ struct dp_display_data { * @dp_aux: controller's aux mapped memory address * @dp_link: controller's link mapped memory address * @dp_p0: controller's p0 mapped memory address - * @phy_io: phy's mapped memory address - * @ln_tx0_io: USB-DP lane TX0's mapped memory address - * @ln_tx1_io: USB-DP lane TX1's mapped memory address * @qfprom_io: qfprom's mapped memory address - * @dp_pll_io: DP PLL mapped memory address - * @usb3_dp_com: USB3 DP PHY combo mapped memory address */ struct dp_io { struct dss_io_data ctrl_io; @@ -72,12 +70,9 @@ struct dp_io { struct dss_io_data dp_aux; struct dss_io_data dp_link; struct dss_io_data dp_p0; - struct dss_io_data phy_io; - struct dss_io_data ln_tx0_io; - struct dss_io_data ln_tx1_io; struct dss_io_data qfprom_io; - struct dss_io_data dp_pll_io; - struct dss_io_data usb3_dp_com; + struct phy *phy; + union phy_configure_opts phy_opts; }; /** @@ -95,38 +90,6 @@ struct dp_pinctrl { struct pinctrl_state *state_suspend; }; -#define DP_ENUM_STR(x) #x -#define DP_AUX_CFG_MAX_VALUE_CNT 3 -/** - * struct dp_aux_cfg - DP's AUX configuration settings - * - * @cfg_cnt: count of the configurable settings for the AUX register - * @current_index: current index of the AUX config lut - * @offset: register offset of the AUX config register - * @lut: look up table for the AUX config values for this register - */ -struct dp_aux_cfg { - u32 cfg_cnt; - u32 current_index; - u32 offset; - u32 lut[DP_AUX_CFG_MAX_VALUE_CNT]; -}; - -/* PHY AUX config registers */ -enum dp_phy_aux_config_type { - PHY_AUX_CFG0, - PHY_AUX_CFG1, - PHY_AUX_CFG2, - PHY_AUX_CFG3, - PHY_AUX_CFG4, - PHY_AUX_CFG5, - PHY_AUX_CFG6, - PHY_AUX_CFG7, - PHY_AUX_CFG8, - PHY_AUX_CFG9, - PHY_AUX_CFG_MAX, -}; - #define DP_DEV_REGULATOR_MAX 4 /* Regulators for DP devices */ @@ -141,35 +104,6 @@ struct dp_regulator_cfg { struct dp_reg_entry regs[DP_DEV_REGULATOR_MAX]; }; - -static inline char *dp_phy_aux_config_type_to_string(u32 cfg_type) -{ - switch (cfg_type) { - case PHY_AUX_CFG0: - return DP_ENUM_STR(PHY_AUX_CFG0); - case PHY_AUX_CFG1: - return DP_ENUM_STR(PHY_AUX_CFG1); - case PHY_AUX_CFG2: - return DP_ENUM_STR(PHY_AUX_CFG2); - case PHY_AUX_CFG3: - return DP_ENUM_STR(PHY_AUX_CFG3); - case PHY_AUX_CFG4: - return DP_ENUM_STR(PHY_AUX_CFG4); - case PHY_AUX_CFG5: - return DP_ENUM_STR(PHY_AUX_CFG5); - case PHY_AUX_CFG6: - return DP_ENUM_STR(PHY_AUX_CFG6); - case PHY_AUX_CFG7: - return DP_ENUM_STR(PHY_AUX_CFG7); - case PHY_AUX_CFG8: - return DP_ENUM_STR(PHY_AUX_CFG8); - case PHY_AUX_CFG9: - return DP_ENUM_STR(PHY_AUX_CFG9); - default: - return "unknown"; - } -} - /** * struct dp_parser - DP parser's data exposed to clients * @@ -194,11 +128,8 @@ struct dp_parser { bool combo_phy_en; struct dp_io io; struct dp_display_data disp_data; - struct msm_dp_pll *pll; - struct device *pll_dev; const struct dp_regulator_cfg *regulator_cfg; u8 l_map[4]; - struct dp_aux_cfg aux_cfg[AUX_CFG_LEN]; u32 max_pclk_khz; u32 max_dp_lanes; diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index 26f84b351c7b..f6fd83beeb73 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -9,6 +9,7 @@ #include #include #include "dp_power.h" +#include "msm_drv.h" struct dp_power_private { struct dp_parser *parser; @@ -124,16 +125,6 @@ static int dp_power_clk_init(struct dp_power_private *power) core = &power->parser->mp[DP_CORE_PM]; ctrl = &power->parser->mp[DP_CTRL_PM]; - if (power->parser->pll && power->parser->pll->get_provider) { - rc = power->parser->pll->get_provider(power->parser->pll, - &power->link_provider, &power->pixel_provider); - if (rc) { - DRM_ERROR("%s:provider failed,don't set parent\n", - __func__); - return 0; - } - } - rc = msm_dss_get_clk(dev, core->clk_config, core->num_clk); if (rc) { DRM_ERROR("failed to get %s clk. err=%d\n", @@ -390,73 +381,6 @@ void dp_power_client_deinit(struct dp_power *dp_power) } -int dp_power_set_link_clk_parent(struct dp_power *dp_power) -{ - int rc = 0; - struct dp_power_private *power; - u32 num; - struct dss_clk *cfg; - char *name = "ctrl_link_clk"; - - if (!dp_power) { - DRM_ERROR("invalid power data\n"); - rc = -EINVAL; - goto exit; - } - - power = container_of(dp_power, struct dp_power_private, dp_power); - - num = power->parser->mp[DP_CTRL_PM].num_clk; - cfg = power->parser->mp[DP_CTRL_PM].clk_config; - - while (num && strcmp(cfg->clk_name, name)) { - num--; - cfg++; - } - - if (num && power->link_provider) { - power->link_clk_src = clk_get_parent(cfg->clk); - if (power->link_clk_src) { - clk_set_parent(power->link_clk_src, - power->link_provider); - DRM_DEBUG_DP("%s: is the parent of clk=%s\n", - __clk_get_name(power->link_provider), - __clk_get_name(power->link_clk_src)); - } else { - DRM_ERROR("couldn't get parent for clk=%s\n", - name); - rc = -EINVAL; - } - } else { - DRM_ERROR("%s clock could not be set parent\n", name); - rc = -EINVAL; - } -exit: - return rc; -} - -int dp_power_set_pixel_clk_parent(struct dp_power *dp_power) -{ - int rc = 0; - struct dp_power_private *power; - - power = container_of(dp_power, struct dp_power_private, dp_power); - - if (power->pixel_clk_rcg && power->pixel_provider) { - rc = clk_set_parent(power->pixel_clk_rcg, - power->pixel_provider); - if (rc) { - DRM_ERROR("failed to set parent clk src, %d\n", rc); - return rc; - } - DRM_DEBUG_DP("%s: is the parent of clk=%s\n", - __clk_get_name(power->pixel_provider), - __clk_get_name(power->pixel_clk_rcg)); - } - - return 0; -} - int dp_power_init(struct dp_power *dp_power, bool flip) { int rc = 0; diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h index 3dc4a525f435..d61194eb58aa 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.h +++ b/drivers/gpu/drm/msm/dp/dp_power.h @@ -57,27 +57,6 @@ int dp_power_deinit(struct dp_power *power); int dp_power_clk_enable(struct dp_power *power, enum dp_pm_type pm_type, bool enable); -/** - * dp_power_set_link_clk_parent() - configures parent of link clocks - * - * @power: instance of power module - * return: 0 for success, error for failures - * - * This API will set the link clock parent source - */ -int dp_power_set_link_clk_parent(struct dp_power *power); - - -/** - * dp_power_set_pixel_clk_parent() - configures parent of pixel clocks - * - * @power: instance of power module - * return: 0 for success, error for failures - * - * This API will set the pixel clock parent source - */ -int dp_power_set_pixel_clk_parent(struct dp_power *power); - /** * dp_power_clinet_init() - initialize clock and regulator modules * diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll.c b/drivers/gpu/drm/msm/dp/pll/dp_pll.c deleted file mode 100644 index a58eb710685e..000000000000 --- a/drivers/gpu/drm/msm/dp/pll/dp_pll.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#include "dp_pll.h" - -int msm_dp_pll_util_parse_dt_clock(struct platform_device *pdev, - struct msm_dp_pll *pll) -{ - u32 i = 0, rc = 0; - struct dss_module_power *mp = &pll->mp; - const char *clock_name; - - mp->num_clk = of_property_count_strings(pdev->dev.of_node, - "clock-names"); - if (mp->num_clk <= 0) { - DRM_DEV_ERROR(&pdev->dev, "%s:clocks are not defined\n", - __func__); - goto clk_err; - } - - mp->clk_config = devm_kcalloc(&pdev->dev, - sizeof(struct dss_clk), mp->num_clk, GFP_KERNEL); - if (!mp->clk_config) { - rc = -ENOMEM; - mp->num_clk = 0; - goto clk_err; - } - - for (i = 0; i < mp->num_clk; i++) { - of_property_read_string_index(pdev->dev.of_node, "clock-names", - i, &clock_name); - strlcpy(mp->clk_config[i].clk_name, clock_name, - sizeof(mp->clk_config[i].clk_name)); - - mp->clk_config[i].type = DSS_CLK_AHB; - } - -clk_err: - return rc; -} - -struct msm_dp_pll *msm_dp_pll_init(struct platform_device *pdev, - enum msm_dp_pll_type type, int id) -{ - struct device *dev = &pdev->dev; - struct msm_dp_pll *pll; - - switch (type) { - case MSM_DP_PLL_10NM: - pll = msm_dp_pll_10nm_init(pdev, id); - break; - default: - pll = ERR_PTR(-ENXIO); - break; - } - - if (IS_ERR(pll)) { - DRM_DEV_ERROR(dev, "%s: failed to init DP PLL\n", __func__); - return pll; - } - - pll->type = type; - - DRM_DEBUG_DP("DP:%d PLL registered", id); - - return pll; -} - -static const struct of_device_id dp_pll_dt_match[] = { - { .compatible = "qcom,dp-pll-10nm" }, - { } -}; - -static int dp_pll_driver_probe(struct platform_device *pdev) -{ - struct msm_dp_pll *pll; - struct device *dev = &pdev->dev; - const struct of_device_id *match; - - match = of_match_node(dp_pll_dt_match, dev->of_node); - if (!match) - return -ENODEV; - - pll = msm_dp_pll_init(pdev, MSM_DP_PLL_10NM, 0); - if (IS_ERR_OR_NULL(pll)) { - DRM_DEV_ERROR(dev, - "%s: pll init failed: %ld\n",__func__, PTR_ERR(pll)); - return -ENODEV; - } - - platform_set_drvdata(pdev, pll); - - return 0; -} - -static int dp_pll_driver_remove(struct platform_device *pdev) -{ - struct msm_dp_pll *pll = platform_get_drvdata(pdev); - - if (pll) - pll = NULL; - - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static struct platform_driver dp_pll_platform_driver = { - .probe = dp_pll_driver_probe, - .remove = dp_pll_driver_remove, - .driver = { - .name = "msm_dp_pll", - .of_match_table = dp_pll_dt_match, - }, -}; - -void __init msm_dp_pll_driver_register(void) -{ - platform_driver_register(&dp_pll_platform_driver); -} - -void __exit msm_dp_pll_driver_unregister(void) -{ - platform_driver_unregister(&dp_pll_platform_driver); -} diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll.h b/drivers/gpu/drm/msm/dp/pll/dp_pll.h deleted file mode 100644 index 236a55bee8da..000000000000 --- a/drivers/gpu/drm/msm/dp/pll/dp_pll.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DP_PLL_H -#define __DP_PLL_H - -#include -#include -#include - -#include "dpu_io_util.h" -#include "msm_drv.h" - -#define PLL_REG_W(base, offset, data) \ - writel((data), (base) + (offset)) -#define PLL_REG_R(base, offset) readl((base) + (offset)) - -enum msm_dp_pll_type { - MSM_DP_PLL_10NM, - MSM_DP_PLL_MAX -}; - -struct msm_dp_pll { - enum msm_dp_pll_type type; - struct clk_hw clk_hw; - unsigned long rate; /* current vco rate */ - u64 min_rate; /* min vco rate */ - u64 max_rate; /* max vco rate */ - bool pll_on; - void *priv; - /* Pll specific resources like GPIO, power supply, clocks, etc*/ - struct dss_module_power mp; - int (*get_provider)(struct msm_dp_pll *pll, - struct clk **link_clk_provider, - struct clk **pixel_clk_provider); -}; - -#define to_msm_dp_pll(x) container_of(x, struct msm_dp_pll, clk_hw) - -struct msm_dp_pll *msm_dp_pll_init(struct platform_device *pdev, - enum msm_dp_pll_type type, int id); - -int msm_dp_pll_util_parse_dt_clock(struct platform_device *pdev, - struct msm_dp_pll *pll); - -#ifdef CONFIG_DRM_MSM_DP_10NM_PLL -struct msm_dp_pll *msm_dp_pll_10nm_init(struct platform_device *pdev, int id); -#else -static inline struct msm_dp_pll * -msm_dp_pll_10nm_init(struct platform_device *pdev, int id) -{ - return ERR_PTR(-ENODEV); -} -#endif -#endif /* __DP_PLL_H */ diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c deleted file mode 100644 index aa845d0f5a03..000000000000 --- a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c +++ /dev/null @@ -1,401 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -/* - * Display Port PLL driver block diagram for branch clocks - * - * +------------------------------+ - * | DP_VCO_CLK | - * | | - * | +-------------------+ | - * | | (DP PLL/VCO) | | - * | +---------+---------+ | - * | v | - * | +----------+-----------+ | - * | | hsclk_divsel_clk_src | | - * | +----------+-----------+ | - * +------------------------------+ - * | - * +---------<---------v------------>----------+ - * | | - * +--------v---------+ | - * | dp_phy_pll | | - * | link_clk | | - * +--------+---------+ | - * | | - * | | - * v v - * Input to DISPCC block | - * for link clk, crypto clk | - * and interface clock | - * | - * | - * +--------<------------+-----------------+---<---+ - * | | | - * +----v---------+ +--------v-----+ +--------v------+ - * | vco_divided | | vco_divided | | vco_divided | - * | _clk_src | | _clk_src | | _clk_src | - * | | | | | | - * |divsel_six | | divsel_two | | divsel_four | - * +-------+------+ +-----+--------+ +--------+------+ - * | | | - * v---->----------v-------------<------v - * | - * +----------+---------+ - * | dp_phy_pll_vco | - * | div_clk | - * +---------+----------+ - * | - * v - * Input to DISPCC block - * for DP pixel clock - * - */ - -#include -#include -#include -#include -#include - -#include "dp_pll_10nm.h" - -#define NUM_PROVIDED_CLKS 2 - -#define DP_LINK_CLK_SRC 0 -#define DP_PIXEL_CLK_SRC 1 - -static struct dp_pll_10nm *dp_pdb; - -static const struct clk_ops dp_10nm_vco_clk_ops = { - .recalc_rate = dp_vco_recalc_rate_10nm, - .set_rate = dp_vco_set_rate_10nm, - .round_rate = dp_vco_round_rate_10nm, - .prepare = dp_vco_prepare_10nm, - .unprepare = dp_vco_unprepare_10nm, -}; - -struct dp_pll_10nm_pclksel { - struct clk_hw hw; - - /* divider params */ - u8 shift; - u8 width; - u8 flags; /* same flags as used by clk_divider struct */ - - struct dp_pll_10nm *pll; -}; -#define to_pll_10nm_pclksel(_hw) \ - container_of(_hw, struct dp_pll_10nm_pclksel, hw) - -static const struct clk_parent_data disp_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, - { .fw_name = "dp_phy_pll_vco_div_clk", - .name = "dp_phy_pll_vco_div_clk"}, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, -}; - -static int dp_pll_mux_set_parent_10nm(struct clk_hw *hw, u8 val) -{ - struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw); - struct dp_pll_10nm *dp_res = pclksel->pll; - u32 auxclk_div; - - auxclk_div = PLL_REG_R(dp_res->phy_base, REG_DP_PHY_VCO_DIV); - auxclk_div &= ~0x03; - - if (val == 0) - auxclk_div |= 1; - else if (val == 1) - auxclk_div |= 2; - else if (val == 2) - auxclk_div |= 0; - - PLL_REG_W(dp_res->phy_base, - REG_DP_PHY_VCO_DIV, auxclk_div); - DRM_DEBUG_DP("%s: mux=%d auxclk_div=%x\n", __func__, val, auxclk_div); - - return 0; -} - -static u8 dp_pll_mux_get_parent_10nm(struct clk_hw *hw) -{ - u32 auxclk_div = 0; - struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw); - struct dp_pll_10nm *dp_res = pclksel->pll; - u8 val = 0; - - auxclk_div = PLL_REG_R(dp_res->phy_base, REG_DP_PHY_VCO_DIV); - auxclk_div &= 0x03; - - if (auxclk_div == 1) /* Default divider */ - val = 0; - else if (auxclk_div == 2) - val = 1; - else if (auxclk_div == 0) - val = 2; - - DRM_DEBUG_DP("%s: auxclk_div=%d, val=%d\n", __func__, auxclk_div, val); - - return val; -} - -static int dp_pll_clk_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - unsigned long rate = 0; - int ret = 0; - - rate = clk_get_rate(hw->clk); - - if (rate <= 0) { - DRM_ERROR("Rate is not set properly\n"); - return -EINVAL; - } - - req->rate = rate; - - DRM_DEBUG_DP("%s: rate=%ld\n", __func__, req->rate); - /* Set the new parent of mux if there is a new valid parent */ - if (hw->clk && req->best_parent_hw->clk) { - ret = clk_set_parent(hw->clk, req->best_parent_hw->clk); - if (ret) { - DRM_ERROR("%s: clk_set_parent failed: ret=%d\n", - __func__, ret); - return ret; - } - } - return 0; -} - -static unsigned long dp_pll_mux_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_hw *div_clk_hw = NULL, *vco_clk_hw = NULL; - struct msm_dp_pll *vco = NULL; - - div_clk_hw = clk_hw_get_parent(hw); - if (!div_clk_hw) - return 0; - - vco_clk_hw = clk_hw_get_parent(div_clk_hw); - if (!vco_clk_hw) - return 0; - - vco = to_msm_dp_pll(vco_clk_hw); - if (!vco) - return 0; - - if (vco->rate == DP_VCO_HSCLK_RATE_8100MHZDIV1000) - return (vco->rate / 6); - else if (vco->rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000) - return (vco->rate / 4); - else - return (vco->rate / 2); -} - -static int dp_pll_10nm_get_provider(struct msm_dp_pll *pll, - struct clk **link_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dp_pll_10nm *pll_10nm = to_dp_pll_10nm(pll); - struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data; - - if (link_clk_provider) - *link_clk_provider = hw_data->hws[DP_LINK_CLK_SRC]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DP_PIXEL_CLK_SRC]->clk; - - return 0; -} - -static const struct clk_ops dp_10nm_pclksel_clk_ops = { - .get_parent = dp_pll_mux_get_parent_10nm, - .set_parent = dp_pll_mux_set_parent_10nm, - .recalc_rate = dp_pll_mux_recalc_rate, - .determine_rate = dp_pll_clk_mux_determine_rate, -}; - -static struct clk_hw *dp_pll_10nm_pixel_clk_sel(struct dp_pll_10nm *pll_10nm) -{ - struct device *dev = &pll_10nm->pdev->dev; - struct dp_pll_10nm_pclksel *pll_pclksel; - struct clk_init_data pclksel_init = { - .parent_data = disp_cc_parent_data_0, - .num_parents = 3, - .name = "dp_phy_pll_vco_div_clk", - .ops = &dp_10nm_pclksel_clk_ops, - }; - int ret; - - pll_pclksel = devm_kzalloc(dev, sizeof(*pll_pclksel), GFP_KERNEL); - if (!pll_pclksel) - return ERR_PTR(-ENOMEM); - - pll_pclksel->pll = pll_10nm; - pll_pclksel->shift = 0; - pll_pclksel->width = 4; - pll_pclksel->flags = CLK_DIVIDER_ONE_BASED; - pll_pclksel->hw.init = &pclksel_init; - - ret = clk_hw_register(dev, &pll_pclksel->hw); - if (ret) - return ERR_PTR(ret); - - return &pll_pclksel->hw; -} - -static int dp_pll_10nm_register(struct dp_pll_10nm *pll_10nm) -{ - struct clk_init_data vco_init = { - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - }, - .num_parents = 1, - .name = "dp_vco_clk", - .ops = &dp_10nm_vco_clk_ops, - }; - struct device *dev = &pll_10nm->pdev->dev; - struct clk_hw **hws = pll_10nm->hws; - struct clk_hw_onecell_data *hw_data; - struct clk_hw *hw; - int num = 0; - int ret; - - DRM_DEBUG_DP("DP->id = %d", pll_10nm->id); - - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - - pll_10nm->base.clk_hw.init = &vco_init; - ret = clk_hw_register(dev, &pll_10nm->base.clk_hw); - if (ret) - return ret; - hws[num++] = &pll_10nm->base.clk_hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_phy_pll_link_clk", "dp_vco_clk", - CLK_SET_RATE_PARENT, 1, 10); - if (IS_ERR(hw)) - return PTR_ERR(hw); - hws[num++] = hw; - hw_data->hws[DP_LINK_CLK_SRC] = hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_two_clk_src", "dp_vco_clk", - 0, 1, 2); - if (IS_ERR(hw)) - return PTR_ERR(hw); - hws[num++] = hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_four_clk_src", "dp_vco_clk", - 0, 1, 4); - if (IS_ERR(hw)) - return PTR_ERR(hw); - hws[num++] = hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_six_clk_src", "dp_vco_clk", - 0, 1, 6); - if (IS_ERR(hw)) - return PTR_ERR(hw); - hws[num++] = hw; - - hw = dp_pll_10nm_pixel_clk_sel(pll_10nm); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - hws[num++] = hw; - hw_data->hws[DP_PIXEL_CLK_SRC] = hw; - - pll_10nm->num_hws = num; - - hw_data->num = NUM_PROVIDED_CLKS; - pll_10nm->hw_data = hw_data; - - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - pll_10nm->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", - ret); - return ret; - } - - return ret; -} - -struct msm_dp_pll *msm_dp_pll_10nm_init(struct platform_device *pdev, int id) -{ - struct dp_pll_10nm *dp_10nm_pll; - struct msm_dp_pll *pll; - int ret; - - if (!pdev) - return ERR_PTR(-ENODEV); - - dp_10nm_pll = devm_kzalloc(&pdev->dev, - sizeof(*dp_10nm_pll), GFP_KERNEL); - if (!dp_10nm_pll) - return ERR_PTR(-ENOMEM); - - DRM_DEBUG_DP("DP PLL%d", id); - - dp_10nm_pll->pdev = pdev; - dp_10nm_pll->id = id; - dp_pdb = dp_10nm_pll; - - dp_10nm_pll->pll_base = msm_ioremap(pdev, "pll_base", "DP_PLL"); - if (IS_ERR_OR_NULL(dp_10nm_pll->pll_base)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PLL base\n"); - return ERR_PTR(-ENOMEM); - } - - dp_10nm_pll->phy_base = msm_ioremap(pdev, "phy_base", "DP_PHY"); - if (IS_ERR_OR_NULL(dp_10nm_pll->phy_base)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return ERR_PTR(-ENOMEM); - } - - dp_10nm_pll->ln_tx0_base = msm_ioremap(pdev, "ln_tx0_base", - "DP_LN_TX0"); - if (IS_ERR_OR_NULL(dp_10nm_pll->ln_tx0_base)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN LN_TX0 base\n"); - return ERR_PTR(-ENOMEM); - } - - dp_10nm_pll->ln_tx1_base = msm_ioremap(pdev, "ln_tx1_base", - "DP_LN_TX1"); - if (IS_ERR_OR_NULL(dp_10nm_pll->ln_tx1_base)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN LN_TX1 base\n"); - return ERR_PTR(-ENOMEM); - } - - ret = of_property_read_u32(pdev->dev.of_node, "cell-index", - &dp_10nm_pll->index); - if (ret) { - DRM_ERROR("Unable to get the cell-index ret=%d\n", ret); - dp_10nm_pll->index = 0; - } - - ret = msm_dp_pll_util_parse_dt_clock(pdev, &dp_10nm_pll->base); - if (ret) { - DRM_ERROR("Unable to parse dt clocks ret=%d\n", ret); - return ERR_PTR(ret); - } - - ret = dp_pll_10nm_register(dp_10nm_pll); - if (ret) { - DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); - } - - pll = &dp_10nm_pll->base; - pll->min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000; - pll->max_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000; - pll->get_provider = dp_pll_10nm_get_provider; - - return pll; -} diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h deleted file mode 100644 index 84664634a53d..000000000000 --- a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DP_PLL_10NM_H -#define __DP_PLL_10NM_H - -#include "dp_pll.h" -#include "dp_reg.h" - -#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL -#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL -#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL -#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL - -#define NUM_DP_CLOCKS_MAX 6 - -#define DP_PHY_PLL_POLL_SLEEP_US 500 -#define DP_PHY_PLL_POLL_TIMEOUT_US 10000 - -#define DP_VCO_RATE_8100MHZDIV1000 8100000UL -#define DP_VCO_RATE_9720MHZDIV1000 9720000UL -#define DP_VCO_RATE_10800MHZDIV1000 10800000UL - -struct dp_pll_10nm { - struct msm_dp_pll base; - - int id; - struct platform_device *pdev; - - void __iomem *pll_base; - void __iomem *phy_base; - void __iomem *ln_tx0_base; - void __iomem *ln_tx1_base; - - /* private clocks: */ - struct clk_hw *hws[NUM_DP_CLOCKS_MAX]; - u32 num_hws; - - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - - /* lane and orientation settings */ - u8 lane_cnt; - u8 orientation; - - /* COM PHY settings */ - u32 hsclk_sel; - u32 dec_start_mode0; - u32 div_frac_start1_mode0; - u32 div_frac_start2_mode0; - u32 div_frac_start3_mode0; - u32 integloop_gain0_mode0; - u32 integloop_gain1_mode0; - u32 vco_tune_map; - u32 lock_cmp1_mode0; - u32 lock_cmp2_mode0; - u32 lock_cmp3_mode0; - u32 lock_cmp_en; - - /* PHY vco divider */ - u32 phy_vco_div; - /* - * Certain pll's needs to update the same vco rate after resume in - * suspend/resume scenario. Cached the vco rate for such plls. - */ - unsigned long vco_cached_rate; - u32 cached_cfg0; - u32 cached_cfg1; - u32 cached_outdiv; - - uint32_t index; -}; - -#define to_dp_pll_10nm(x) container_of(x, struct dp_pll_10nm, base) - -int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); -unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw, - unsigned long parent_rate); -long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate); -int dp_vco_prepare_10nm(struct clk_hw *hw); -void dp_vco_unprepare_10nm(struct clk_hw *hw); -#endif /* __DP_PLL_10NM_H */ diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c deleted file mode 100644 index fff2e8d16e3b..000000000000 --- a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c +++ /dev/null @@ -1,524 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#define pr_fmt(fmt) "%s: " fmt, __func__ - -#include -#include -#include -#include - -#include "dp_hpd.h" -#include "dp_pll.h" -#include "dp_pll_10nm.h" - -static int dp_vco_pll_init_db_10nm(struct msm_dp_pll *pll, - unsigned long rate) -{ - struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll); - u32 spare_value = 0; - - spare_value = PLL_REG_R(dp_res->phy_base, REG_DP_PHY_SPARE0); - dp_res->lane_cnt = spare_value & 0x0F; - dp_res->orientation = (spare_value & 0xF0) >> 4; - - DRM_DEBUG_DP("%s: spare_value=0x%x, ln_cnt=0x%x, orientation=0x%x\n", - __func__, spare_value, dp_res->lane_cnt, - dp_res->orientation); - - switch (rate) { - case DP_VCO_HSCLK_RATE_1620MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_9720MHZDIV1000); - dp_res->hsclk_sel = 0x0c; - dp_res->dec_start_mode0 = 0x69; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x80; - dp_res->div_frac_start3_mode0 = 0x07; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x6f; - dp_res->lock_cmp2_mode0 = 0x08; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x1; - dp_res->lock_cmp_en = 0x00; - break; - case DP_VCO_HSCLK_RATE_2700MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_10800MHZDIV1000); - dp_res->hsclk_sel = 0x04; - dp_res->dec_start_mode0 = 0x69; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x80; - dp_res->div_frac_start3_mode0 = 0x07; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x0f; - dp_res->lock_cmp2_mode0 = 0x0e; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x1; - dp_res->lock_cmp_en = 0x00; - break; - case DP_VCO_HSCLK_RATE_5400MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_10800MHZDIV1000); - dp_res->hsclk_sel = 0x00; - dp_res->dec_start_mode0 = 0x8c; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x00; - dp_res->div_frac_start3_mode0 = 0x0a; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x1f; - dp_res->lock_cmp2_mode0 = 0x1c; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x2; - dp_res->lock_cmp_en = 0x00; - break; - case DP_VCO_HSCLK_RATE_8100MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_8100MHZDIV1000); - dp_res->hsclk_sel = 0x03; - dp_res->dec_start_mode0 = 0x69; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x80; - dp_res->div_frac_start3_mode0 = 0x07; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x2f; - dp_res->lock_cmp2_mode0 = 0x2a; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x0; - dp_res->lock_cmp_en = 0x08; - break; - default: - return -EINVAL; - } - return 0; -} - -static int dp_config_vco_rate_10nm(struct msm_dp_pll *pll, - unsigned long rate) -{ - u32 res = 0; - struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll); - - res = dp_vco_pll_init_db_10nm(pll, rate); - if (res) { - DRM_ERROR("VCO Init DB failed\n"); - return res; - } - - if (dp_res->lane_cnt != 4) { - if (dp_res->orientation == ORIENTATION_CC2) - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_PD_CTL, 0x6d); - else - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_PD_CTL, 0x75); - } else { - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_PD_CTL, 0x7d); - } - - PLL_REG_W(dp_res->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_SYSCLK_EN_SEL, 0x37); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x02); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_CLK_ENABLE1, 0x0e); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_CLK_SEL, 0x30); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_CMN_CONFIG, 0x02); - - /* Different for each clock rates */ - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_HSCLK_SEL, dp_res->hsclk_sel); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_DEC_START_MODE0, dp_res->dec_start_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_DIV_FRAC_START1_MODE0, - dp_res->div_frac_start1_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_DIV_FRAC_START2_MODE0, - dp_res->div_frac_start2_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_DIV_FRAC_START3_MODE0, - dp_res->div_frac_start3_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_INTEGLOOP_GAIN0_MODE0, - dp_res->integloop_gain0_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_INTEGLOOP_GAIN1_MODE0, - dp_res->integloop_gain1_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_VCO_TUNE_MAP, dp_res->vco_tune_map); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_LOCK_CMP1_MODE0, dp_res->lock_cmp1_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_LOCK_CMP2_MODE0, dp_res->lock_cmp2_mode0); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_LOCK_CMP3_MODE0, dp_res->lock_cmp3_mode0); - - PLL_REG_W(dp_res->pll_base, QSERDES_COM_BG_TIMER, 0x0a); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_CORECLK_DIV_MODE0, 0x0a); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_VCO_TUNE_CTRL, 0x00); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_CORE_CLK_EN, 0x1f); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_PLL_IVCO, 0x07); - PLL_REG_W(dp_res->pll_base, - QSERDES_COM_LOCK_CMP_EN, dp_res->lock_cmp_en); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); - PLL_REG_W(dp_res->pll_base, QSERDES_COM_CP_CTRL_MODE0, 0x06); - - if (dp_res->orientation == ORIENTATION_CC2) - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_MODE, 0x4c); - else - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_MODE, 0x5c); - - /* TX Lane configuration */ - PLL_REG_W(dp_res->phy_base, - REG_DP_PHY_TX0_TX1_LANE_CTL, 0x05); - PLL_REG_W(dp_res->phy_base, - REG_DP_PHY_TX2_TX3_LANE_CTL, 0x05); - - /* TX-0 register configuration */ - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, 0x1a); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_VMODE_CTRL1, 0x40); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN, 0x30); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_INTERFACE_SELECT, 0x3d); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_CLKBUF_ENABLE, 0x0f); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_RESET_TSYNC_EN, 0x03); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN, 0x03); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_TX_INTERFACE_MODE, 0x00); - PLL_REG_W(dp_res->ln_tx0_base, REG_DP_PHY_TXn_TX_BAND, 0x4); - - /* TX-1 register configuration */ - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, 0x1a); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_VMODE_CTRL1, 0x40); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN, 0x30); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_INTERFACE_SELECT, 0x3d); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_CLKBUF_ENABLE, 0x0f); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_RESET_TSYNC_EN, 0x03); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN, 0x03); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_TX_INTERFACE_MODE, 0x00); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_TX_BAND, 0x4); - - /* dependent on the vco frequency */ - PLL_REG_W(dp_res->phy_base, - REG_DP_PHY_VCO_DIV, dp_res->phy_vco_div); - - return res; -} - -static bool dp_10nm_pll_lock_status(struct dp_pll_10nm *dp_res) -{ - u32 status; - bool pll_locked; - - /* poll for PLL lock status */ - if (readl_poll_timeout_atomic((dp_res->pll_base + - QSERDES_COM_C_READY_STATUS), - status, - ((status & BIT(0)) > 0), - DP_PHY_PLL_POLL_SLEEP_US, - DP_PHY_PLL_POLL_TIMEOUT_US)) { - DRM_ERROR("%s: C_READY status is not high. Status=%x\n", - __func__, status); - pll_locked = false; - } else { - pll_locked = true; - } - - return pll_locked; -} - -static bool dp_10nm_phy_rdy_status(struct dp_pll_10nm *dp_res) -{ - u32 status; - bool phy_ready = true; - - /* poll for PHY ready status */ - if (readl_poll_timeout_atomic((dp_res->phy_base + - REG_DP_PHY_STATUS), - status, - ((status & (BIT(1))) > 0), - DP_PHY_PLL_POLL_SLEEP_US, - DP_PHY_PLL_POLL_TIMEOUT_US)) { - DRM_ERROR("%s: Phy_ready is not high. Status=%x\n", - __func__, status); - phy_ready = false; - } - - return phy_ready; -} - -static int dp_pll_enable_10nm(struct clk_hw *hw) -{ - int rc = 0; - struct msm_dp_pll *pll = to_msm_dp_pll(hw); - struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll); - u32 bias_en, drvr_en; - - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_AUX_CFG2, 0x04); - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_CFG, 0x01); - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_CFG, 0x05); - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_CFG, 0x01); - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_CFG, 0x09); - - PLL_REG_W(dp_res->pll_base, QSERDES_COM_RESETSM_CNTRL, 0x20); - - if (!dp_10nm_pll_lock_status(dp_res)) { - rc = -EINVAL; - goto lock_err; - } - - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_CFG, 0x19); - /* poll for PHY ready status */ - if (!dp_10nm_phy_rdy_status(dp_res)) { - rc = -EINVAL; - goto lock_err; - } - - DRM_DEBUG_DP("%s: PLL is locked\n", __func__); - - if (dp_res->lane_cnt == 1) { - bias_en = 0x3e; - drvr_en = 0x13; - } else { - bias_en = 0x3f; - drvr_en = 0x10; - } - - if (dp_res->lane_cnt != 4) { - if (dp_res->orientation == ORIENTATION_CC1) { - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - } else { - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - } - } else { - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - } - - PLL_REG_W(dp_res->ln_tx0_base, REG_DP_PHY_TXn_TX_POL_INV, 0x0a); - PLL_REG_W(dp_res->ln_tx1_base, REG_DP_PHY_TXn_TX_POL_INV, 0x0a); - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_CFG, 0x18); - udelay(2000); - - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_CFG, 0x19); - - /* poll for PHY ready status */ - if (!dp_10nm_phy_rdy_status(dp_res)) { - rc = -EINVAL; - goto lock_err; - } - - PLL_REG_W(dp_res->ln_tx0_base, REG_DP_PHY_TXn_TX_DRV_LVL, 0x38); - PLL_REG_W(dp_res->ln_tx1_base, REG_DP_PHY_TXn_TX_DRV_LVL, 0x38); - PLL_REG_W(dp_res->ln_tx0_base, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, 0x20); - PLL_REG_W(dp_res->ln_tx1_base, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, 0x20); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX, 0x06); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX, 0x06); - PLL_REG_W(dp_res->ln_tx0_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX, 0x07); - PLL_REG_W(dp_res->ln_tx1_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX, 0x07); - -lock_err: - return rc; -} - -static int dp_pll_disable_10nm(struct clk_hw *hw) -{ - int rc = 0; - struct msm_dp_pll *pll = to_msm_dp_pll(hw); - struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll); - - /* Assert DP PHY power down */ - PLL_REG_W(dp_res->phy_base, REG_DP_PHY_PD_CTL, 0x2); - - return rc; -} - - -int dp_vco_prepare_10nm(struct clk_hw *hw) -{ - int rc = 0; - struct msm_dp_pll *pll = to_msm_dp_pll(hw); - struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll); - - DRM_DEBUG_DP("%s: rate = %ld\n", __func__, pll->rate); - if ((dp_res->vco_cached_rate != 0) - && (dp_res->vco_cached_rate == pll->rate)) { - rc = dp_vco_set_rate_10nm(hw, - dp_res->vco_cached_rate, dp_res->vco_cached_rate); - if (rc) { - DRM_ERROR("index=%d vco_set_rate failed. rc=%d\n", - rc, dp_res->index); - goto error; - } - } - - rc = dp_pll_enable_10nm(hw); - if (rc) { - DRM_ERROR("ndx=%d failed to enable dp pll\n", - dp_res->index); - goto error; - } - - pll->pll_on = true; -error: - return rc; -} - -void dp_vco_unprepare_10nm(struct clk_hw *hw) -{ - struct msm_dp_pll *pll = to_msm_dp_pll(hw); - struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll); - - if (!dp_res) { - DRM_ERROR("Invalid input parameter\n"); - return; - } - - if (!pll->pll_on) { - DRM_ERROR("pll resource can't be enabled\n"); - return; - } - dp_res->vco_cached_rate = pll->rate; - dp_pll_disable_10nm(hw); - - pll->pll_on = false; -} - -int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct msm_dp_pll *pll = to_msm_dp_pll(hw); - int rc; - - DRM_DEBUG_DP("DP lane CLK rate=%ld\n", rate); - - rc = dp_config_vco_rate_10nm(pll, rate); - if (rc) - DRM_ERROR("%s: Failed to set clk rate\n", __func__); - - pll->rate = rate; - - return 0; -} - -unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct msm_dp_pll *pll = to_msm_dp_pll(hw); - struct dp_pll_10nm *dp_res = to_dp_pll_10nm(pll); - u32 div, hsclk_div, link_clk_div = 0; - u64 vco_rate; - - div = PLL_REG_R(dp_res->pll_base, QSERDES_COM_HSCLK_SEL); - div &= 0x0f; - - if (div == 12) - hsclk_div = 6; /* Default */ - else if (div == 4) - hsclk_div = 4; - else if (div == 0) - hsclk_div = 2; - else if (div == 3) - hsclk_div = 1; - else { - DRM_DEBUG_DP("unknown divider. forcing to default\n"); - hsclk_div = 5; - } - - div = PLL_REG_R(dp_res->phy_base, REG_DP_PHY_AUX_CFG2); - div >>= 2; - - if ((div & 0x3) == 0) - link_clk_div = 5; - else if ((div & 0x3) == 1) - link_clk_div = 10; - else if ((div & 0x3) == 2) - link_clk_div = 20; - else - DRM_ERROR("%s: unsupported div. Phy_mode: %d\n", __func__, div); - - if (link_clk_div == 20) { - vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; - } else { - if (hsclk_div == 6) - vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000; - else if (hsclk_div == 4) - vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; - else if (hsclk_div == 2) - vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000; - else - vco_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000; - } - - DRM_DEBUG_DP("returning vco rate = %lu\n", (unsigned long)vco_rate); - - dp_res->vco_cached_rate = pll->rate = vco_rate; - return (unsigned long)vco_rate; -} - -long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - unsigned long rrate = rate; - struct msm_dp_pll *pll = to_msm_dp_pll(hw); - - if (rate <= pll->min_rate) - rrate = pll->min_rate; - else if (rate <= DP_VCO_HSCLK_RATE_2700MHZDIV1000) - rrate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; - else if (rate <= DP_VCO_HSCLK_RATE_5400MHZDIV1000) - rrate = DP_VCO_HSCLK_RATE_5400MHZDIV1000; - else - rrate = pll->max_rate; - - DRM_DEBUG_DP("%s: rrate=%ld\n", __func__, rrate); - - *parent_rate = rrate; - return rrate; -} -