From patchwork Thu Jun 18 15:38:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11612585 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42E5F159A for ; Thu, 18 Jun 2020 15:41:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3128820890 for ; Thu, 18 Jun 2020 15:41:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731795AbgFRPl0 (ORCPT ); Thu, 18 Jun 2020 11:41:26 -0400 Received: from lhrrgout.huawei.com ([185.176.76.210]:2328 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731736AbgFRPkx (ORCPT ); Thu, 18 Jun 2020 11:40:53 -0400 Received: from lhreml715-chm.china.huawei.com (unknown [172.18.7.106]) by Forcepoint Email with ESMTP id 69FA963F7BC3307C754F; Thu, 18 Jun 2020 16:40:51 +0100 (IST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.90.32) by lhreml715-chm.china.huawei.com (10.201.108.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Thu, 18 Jun 2020 16:40:50 +0100 From: Shiju Jose To: , , , , , , , , , , , , , CC: , , , Subject: [PATCH v10 1/2] ACPI / APEI: Add support to notify the vendor specific HW errors Date: Thu, 18 Jun 2020 16:38:22 +0100 Message-ID: <20200618153823.588-2-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200618153823.588-1-shiju.jose@huawei.com> References: <20200618153823.588-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.90.32] X-ClientProxiedBy: lhreml714-chm.china.huawei.com (10.201.108.65) To lhreml715-chm.china.huawei.com (10.201.108.66) X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to report the vendor specific non-fatal HW errors to the drivers for the error recovery. The interface functions ghes_register_event_notifier() and ghes_unregister_event_notifier() enables the drivers to register and unregister the vendor specific error handlers. The interface uses work queue for queuing each vendor-specific error record and uses blocking notifier chain, in the work function, to report the error to the registered drivers. The drivers should match the section type of the error record before processing the error data. Signed-off-by: Shiju Jose Reviewed-by: Bjorn Helgaas --- drivers/acpi/apei/ghes.c | 123 +++++++++++++++++++++++++++++++++++++++ include/acpi/ghes.h | 29 +++++++++ 2 files changed, 152 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 81bf71b10d44..b6dc4eaa6345 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -64,6 +65,7 @@ #define GHES_ESTATUS_CACHES_SIZE 4 #define GHES_ESTATUS_IN_CACHE_MAX_NSEC 10000000000ULL + /* Prevent too many caches are allocated because of RCU */ #define GHES_ESTATUS_CACHE_ALLOCED_MAX (GHES_ESTATUS_CACHES_SIZE * 3 / 2) @@ -88,6 +90,10 @@ #define FIX_APEI_GHES_SDEI_CRITICAL __end_of_fixed_addresses #endif +#define GHES_EVENT_RING_SIZE 256 +#define GHES_EVENT_GDATA_POOL_MIN_ALLOC_ORDER 3 +#define GHES_EVENT_GDATA_POOL_MIN_SIZE 65536 + static inline bool is_hest_type_generic_v2(struct ghes *ghes) { return ghes->generic->header.type == ACPI_HEST_TYPE_GENERIC_ERROR_V2; @@ -123,6 +129,19 @@ static DEFINE_MUTEX(ghes_list_mutex); */ static DEFINE_SPINLOCK(ghes_notify_lock_irq); +struct ghes_event_entry { + struct acpi_hest_generic_data *gdata; + int error_severity; +}; + +static DEFINE_KFIFO(ghes_event_ring, struct ghes_event_entry, + GHES_EVENT_RING_SIZE); + +static DEFINE_SPINLOCK(ghes_event_ring_lock); + +static struct gen_pool *ghes_event_gdata_pool; +static unsigned long ghes_event_gdata_pool_size_request; + static struct gen_pool *ghes_estatus_pool; static unsigned long ghes_estatus_pool_size_request; @@ -183,6 +202,38 @@ int ghes_estatus_pool_init(int num_ghes) return -ENOMEM; } +static int ghes_event_gdata_pool_init(void) +{ + unsigned long addr, len; + int rc; + + ghes_event_gdata_pool = gen_pool_create(GHES_EVENT_GDATA_POOL_MIN_ALLOC_ORDER, -1); + if (!ghes_event_gdata_pool) + return -ENOMEM; + + if (ghes_event_gdata_pool_size_request < GHES_EVENT_GDATA_POOL_MIN_SIZE) + ghes_event_gdata_pool_size_request = GHES_EVENT_GDATA_POOL_MIN_SIZE; + + len = ghes_event_gdata_pool_size_request; + addr = (unsigned long)vmalloc(PAGE_ALIGN(len)); + if (!addr) + goto err_pool_alloc; + + rc = gen_pool_add(ghes_event_gdata_pool, addr, PAGE_ALIGN(len), -1); + if (rc) + goto err_pool_add; + + return 0; + +err_pool_add: + vfree((void *)addr); + +err_pool_alloc: + gen_pool_destroy(ghes_event_gdata_pool); + + return -ENOMEM; +} + static int map_gen_v2(struct ghes *ghes) { return apei_map_generic_address(&ghes->generic_v2->read_ack_register); @@ -242,6 +293,10 @@ static struct ghes *ghes_new(struct acpi_hest_generic *generic) goto err_unmap_status_addr; } + ghes_event_gdata_pool_size_request += generic->records_to_preallocate * + generic->max_sections_per_record * + generic->max_raw_data_length; + return ghes; err_unmap_status_addr: @@ -511,6 +566,69 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata) #endif } +static BLOCKING_NOTIFIER_HEAD(ghes_event_notify_list); + +/** + * ghes_register_event_notifier - register an event notifier + * for the non-fatal HW errors.Presently supported to notify + * the vendor-specific HW errors only, though it can be used to + * notify the standard errors also. + * @nb: pointer to the notifier_block structure of the event handler. + * + * return 0 : SUCCESS, non-zero : FAIL + */ +int ghes_register_event_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&ghes_event_notify_list, nb); +} +EXPORT_SYMBOL_GPL(ghes_register_event_notifier); + +/** + * ghes_unregister_event_notifier - unregister the previously + * registered event notifier. + * @nb: pointer to the notifier_block structure of the event handler. + */ +void ghes_unregister_event_notifier(struct notifier_block *nb) +{ + blocking_notifier_chain_unregister(&ghes_event_notify_list, nb); +} +EXPORT_SYMBOL_GPL(ghes_unregister_event_notifier); + +static void ghes_event_work_func(struct work_struct *work) +{ + struct ghes_event_entry entry; + u32 len; + + while (kfifo_get(&ghes_event_ring, &entry)) { + blocking_notifier_call_chain(&ghes_event_notify_list, + entry.error_severity, + entry.gdata); + len = acpi_hest_get_record_size(entry.gdata); + gen_pool_free(ghes_event_gdata_pool, (unsigned long)entry.gdata, len); + } +} + +static DECLARE_WORK(ghes_event_work, ghes_event_work_func); + +static void ghes_handle_non_standard_event(struct acpi_hest_generic_data *gdata, + int sev) +{ + u32 len; + struct ghes_event_entry event_entry; + + len = acpi_hest_get_record_size(gdata); + event_entry.gdata = (void *)gen_pool_alloc(ghes_event_gdata_pool, len); + if (!event_entry.gdata) + return; + + memcpy(event_entry.gdata, gdata, len); + event_entry.error_severity = sev; + if (kfifo_in_spinlocked(&ghes_event_ring, &event_entry, 1, &ghes_event_ring_lock)) + schedule_work(&ghes_event_work); + else + pr_warn(GHES_PFX "event notify queue full\n"); +} + static bool ghes_do_proc(struct ghes *ghes, const struct acpi_hest_generic_status *estatus) { @@ -549,6 +667,7 @@ static bool ghes_do_proc(struct ghes *ghes, } else { void *err = acpi_hest_get_payload(gdata); + ghes_handle_non_standard_event(gdata, sev); log_non_standard_event(sec_type, fru_id, fru_text, sec_sev, err, gdata->error_data_length); @@ -1385,6 +1504,10 @@ static int __init ghes_init(void) else pr_info(GHES_PFX "Failed to enable APEI firmware first mode.\n"); + rc = ghes_event_gdata_pool_init(); + if (rc) + pr_warn(GHES_PFX "non-fatal vendor-specific errors not being notified\n"); + return 0; err: return rc; diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index 517a5231cc1b..37a48ce13499 100644 --- a/include/acpi/ghes.h +++ b/include/acpi/ghes.h @@ -53,6 +53,35 @@ enum { GHES_SEV_PANIC = 0x3, }; +#ifdef CONFIG_ACPI_APEI_GHES +/** + * ghes_register_event_notifier - register an event notifier + * for the non-fatal HW errors.Presently supported to notify + * the vendor-specific HW errors only, though it can be used to notify + * the standard errors also. + * @nb: pointer to the notifier_block structure of the event notifier. + * + * Return : 0 - SUCCESS, non-zero - FAIL. + */ +int ghes_register_event_notifier(struct notifier_block *nb); + +/** + * ghes_unregister_event_notifier - unregister the previously + * registered event notifier. + * @nb: pointer to the notifier_block structure of the event notifier. + */ +void ghes_unregister_event_notifier(struct notifier_block *nb); +#else +static inline int ghes_register_event_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} + +static inline void ghes_unregister_event_notifier(struct notifier_block *nb) +{ +} +#endif + int ghes_estatus_pool_init(int num_ghes); /* From drivers/edac/ghes_edac.c */ From patchwork Thu Jun 18 15:40:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11612613 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40EFD14E3 for ; Thu, 18 Jun 2020 15:43:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2636620890 for ; Thu, 18 Jun 2020 15:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731638AbgFRPnA (ORCPT ); Thu, 18 Jun 2020 11:43:00 -0400 Received: from lhrrgout.huawei.com ([185.176.76.210]:2329 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731617AbgFRPmz (ORCPT ); Thu, 18 Jun 2020 11:42:55 -0400 Received: from lhreml715-chm.china.huawei.com (unknown [172.18.7.107]) by Forcepoint Email with ESMTP id 1EEDA7D2836602DCFE8C; Thu, 18 Jun 2020 16:42:54 +0100 (IST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.90.32) by lhreml715-chm.china.huawei.com (10.201.108.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Thu, 18 Jun 2020 16:42:53 +0100 From: Shiju Jose To: , , , , , , , , , , , , , CC: , , , , Andy Shevchenko Subject: [PATCH v10 2/2] PCI: hip: Add handling of HiSilicon HIP PCIe controller errors Date: Thu, 18 Jun 2020 16:40:51 +0100 Message-ID: <20200618154051.639-3-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.47.90.32] X-ClientProxiedBy: lhreml714-chm.china.huawei.com (10.201.108.65) To lhreml715-chm.china.huawei.com (10.201.108.66) X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Yicong Yang The HiSilicon HIP PCIe controller is capable of handling errors on root port and perform port reset separately at each root port. Add error handling driver for HIP PCIe controller to log and report recoverable errors. Perform root port reset and restore link status after the recovery. Following are some of the PCIe controller's recoverable errors 1. completion transmission timeout error. 2. CRS retry counter over the threshold error. 3. ECC 2 bit errors 4. AXI bresponse/rresponse errors etc. The driver placed in the drivers/pci/controller/ because the HIP PCIe controller does not use DWC ip. Signed-off-by: Yicong Yang Signed-off-by: Shiju Jose Reviewed-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko --- drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-hisi-error.c | 336 +++++++++++++++++++++++++++++++ 3 files changed, 345 insertions(+) create mode 100644 drivers/pci/controller/pcie-hisi-error.c --- drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-hisi-error.c | 327 +++++++++++++++++++++++ 3 files changed, 336 insertions(+) create mode 100644 drivers/pci/controller/pcie-hisi-error.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index adddf21fa381..b7949b37c029 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -286,6 +286,14 @@ config PCI_LOONGSON Say Y here if you want to enable PCI controller support on Loongson systems. +config PCIE_HISI_ERR + depends on ARM64 || COMPILE_TEST + depends on ACPI + bool "HiSilicon HIP PCIe controller error handling driver" + help + Say Y here if you want error handling support + for the PCIe controller's errors on HiSilicon HIP SoCs + source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig" source "drivers/pci/controller/cadence/Kconfig" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index efd9733ead26..90afd865bf6b 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o +obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ obj-y += mobiveil/ diff --git a/drivers/pci/controller/pcie-hisi-error.c b/drivers/pci/controller/pcie-hisi-error.c new file mode 100644 index 000000000000..3cfcc31568f0 --- /dev/null +++ b/drivers/pci/controller/pcie-hisi-error.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for handling the PCIe controller errors on + * HiSilicon HIP SoCs. + * + * Copyright (c) 2020 HiSilicon Limited. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* HISI PCIe controller error definitions */ +#define HISI_PCIE_ERR_MISC_REGS 33 + +#define HISI_PCIE_LOCAL_VALID_VERSION BIT(0) +#define HISI_PCIE_LOCAL_VALID_SOC_ID BIT(1) +#define HISI_PCIE_LOCAL_VALID_SOCKET_ID BIT(2) +#define HISI_PCIE_LOCAL_VALID_NIMBUS_ID BIT(3) +#define HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID BIT(4) +#define HISI_PCIE_LOCAL_VALID_CORE_ID BIT(5) +#define HISI_PCIE_LOCAL_VALID_PORT_ID BIT(6) +#define HISI_PCIE_LOCAL_VALID_ERR_TYPE BIT(7) +#define HISI_PCIE_LOCAL_VALID_ERR_SEVERITY BIT(8) +#define HISI_PCIE_LOCAL_VALID_ERR_MISC 9 + +static guid_t hisi_pcie_sec_guid = + GUID_INIT(0xB2889FC9, 0xE7D7, 0x4F9D, + 0xA8, 0x67, 0xAF, 0x42, 0xE9, 0x8B, 0xE7, 0x72); + +/* + * We pass core id and core port id to the ACPI reset method to identify + * certain root port to reset, while the firmware reports sockets port + * id which occurs an error. Use the macros here to do the conversion + */ +#define HISI_PCIE_CORE_ID(v) ((v) >> 3) +#define HISI_PCIE_PORT_ID(core, v) (((v) >> 1) + ((core) << 3)) +#define HISI_PCIE_CORE_PORT_ID(v) (((v) & 7) << 1) + +struct hisi_pcie_error_data { + u64 val_bits; + u8 version; + u8 soc_id; + u8 socket_id; + u8 nimbus_id; + u8 sub_module_id; + u8 core_id; + u8 port_id; + u8 err_severity; + u16 err_type; + u8 reserv[2]; + u32 err_misc[HISI_PCIE_ERR_MISC_REGS]; +}; + +struct hisi_pcie_error_private { + struct notifier_block nb; + struct device *dev; +}; + +enum hisi_pcie_submodule_id { + HISI_PCIE_SUB_MODULE_ID_AP, + HISI_PCIE_SUB_MODULE_ID_TL, + HISI_PCIE_SUB_MODULE_ID_MAC, + HISI_PCIE_SUB_MODULE_ID_DL, + HISI_PCIE_SUB_MODULE_ID_SDI, +}; + +static const char * const hisi_pcie_sub_module[] = { + [HISI_PCIE_SUB_MODULE_ID_AP] = "AP Layer", + [HISI_PCIE_SUB_MODULE_ID_TL] = "TL Layer", + [HISI_PCIE_SUB_MODULE_ID_MAC] = "MAC Layer", + [HISI_PCIE_SUB_MODULE_ID_DL] = "DL Layer", + [HISI_PCIE_SUB_MODULE_ID_SDI] = "SDI Layer", +}; + +enum hisi_pcie_err_severity { + HISI_PCIE_ERR_SEV_RECOVERABLE, + HISI_PCIE_ERR_SEV_FATAL, + HISI_PCIE_ERR_SEV_CORRECTED, + HISI_PCIE_ERR_SEV_NONE, +}; + +static const char * const hisi_pcie_error_sev[] = { + [HISI_PCIE_ERR_SEV_RECOVERABLE] = "recoverable", + [HISI_PCIE_ERR_SEV_FATAL] = "fatal", + [HISI_PCIE_ERR_SEV_CORRECTED] = "corrected", + [HISI_PCIE_ERR_SEV_NONE] = "none", +}; + +static const char *hisi_pcie_get_string(const char * const *array, + size_t n, u32 id) +{ + u32 index; + + for (index = 0; index < n; index++) { + if (index == id && array[index]) + return array[index]; + } + + return "unknown"; +} + +static int hisi_pcie_port_reset(struct platform_device *pdev, + u32 chip_id, u32 port_id) +{ + struct device *dev = &pdev->dev; + acpi_handle handle = ACPI_HANDLE(dev); + union acpi_object arg[3]; + struct acpi_object_list arg_list; + acpi_status s; + unsigned long long data = 0; + + arg[0].type = ACPI_TYPE_INTEGER; + arg[0].integer.value = chip_id; + arg[1].type = ACPI_TYPE_INTEGER; + arg[1].integer.value = HISI_PCIE_CORE_ID(port_id); + arg[2].type = ACPI_TYPE_INTEGER; + arg[2].integer.value = HISI_PCIE_CORE_PORT_ID(port_id); + + arg_list.count = 3; + arg_list.pointer = arg; + + s = acpi_evaluate_integer(handle, "RST", &arg_list, &data); + if (ACPI_FAILURE(s)) { + dev_err(dev, "No RST method\n"); + return -EIO; + } + + if (data) { + dev_err(dev, "Failed to Reset\n"); + return -EIO; + } + + return 0; +} + +static int hisi_pcie_port_do_recovery(struct platform_device *dev, + u32 chip_id, u32 port_id) +{ + acpi_status s; + struct device *device = &dev->dev; + acpi_handle root_handle = ACPI_HANDLE(device); + struct acpi_pci_root *pci_root; + struct pci_bus *root_bus; + struct pci_dev *pdev; + u32 domain, busnr, devfn; + + s = acpi_get_parent(root_handle, &root_handle); + if (ACPI_FAILURE(s)) + return -ENODEV; + pci_root = acpi_pci_find_root(root_handle); + if (!pci_root) + return -ENODEV; + root_bus = pci_root->bus; + domain = pci_root->segment; + + busnr = root_bus->number; + devfn = PCI_DEVFN(port_id, 0); + pdev = pci_get_domain_bus_and_slot(domain, busnr, devfn); + if (!pdev) { + dev_info(device, "Fail to get root port %04x:%02x:%02x.%d device\n", + domain, busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); + return -ENODEV; + } + + pci_stop_and_remove_bus_device_locked(pdev); + pci_dev_put(pdev); + + if (hisi_pcie_port_reset(dev, chip_id, port_id)) + return -EIO; + + /* + * The initialization time of subordinate devices after + * hot reset is no more than 1s, which is required by + * the PCI spec v5.0 sec 6.6.1. The time will shorten + * if Readiness Notifications mechanisms are used. But + * wait 1s here to adapt any conditions. + */ + ssleep(1UL); + + /* add root port and downstream devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(root_bus); + pci_unlock_rescan_remove(); + + return 0; +} + +static void hisi_pcie_handle_error(struct platform_device *pdev, + const struct hisi_pcie_error_data *edata) +{ + struct device *dev = &pdev->dev; + int idx, rc; + + if (edata->val_bits == 0) { + dev_warn(dev, "%s: no valid error information\n", __func__); + return; + } + + dev_info(dev, "\nHISI : HIP : PCIe controller error\n"); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SOC_ID) + dev_info(dev, "Table version = %d\n", edata->version); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SOCKET_ID) + dev_info(dev, "Socket ID = %d\n", edata->socket_id); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_NIMBUS_ID) + dev_info(dev, "Nimbus ID = %d\n", edata->nimbus_id); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID) + dev_info(dev, "Sub Module = %s\n", + hisi_pcie_get_string(hisi_pcie_sub_module, + ARRAY_SIZE(hisi_pcie_sub_module), + edata->sub_module_id)); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_CORE_ID) + dev_info(dev, "Core ID = core%d\n", edata->core_id); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_PORT_ID) + dev_info(dev, "Port ID = port%d\n", edata->port_id); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_ERR_SEVERITY) + dev_info(dev, "Error severity = %s\n", + hisi_pcie_get_string(hisi_pcie_error_sev, + ARRAY_SIZE(hisi_pcie_error_sev), + edata->err_severity)); + if (edata->val_bits & HISI_PCIE_LOCAL_VALID_ERR_TYPE) + dev_info(dev, "Error type = 0x%x\n", edata->err_type); + + dev_info(dev, "Reg Dump:\n"); + idx = HISI_PCIE_LOCAL_VALID_ERR_MISC; + for_each_set_bit_from(idx, (const unsigned long *)&edata->val_bits, + HISI_PCIE_LOCAL_VALID_ERR_MISC + HISI_PCIE_ERR_MISC_REGS) + dev_info(dev, "ERR_MISC_%d = 0x%x\n", idx - HISI_PCIE_LOCAL_VALID_ERR_MISC, + edata->err_misc[idx]); + + if (edata->err_severity != HISI_PCIE_ERR_SEV_RECOVERABLE) + return; + + /* Recovery for the PCIe controller errors, try reset + * PCI port for the error recovery + */ + rc = hisi_pcie_port_do_recovery(pdev, edata->socket_id, + HISI_PCIE_PORT_ID(edata->core_id, edata->port_id)); + if (rc) + dev_info(dev, "fail to do hisi pcie port reset\n"); +} + +static int hisi_pcie_notify_error(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct acpi_hest_generic_data *gdata = data; + const struct hisi_pcie_error_data *error_data = acpi_hest_get_payload(gdata); + struct hisi_pcie_error_private *priv; + struct device *dev; + struct platform_device *pdev; + guid_t err_sec_guid; + u8 socket; + + import_guid(&err_sec_guid, gdata->section_type); + if (!guid_equal(&err_sec_guid, &hisi_pcie_sec_guid)) + return NOTIFY_DONE; + + priv = container_of(nb, struct hisi_pcie_error_private, nb); + dev = priv->dev; + + if (device_property_read_u8(dev, "socket", &socket)) + return NOTIFY_DONE; + + if (error_data->socket_id != socket) + return NOTIFY_DONE; + + pdev = container_of(dev, struct platform_device, dev); + hisi_pcie_handle_error(pdev, error_data); + + return NOTIFY_OK; +} + +static int hisi_pcie_error_handler_probe(struct platform_device *pdev) +{ + struct hisi_pcie_error_private *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->nb.notifier_call = hisi_pcie_notify_error; + priv->dev = &pdev->dev; + ret = ghes_register_event_notifier(&priv->nb); + if (ret) { + dev_err(&pdev->dev, + "Failed to register hisi_pcie_notify_error function\n"); + return ret; + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int hisi_pcie_error_handler_remove(struct platform_device *pdev) +{ + struct hisi_pcie_error_private *priv = platform_get_drvdata(pdev); + + ghes_unregister_event_notifier(&priv->nb); + kfree(priv); + + return 0; +} + +static const struct acpi_device_id hisi_pcie_acpi_match[] = { + { "HISI0361", 0 }, + { } +}; + +static struct platform_driver hisi_pcie_error_handler_driver = { + .driver = { + .name = "hisi-pcie-error-handler", + .acpi_match_table = hisi_pcie_acpi_match, + }, + .probe = hisi_pcie_error_handler_probe, + .remove = hisi_pcie_error_handler_remove, +}; +module_platform_driver(hisi_pcie_error_handler_driver); + +MODULE_DESCRIPTION("HiSilicon HIP PCIe controller error handling driver"); +MODULE_LICENSE("GPL v2");